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* [PATCH 0/1] RISC-V: i18n enablement on error messages
@ 2022-06-10  9:52 Tsukasa OI
  2022-06-10  9:52 ` [PATCH 1/1] RISC-V: Prepare i18n for required ISA extensions Tsukasa OI
  0 siblings, 1 reply; 3+ messages in thread
From: Tsukasa OI @ 2022-06-10  9:52 UTC (permalink / raw)
  To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu
  Cc: binutils

Hello,

This patchset contains i18n enablement.

When extensions are missing for an instruction, it will print an error
message like this:

    Error: unrecognized opcode `fence.i', extension `zifencei' required

This is formatted in gas/config/tc-riscv.c:

    as_bad ("%s `%s', extension `%s' required", error.msg,
            error.statement, error.missing_ext);

error.missing_ext is a return value from the function
`riscv_multi_subset_supports_ext' in bfd/elfxx-riscv.c.

If required "extension" IS simple, that's fine.  All we have to do
with i18n is to translate "%s `%s', extension `%s' required".
But if requirementS get complex, that's not that simple.  There are
13 complex strings representing required extensions:

    return "f' and `c";
    return "d' and `c";
    return "f' or `zfinx";
    return "d' or `zdinx";
    return "q' or `zqinx";
    return "zbb' or `zbkb";
    return "zbc' or `zbkc";
    return "zknd' or `zkne";
    return "v' or `zve64x' or `zve32x";
    return "v' or `zve64d' or `zve64f' or `zve32f";
    return "zfh' or 'zhinx";
    return "('d' and 'zfh') or 'zhinx";
    return "('q' and 'zfh') or 'zhinx";

For i18n, we have to translate words like "and" and "or".  In Japanese,
we should translate:
    "f' and `c"
to:
    "f' および `c"

This is simple (I replaced "and" with equivalent Japanese word "および").
But more complex requirements (e.g. involving V or Zfh) will need
natural sentense (that would depend on each language).

This patch wraps such 13 strings with _() for i18n enablement.
It will be a prerequisite to my future submission of quick Zhinx fixes
and larger Z{h,f,d,q}inx fixes.

Thanks,
Tsukasa




Tsukasa OI (1):
  RISC-V: Prepare i18n for required ISA extensions

 bfd/elfxx-riscv.c | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)


base-commit: 6a72edd8e26c670bbdce7aeae3c0c8f793fc8612
-- 
2.34.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

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2022-06-10  9:52 [PATCH 0/1] RISC-V: i18n enablement on error messages Tsukasa OI
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2022-06-22 10:35   ` Nelson Chu

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