* [PATCH 1/2] Exclude trap instructions for MIPS Allegrex @ 2023-06-22 23:25 david 2023-06-22 23:25 ` [PATCH 2/2] Adding missing MIPS Allegrex instruction david 2024-04-02 11:43 ` [PATCH 1/2] Exclude trap instructions for MIPS Allegrex YunQiang Su 0 siblings, 2 replies; 4+ messages in thread From: david @ 2023-06-22 23:25 UTC (permalink / raw) To: binutils From: David Guillen Fandos <david@davidgf.net> These instructions are not supported by the target even though they are part of the MIPS II specification. --- opcodes/mips-opc.c | 60 +++++++++++------------ gas/testsuite/gas/mips/mips.exp | 1 + gas/testsuite/gas/mips/allegrex-removed.s | 13 +++++ gas/testsuite/gas/mips/allegrex-removed.l | 13 +++++ 4 files changed, 57 insertions(+), 30 deletions(-) create mode 100644 gas/testsuite/gas/mips/allegrex-removed.s create mode 100644 gas/testsuite/gas/mips/allegrex-removed.l diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 2cc82010a4..39833cd45f 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -2028,21 +2028,21 @@ const struct mips_opcode mips_builtin_opcodes[] = {"synci", "o(b)", 0x041f0000, 0xfc1f0000, RD_2|SM, 0, I33, 0, 0 }, {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1, 0, 0 }, {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1, 0, 0 }, -{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* teqi */ -{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgei */ -{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgeiu */ -{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, 0 }, +{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* teqi */ +{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, AL }, +{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tgei */ +{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, AL }, +{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tgeiu */ +{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, AL }, {"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 }, {"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 }, {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, @@ -2055,21 +2055,21 @@ const struct mips_opcode mips_builtin_opcodes[] = {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, {"tlbgp", "", 0x42000010, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tlti */ -{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tltiu */ -{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tnei */ -{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, 0 }, +{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tlti */ +{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, AL }, +{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tltiu */ +{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, AL }, +{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, +{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tnei */ +{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, AL }, {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 91cf8b1107..bb249b3525 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -1628,6 +1628,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test "r5900-error-vu0" "-march=r5900" run_dump_test "allegrex" + run_list_test_arches "allegrex-removed" [mips_arch_list_matching allegrex] run_list_test_arches "ext-ill" [mips_arch_list_matching mips64r2] diff --git a/gas/testsuite/gas/mips/allegrex-removed.s b/gas/testsuite/gas/mips/allegrex-removed.s new file mode 100644 index 0000000000..8dac8a1fca --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex-removed.s @@ -0,0 +1,13 @@ + .set noreorder + teqi $11,1024 + tgei $11,1024 + tgeiu $11,1024 + tlti $11,1024 + tltiu $11,1024 + tnei $11,1024 + teq $1,$2 + tge $1,$2 + tgeu $1,$2 + tlt $1,$2 + tltu $1,$2 + tne $1,$2 diff --git a/gas/testsuite/gas/mips/allegrex-removed.l b/gas/testsuite/gas/mips/allegrex-removed.l new file mode 100644 index 0000000000..a77d4df2f1 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex-removed.l @@ -0,0 +1,13 @@ +.*: Assembler messages: +.*:2: Error: opcode not supported on this processor: .* \(.*\) `teqi \$11,1024' +.*:3: Error: opcode not supported on this processor: .* \(.*\) `tgei \$11,1024' +.*:4: Error: opcode not supported on this processor: .* \(.*\) `tgeiu \$11,1024' +.*:5: Error: opcode not supported on this processor: .* \(.*\) `tlti \$11,1024' +.*:6: Error: opcode not supported on this processor: .* \(.*\) `tltiu \$11,1024' +.*:7: Error: opcode not supported on this processor: .* \(.*\) `tnei \$11,1024' +.*:8: Error: opcode not supported on this processor: .* \(.*\) `teq \$1,\$2' +.*:9: Error: opcode not supported on this processor: .* \(.*\) `tge \$1,\$2' +.*:10: Error: opcode not supported on this processor: .* \(.*\) `tgeu \$1,\$2' +.*:11: Error: opcode not supported on this processor: .* \(.*\) `tlt \$1,\$2' +.*:12: Error: opcode not supported on this processor: .* \(.*\) `tltu \$1,\$2' +.*:13: Error: opcode not supported on this processor: .* \(.*\) `tne \$1,\$2' -- 2.40.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] Adding missing MIPS Allegrex instruction 2023-06-22 23:25 [PATCH 1/2] Exclude trap instructions for MIPS Allegrex david @ 2023-06-22 23:25 ` david 2024-04-02 11:46 ` YunQiang Su 2024-04-02 11:43 ` [PATCH 1/2] Exclude trap instructions for MIPS Allegrex YunQiang Su 1 sibling, 1 reply; 4+ messages in thread From: david @ 2023-06-22 23:25 UTC (permalink / raw) To: binutils From: David Guillen Fandos <david@davidgf.net> --- opcodes/mips-opc.c | 2 +- gas/testsuite/gas/mips/allegrex.s | 1 + gas/testsuite/gas/mips/allegrex.d | 3 ++- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 39833cd45f..4e0c58d600 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1030,7 +1030,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, {"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, -{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, +{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5|AL, 0, 0 }, {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, diff --git a/gas/testsuite/gas/mips/allegrex.s b/gas/testsuite/gas/mips/allegrex.s index c36745882d..df05f97ee4 100644 --- a/gas/testsuite/gas/mips/allegrex.s +++ b/gas/testsuite/gas/mips/allegrex.s @@ -40,6 +40,7 @@ mfdr $v0, $0 mfdr $v0, $1 mtdr $v1, $1 + dbreak dret # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... diff --git a/gas/testsuite/gas/mips/allegrex.d b/gas/testsuite/gas/mips/allegrex.d index d0f79671de..b535c6dbdc 100644 --- a/gas/testsuite/gas/mips/allegrex.d +++ b/gas/testsuite/gas/mips/allegrex.d @@ -46,5 +46,6 @@ Disassembly of section .text: 0x00000094 7002003d mfdr \$2,\$0 0x00000098 7002083d mfdr \$2,\$1 0x0000009c 7083083d mtdr \$3,\$1 -0x000000a0 7000003e dret +0x000000a0 7000003f dbreak +0x000000a4 7000003e dret \.\.\. -- 2.40.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] Adding missing MIPS Allegrex instruction 2023-06-22 23:25 ` [PATCH 2/2] Adding missing MIPS Allegrex instruction david @ 2024-04-02 11:46 ` YunQiang Su 0 siblings, 0 replies; 4+ messages in thread From: YunQiang Su @ 2024-04-02 11:46 UTC (permalink / raw) To: david; +Cc: binutils <david@davidgf.es> 于2023年6月23日周五 07:26写道： > > From: David Guillen Fandos <david@davidgf.net> > > --- > opcodes/mips-opc.c | 2 +- > gas/testsuite/gas/mips/allegrex.s | 1 + > gas/testsuite/gas/mips/allegrex.d | 3 ++- > 3 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c > index 39833cd45f..4e0c58d600 100644 > --- a/opcodes/mips-opc.c > +++ b/opcodes/mips-opc.c > @@ -1030,7 +1030,7 @@ const struct mips_opcode mips_builtin_opcodes[] = > {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, > {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, > {"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, > -{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, > +{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5|AL, 0, 0 }, This is the only instruction changed in this patch. I think that we may use a more detailed commit msg, such as: MIPS/Allegrex: Enable dbreak instruction Or something else. For the code, LGTM. > {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, > {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, > {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, > diff --git a/gas/testsuite/gas/mips/allegrex.s b/gas/testsuite/gas/mips/allegrex.s > index c36745882d..df05f97ee4 100644 > --- a/gas/testsuite/gas/mips/allegrex.s > +++ b/gas/testsuite/gas/mips/allegrex.s > @@ -40,6 +40,7 @@ > mfdr $v0, $0 > mfdr $v0, $1 > mtdr $v1, $1 > + dbreak > dret > > # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... > diff --git a/gas/testsuite/gas/mips/allegrex.d b/gas/testsuite/gas/mips/allegrex.d > index d0f79671de..b535c6dbdc 100644 > --- a/gas/testsuite/gas/mips/allegrex.d > +++ b/gas/testsuite/gas/mips/allegrex.d > @@ -46,5 +46,6 @@ Disassembly of section .text: > 0x00000094 7002003d mfdr \$2,\$0 > 0x00000098 7002083d mfdr \$2,\$1 > 0x0000009c 7083083d mtdr \$3,\$1 > -0x000000a0 7000003e dret > +0x000000a0 7000003f dbreak > +0x000000a4 7000003e dret > \.\.\. > -- > 2.40.1 > -- YunQiang Su ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] Exclude trap instructions for MIPS Allegrex 2023-06-22 23:25 [PATCH 1/2] Exclude trap instructions for MIPS Allegrex david 2023-06-22 23:25 ` [PATCH 2/2] Adding missing MIPS Allegrex instruction david @ 2024-04-02 11:43 ` YunQiang Su 1 sibling, 0 replies; 4+ messages in thread From: YunQiang Su @ 2024-04-02 11:43 UTC (permalink / raw) To: david; +Cc: binutils <david@davidgf.es> 于2023年6月23日周五 07:26写道： > > From: David Guillen Fandos <david@davidgf.net> > > These instructions are not supported by the target even though they are > part of the MIPS II specification. LGTM. > --- > opcodes/mips-opc.c | 60 +++++++++++------------ > gas/testsuite/gas/mips/mips.exp | 1 + > gas/testsuite/gas/mips/allegrex-removed.s | 13 +++++ > gas/testsuite/gas/mips/allegrex-removed.l | 13 +++++ > 4 files changed, 57 insertions(+), 30 deletions(-) > create mode 100644 gas/testsuite/gas/mips/allegrex-removed.s > create mode 100644 gas/testsuite/gas/mips/allegrex-removed.l > > diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c > index 2cc82010a4..39833cd45f 100644 > --- a/opcodes/mips-opc.c > +++ b/opcodes/mips-opc.c > @@ -2028,21 +2028,21 @@ const struct mips_opcode mips_builtin_opcodes[] = > {"synci", "o(b)", 0x041f0000, 0xfc1f0000, RD_2|SM, 0, I33, 0, 0 }, > {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1, 0, 0 }, > {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1, 0, 0 }, > -{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, > -{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* teqi */ > -{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, 0 }, > -{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, > -{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgei */ > -{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, 0 }, > -{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, > -{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgeiu */ > -{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, 0 }, > +{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, > +{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* teqi */ > +{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, AL }, > +{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, > +{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tgei */ > +{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, AL }, > +{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, > +{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tgeiu */ > +{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, AL }, > {"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 }, > {"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 }, > {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, > @@ -2055,21 +2055,21 @@ const struct mips_opcode mips_builtin_opcodes[] = > {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, > {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, > {"tlbgp", "", 0x42000010, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, > -{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, > -{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tlti */ > -{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, 0 }, > -{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, > -{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tltiu */ > -{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, 0 }, > -{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, > -{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, > -{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tnei */ > -{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, 0 }, > +{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, > +{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tlti */ > +{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, AL }, > +{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, > +{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tltiu */ > +{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, AL }, > +{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, > +{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL }, > +{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, /* tnei */ > +{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, AL }, > {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, > {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, > {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, > diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp > index 91cf8b1107..bb249b3525 100644 > --- a/gas/testsuite/gas/mips/mips.exp > +++ b/gas/testsuite/gas/mips/mips.exp > @@ -1628,6 +1628,7 @@ if { [istarget mips*-*-vxworks*] } { > run_list_test "r5900-error-vu0" "-march=r5900" > > run_dump_test "allegrex" > + run_list_test_arches "allegrex-removed" [mips_arch_list_matching allegrex] > > run_list_test_arches "ext-ill" [mips_arch_list_matching mips64r2] > > diff --git a/gas/testsuite/gas/mips/allegrex-removed.s b/gas/testsuite/gas/mips/allegrex-removed.s > new file mode 100644 > index 0000000000..8dac8a1fca > --- /dev/null > +++ b/gas/testsuite/gas/mips/allegrex-removed.s > @@ -0,0 +1,13 @@ > + .set noreorder > + teqi $11,1024 > + tgei $11,1024 > + tgeiu $11,1024 > + tlti $11,1024 > + tltiu $11,1024 > + tnei $11,1024 > + teq $1,$2 > + tge $1,$2 > + tgeu $1,$2 > + tlt $1,$2 > + tltu $1,$2 > + tne $1,$2 > diff --git a/gas/testsuite/gas/mips/allegrex-removed.l b/gas/testsuite/gas/mips/allegrex-removed.l > new file mode 100644 > index 0000000000..a77d4df2f1 > --- /dev/null > +++ b/gas/testsuite/gas/mips/allegrex-removed.l > @@ -0,0 +1,13 @@ > +.*: Assembler messages: > +.*:2: Error: opcode not supported on this processor: .* \(.*\) `teqi \$11,1024' > +.*:3: Error: opcode not supported on this processor: .* \(.*\) `tgei \$11,1024' > +.*:4: Error: opcode not supported on this processor: .* \(.*\) `tgeiu \$11,1024' > +.*:5: Error: opcode not supported on this processor: .* \(.*\) `tlti \$11,1024' > +.*:6: Error: opcode not supported on this processor: .* \(.*\) `tltiu \$11,1024' > +.*:7: Error: opcode not supported on this processor: .* \(.*\) `tnei \$11,1024' > +.*:8: Error: opcode not supported on this processor: .* \(.*\) `teq \$1,\$2' > +.*:9: Error: opcode not supported on this processor: .* \(.*\) `tge \$1,\$2' > +.*:10: Error: opcode not supported on this processor: .* \(.*\) `tgeu \$1,\$2' > +.*:11: Error: opcode not supported on this processor: .* \(.*\) `tlt \$1,\$2' > +.*:12: Error: opcode not supported on this processor: .* \(.*\) `tltu \$1,\$2' > +.*:13: Error: opcode not supported on this processor: .* \(.*\) `tne \$1,\$2' > -- > 2.40.1 > -- YunQiang Su ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2024-04-02 11:46 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-06-22 23:25 [PATCH 1/2] Exclude trap instructions for MIPS Allegrex david 2023-06-22 23:25 ` [PATCH 2/2] Adding missing MIPS Allegrex instruction david 2024-04-02 11:46 ` YunQiang Su 2024-04-02 11:43 ` [PATCH 1/2] Exclude trap instructions for MIPS Allegrex YunQiang Su
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