* [committed 07/10] arc: Add new opcode functions for ARCv3 ISA.
2023-09-25 8:35 [committed 01/10] arc: Add new GAS tests for ARCv3 Claudiu Zissulescu
` (4 preceding siblings ...)
2023-09-25 8:35 ` [committed 06/10] arc: Update ARC's Gnu Assembler backend with ARCv3 ISA Claudiu Zissulescu
@ 2023-09-25 8:35 ` Claudiu Zissulescu
2023-09-25 8:35 ` [committed 08/10] arc: New ARCv3 ISA instruction table Claudiu Zissulescu
` (4 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Claudiu Zissulescu @ 2023-09-25 8:35 UTC (permalink / raw)
To: binutils; +Cc: fbedard
opcodes/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
Cupertino Miranda <cmiranda@synopsys.com>
* opcodes/Makefile.am: Add ARC64 opcode file.
* opcodes/Makefile.in: Regenerate.
* opcodes/arc-opc.c: Move the common functionality to
arcxx-opc.inc. Keep only ARCv2 ARCv1 specifics.
* opcodes/arc-ext-tbl.h: Deleted file.
* opcodes/arcxx-opc.inc: New file.
* opcodes/arc64-opc.c: Likewise.
* opcodes/arc-fxi.h (insert_uimm9_a32_11_s): New function.
(extract_uimm9_a32_11_s): Likewise.
(insert_uimm10_13_s): Likewise.
(extract_uimm10_13_s): Likewise.
* opcodes/configure: Regenerate.
* opcodes/configure.ac: Add ARC64 target.
* opcodes/disassemble.c: Likewise.
* opcodes/arc-dis.c (regmod_t): New type.
(regmods): New structure.
(fpnames): New strings with fp-regs name.
(REG_PCL, REG_LIMM, REG_LIMM_S, REG_U32, REG_S32): New defines.
(getregname): New function.
(find_format_from_table): Discriminate between signed and unsigned
32bit immediates.
(find_format): Handle extract function for flags.
(arc_insn_length): Update insn lengths to various architectures.
(print_insn_arc): Update printing for various ARC architectures.
* opcodes/arc-flag-classes.def: New file.
* opcodes/arc-flag.def: New file.
* opcodes/arc-operands.def: New file.
* opcodes/arc-regs.h: Changed.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
---
opcodes/Makefile.am | 1 +
opcodes/Makefile.in | 2 +
opcodes/arc-dis.c | 290 +++-
opcodes/arc-ext-tbl.h | 124 --
opcodes/arc-flag-classes.def | 125 ++
opcodes/arc-flag.def | 179 ++
opcodes/arc-fxi.h | 60 +
opcodes/arc-opc.c | 2990 ++--------------------------------
opcodes/arc-operands.def | 502 ++++++
opcodes/arc-regs.h | 8 +-
opcodes/arc64-opc.c | 834 ++++++++++
opcodes/arcxx-opc.inc | 1840 +++++++++++++++++++++
opcodes/configure | 1 +
opcodes/configure.ac | 1 +
opcodes/disassemble.c | 6 +
15 files changed, 3872 insertions(+), 3091 deletions(-)
delete mode 100644 opcodes/arc-ext-tbl.h
create mode 100644 opcodes/arc-flag-classes.def
create mode 100644 opcodes/arc-flag.def
create mode 100644 opcodes/arc-operands.def
create mode 100644 opcodes/arc64-opc.c
create mode 100644 opcodes/arcxx-opc.inc
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 5804dd1ab38..effcd41b6ae 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -116,6 +116,7 @@ TARGET32_LIBOPCODES_CFILES = \
arc-dis.c \
arc-ext.c \
arc-opc.c \
+ arc64-opc.c \
arm-dis.c \
avr-dis.c \
bfin-dis.c \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 29c26263061..f207cf57f44 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -508,6 +508,7 @@ TARGET32_LIBOPCODES_CFILES = \
arc-dis.c \
arc-ext.c \
arc-opc.c \
+ arc64-opc.c \
arm-dis.c \
avr-dis.c \
bfin-dis.c \
@@ -876,6 +877,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-ext.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-opc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc64-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avr-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bfin-dis.Plo@am__quote@
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 59b668ff64e..dbcd0dbd7f8 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -60,7 +60,7 @@ struct arc_disassemble_info
/* Instruction length w/o limm field. */
unsigned insn_len;
- /* TRUE if we have limm. */
+ /* true if we have limm. */
bool limm_p;
/* LIMM value, if exists. */
@@ -85,7 +85,7 @@ static const char * const regnames[64] =
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
- "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
+ "r24", "r25", "r26", "fp", "sp", "ilink", "r30", "blink",
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
@@ -93,6 +93,29 @@ static const char * const regnames[64] =
"r56", "r57", "r58", "r59", "lp_count", "reserved", "LIMM", "pcl"
};
+typedef struct regmod
+{
+ const unsigned int index;
+ const unsigned int isa;
+ const char *rname;
+} regmod_t;
+
+static regmod_t regmods[] =
+{
+ { 26, ARC_OPCODE_ARCV1 | ARC_OPCODE_ARCV2, "gp" },
+ { 29, ARC_OPCODE_ARCV1, "ilink1" },
+ { 30, ARC_OPCODE_ARCV1, "ilink2" },
+ { 0, ARC_OPCODE_NONE, 0 }
+};
+
+static const char * const fpnames[32] =
+{
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
+};
+
static const char * const addrtypenames[ARC_NUM_ADDRTYPES] =
{
"bd", "jid", "lbd", "mbd", "sd", "sm", "xa", "xd",
@@ -126,7 +149,6 @@ static unsigned enforced_isa_mask = ARC_OPCODE_NONE;
static bool print_hex = false;
/* Macros section. */
-
#ifdef DEBUG
# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
#else
@@ -140,8 +162,29 @@ static bool print_hex = false;
#define BITS(word,s,e) (((word) >> (s)) & ((1ull << ((e) - (s)) << 1) - 1))
#define OPCODE_32BIT_INSN(word) (BITS ((word), 27, 31))
+#define REG_PCL 63
+#define REG_LIMM 62
+#define REG_LIMM_S 30
+#define REG_U32 62
+#define REG_S32 60
+
/* Functions implementation. */
+static const char *
+getregname (unsigned int index, unsigned int isa_mask)
+{
+ regmod_t *iregmods = regmods;
+ while (iregmods->rname)
+ {
+ if (index == iregmods->index
+ && (isa_mask & iregmods->isa))
+ return iregmods->rname;
+ iregmods ++;
+ }
+
+ return regnames[index % 64];
+}
+
/* Initialize private data. */
static bool
init_arc_disasm_info (struct disassemble_info *info)
@@ -170,7 +213,7 @@ add_to_decodelist (insn_class_t insn_class,
decodelist = t;
}
-/* Return TRUE if we need to skip the opcode from being
+/* Return true if we need to skip the opcode from being
disassembled. */
static bool
@@ -277,7 +320,7 @@ find_format_from_table (struct disassemble_info *info,
if (arc_opcode_len (opcode) != (int) insn_len)
continue;
- if ((insn & opcode->mask) != opcode->opcode)
+ if ((insn & opcode->mask) != (opcode->mask & opcode->opcode))
continue;
*has_limm = false;
@@ -285,7 +328,7 @@ find_format_from_table (struct disassemble_info *info,
/* Possible candidate, check the operands. */
for (opidx = opcode->operands; *opidx; opidx++)
{
- int value, limmind;
+ int value, slimmind;
const struct arc_operand *operand = &arc_operands[*opidx];
if (operand->flags & ARC_OPERAND_FAKE)
@@ -296,19 +339,19 @@ find_format_from_table (struct disassemble_info *info,
else
value = (insn >> operand->shift) & ((1ull << operand->bits) - 1);
- /* Check for LIMM indicator. If it is there, then make sure
- we pick the right format. */
- limmind = (isa_mask & ARC_OPCODE_ARCV2) ? 0x1E : 0x3E;
+ /* Check for (short) LIMM indicator. If it is there, then
+ make sure we pick the right format. */
+ slimmind = (isa_mask & ARC_OPCODE_ARCVx) ? REG_LIMM_S : REG_LIMM;
if (operand->flags & ARC_OPERAND_IR
&& !(operand->flags & ARC_OPERAND_LIMM))
- {
- if ((value == 0x3E && insn_len == 4)
- || (value == limmind && insn_len == 2))
- {
- invalid = true;
- break;
- }
- }
+ if ((value == REG_LIMM && insn_len == 4)
+ || (value == slimmind && insn_len == 2)
+ || (isa_mask & ARC_OPCODE_ARC64
+ && (value == REG_S32) && (insn_len == 4)))
+ {
+ invalid = true;
+ break;
+ }
if (operand->flags & ARC_OPERAND_LIMM
&& !(operand->flags & ARC_OPERAND_DUPLICATE))
@@ -338,11 +381,15 @@ find_format_from_table (struct disassemble_info *info,
for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
{
+ bool tmp = false;
const struct arc_flag_operand *flg_operand =
&arc_flag_operands[*flgopridx];
- value = (insn >> flg_operand->shift)
- & ((1 << flg_operand->bits) - 1);
+ if (cl_flags->extract)
+ value = (*cl_flags->extract)(insn, &tmp);
+ else
+ value = (insn >> flg_operand->shift)
+ & ((1 << flg_operand->bits) - 1);
if (value == flg_operand->code)
foundA = 1;
if (value)
@@ -396,15 +443,15 @@ find_format_from_table (struct disassemble_info *info,
the found opcode requires a LIMM then the LIMM value will be loaded into a
field of ITER.
- This function returns TRUE in almost all cases, FALSE is reserved to
+ This function returns true in almost all cases, false is reserved to
indicate an error (failing to find an opcode is not an error) a returned
- result of FALSE would indicate that the disassembler can't continue.
+ result of false would indicate that the disassembler can't continue.
- If no matching opcode is found then the returned result will be TRUE, the
+ If no matching opcode is found then the returned result will be true, the
value placed into OPCODE_RESULT will be NULL, ITER will be undefined, and
INSN_LEN will be unchanged.
- If a matching opcode is found, then the returned result will be TRUE, the
+ If a matching opcode is found, then the returned result will be true, the
opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be increased by
4 if the instruction requires a LIMM, and the LIMM value will have been
loaded into a field of ITER. Finally, ITER will have been initialised so
@@ -421,11 +468,14 @@ find_format (bfd_vma memaddr,
struct arc_operand_iterator * iter)
{
const struct arc_opcode *opcode = NULL;
+ const struct arc_opcode *opcodeList = NULL;
bool needs_limm = false;
const extInstruction_t *einsn, *i;
unsigned limm = 0;
struct arc_disassemble_info *arc_infop = info->private_data;
+ opcodeList = arc_opcodes;
+
/* First, try the extension instructions. */
if (*insn_len == 4)
{
@@ -452,7 +502,7 @@ find_format (bfd_vma memaddr,
/* Then, try finding the first match in the opcode table. */
if (opcode == NULL)
- opcode = find_format_from_table (info, arc_opcodes, insn, *insn_len,
+ opcode = find_format_from_table (info, opcodeList, insn, *insn_len,
isa_mask, &needs_limm, true);
if (opcode != NULL && needs_limm)
@@ -542,8 +592,14 @@ print_flags (const struct arc_opcode *opcode,
if (!flg_operand->favail)
continue;
- value = (insn[0] >> flg_operand->shift)
- & ((1 << flg_operand->bits) - 1);
+ if (cl_flags->extract)
+ {
+ bool tmp = false;
+ value = (*cl_flags->extract)(insn[0], &tmp);
+ }
+ else
+ value = (insn[0] >> flg_operand->shift)
+ & ((1 << flg_operand->bits) - 1);
if (value == flg_operand->code)
{
/* FIXME!: print correctly nt/t flag. */
@@ -646,34 +702,59 @@ arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
{
bfd_byte major_opcode = msb >> 3;
- switch (info->mach)
+ switch (info->arch)
{
- case bfd_mach_arc_arc700:
- /* The nps400 extension set requires this special casing of the
- instruction length calculation. Right now this is not causing any
- problems as none of the known extensions overlap in opcode space,
- but, if they ever do then we might need to start carrying
- information around in the elf about which extensions are in use. */
- if (major_opcode == 0xb)
- {
- bfd_byte minor_opcode = lsb & 0x1f;
+ case bfd_arch_arc:
+ switch (info->mach)
+ {
+ case bfd_mach_arc_arc700:
+ /* The nps400 extension set requires this special casing of
+ the instruction length calculation. Right now this is
+ not causing any problems as none of the known extensions
+ overlap in opcode space, but, if they ever do then we
+ might need to start carrying information around in the
+ elf about which extensions are in use. */
+ if (major_opcode == 0xb)
+ {
+ bfd_byte minor_opcode = lsb & 0x1f;
- if (minor_opcode < 4)
- return 6;
- else if (minor_opcode == 0x10 || minor_opcode == 0x11)
- return 8;
- }
- if (major_opcode == 0xa)
- {
- return 8;
- }
- /* Fall through. */
- case bfd_mach_arc_arc600:
- return (major_opcode > 0xb) ? 2 : 4;
+ if (minor_opcode < 4)
+ return 6;
+ else if (minor_opcode == 0x10 || minor_opcode == 0x11)
+ return 8;
+ }
+ if (major_opcode == 0xa)
+ {
+ return 8;
+ }
+ /* Fall through. */
+ case bfd_mach_arc_arc600:
+ return (major_opcode > 0xb) ? 2 : 4;
+ break;
+
+ case bfd_mach_arc_arcv2:
+ return (major_opcode > 0x7) ? 2 : 4;
+ break;
+
+ default:
+ return 0;
+ }
break;
- case bfd_mach_arc_arcv2:
- return (major_opcode > 0x7) ? 2 : 4;
+ case bfd_arch_arc64:
+ switch (info->mach)
+ {
+ case bfd_mach_arcv3_32:
+ case bfd_mach_arcv3_64:
+ if (major_opcode == 0x0b
+ || major_opcode == 0x0d
+ || major_opcode == 0x1c)
+ return 4;
+ return (major_opcode > 0x7) ? 2 : 4;
+
+ default:
+ return 0;
+ }
break;
default:
@@ -723,8 +804,8 @@ extract_operand_value (const struct arc_operand *operand,
return value;
}
-/* Find the next operand, and the operands value from ITER. Return TRUE if
- there is another operand, otherwise return FALSE. If there is an
+/* Find the next operand, and the operands value from ITER. Return true if
+ there is another operand, otherwise return false. If there is an
operand returned then the operand is placed into OPERAND, and the value
into VALUE. If there is no operand returned then OPERAND and VALUE are
unchanged. */
@@ -808,14 +889,18 @@ parse_option (const char *option)
}
#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARC600, "ARC600" }
+ { #NAME, ARC_OPCODE_ARC600, "ARC600" },
#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARC700, "ARC700" }
+ { #NAME, ARC_OPCODE_ARC700, "ARC700" },
#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARCv2EM, "ARC EM" }
+ { #NAME, ARC_OPCODE_ARCv2EM, "ARC EM" },
#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARCv2HS, "ARC HS" }
-#define ARC_CPU_TYPE_NONE \
+ { #NAME, ARC_OPCODE_ARCv2HS, "ARC HS" },
+#define ARC_CPU_TYPE_A64x(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARC64, "ARC64" },
+#define ARC_CPU_TYPE_A32x(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARC64, "ARC32" },
+#define ARC_CPU_TYPE_NONE \
{ 0, 0, 0 }
/* A table of CPU names and opcode sets. */
@@ -950,7 +1035,8 @@ print_insn_arc (bfd_vma memaddr,
bool open_braket;
int size;
const struct arc_operand *operand;
- int value, vpcl;
+ int value;
+ bfd_vma vpcl;
struct arc_operand_iterator iter;
struct arc_disassemble_info *arc_infop;
bool rpcl = false, rset = false;
@@ -978,25 +1064,54 @@ print_insn_arc (bfd_vma memaddr,
if (info->section && info->section->owner)
header = elf_elfheader (info->section->owner);
- switch (info->mach)
+ switch (info->arch)
{
- case bfd_mach_arc_arc700:
- isa_mask = ARC_OPCODE_ARC700;
+ case bfd_arch_arc:
+ switch (info->mach)
+ {
+ case bfd_mach_arc_arc700:
+ isa_mask = ARC_OPCODE_ARC700;
+ break;
+
+ case bfd_mach_arc_arc600:
+ isa_mask = ARC_OPCODE_ARC600;
+ break;
+
+ case bfd_mach_arc_arcv2:
+ default:
+ isa_mask = ARC_OPCODE_ARCv2EM;
+ /* TODO: Perhaps remove definition of header since it is
+ only used at this location. */
+ if (header != NULL
+ && (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
+ isa_mask = ARC_OPCODE_ARCv2HS;
+ break;
+ }
break;
- case bfd_mach_arc_arc600:
- isa_mask = ARC_OPCODE_ARC600;
+ case bfd_arch_arc64:
+ switch (info->mach)
+ {
+ case bfd_mach_arcv3_64:
+ isa_mask = ARC_OPCODE_ARC64;
+ break;
+
+ case bfd_mach_arcv3_32:
+ isa_mask = ARC_OPCODE_ARC32;
+ break;
+
+ default:
+ /* xgettext:c-format */
+ opcodes_error_handler (_("unrecognised arc64 disassembler \
+variant"));
+ return -1;
+ }
break;
- case bfd_mach_arc_arcv2:
default:
- isa_mask = ARC_OPCODE_ARCv2EM;
- /* TODO: Perhaps remove definition of header since it is only used at
- this location. */
- if (header != NULL
- && (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
- isa_mask = ARC_OPCODE_ARCv2HS;
- break;
+ /* xgettext:c-format */
+ opcodes_error_handler (_("unrecognised disassembler architecture"));
+ return -1;
}
}
else
@@ -1289,8 +1404,10 @@ print_insn_arc (bfd_vma memaddr,
rpcl = true;
vpcl = value;
rset = true;
-
- info->target = (bfd_vma) (memaddr & ~3) + value;
+ if ((operand->flags & ARC_OPERAND_LIMM)
+ && (operand->flags & ARC_OPERAND_ALIGNED32))
+ vpcl <<= 2;
+ info->target = (bfd_vma) (memaddr & ~3) + vpcl;
}
else if (!(operand->flags & ARC_OPERAND_IR))
{
@@ -1303,10 +1420,15 @@ print_insn_arc (bfd_vma memaddr,
{
const char *rname;
- assert (value >=0 && value < 64);
+ assert (value >= 0 && value < 64);
rname = arcExtMap_coreRegName (value);
if (!rname)
- rname = regnames[value];
+ {
+ if (operand->flags & ARC_OPERAND_FP)
+ rname = fpnames[value & 0x1f];
+ else
+ rname = getregname (value, isa_mask);
+ }
(*info->fprintf_styled_func) (info->stream, dis_style_register,
"%s", rname);
@@ -1316,8 +1438,10 @@ print_insn_arc (bfd_vma memaddr,
if ((value & 0x01) == 0)
{
rname = arcExtMap_coreRegName (value + 1);
- if (!rname)
- rname = regnames[value + 1];
+ if (operand->flags & ARC_OPERAND_FP)
+ rname = fpnames[(value + 1) & 0x1f];
+ else
+ rname = getregname (value + 1, isa_mask);
}
else
rname = _("\nWarning: illegal use of double register "
@@ -1325,7 +1449,7 @@ print_insn_arc (bfd_vma memaddr,
(*info->fprintf_styled_func) (info->stream, dis_style_register,
"%s", rname);
}
- if (value == 63)
+ if (value == REG_PCL)
rpcl = true;
else
rpcl = false;
@@ -1339,8 +1463,12 @@ print_insn_arc (bfd_vma memaddr,
"%s", rname);
else
{
- (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
- "%#x", value);
+ if (operand->flags & ARC_OPERAND_SIGNED)
+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+ "%d@s32", value);
+ else
+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+ "%#x", value);
if (info->insn_type == dis_branch
|| info->insn_type == dis_jsr)
info->target = (bfd_vma) value;
@@ -1418,7 +1546,7 @@ print_insn_arc (bfd_vma memaddr,
= ARC_OPERAND_KIND_LIMM;
/* It is not important to have exactly the LIMM indicator
here. */
- arc_infop->operands[arc_infop->operands_count].value = 63;
+ arc_infop->operands[arc_infop->operands_count].value = REG_PCL;
}
else
{
diff --git a/opcodes/arc-ext-tbl.h b/opcodes/arc-ext-tbl.h
deleted file mode 100644
index d230b610e8c..00000000000
--- a/opcodes/arc-ext-tbl.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* ARC instruction defintions.
- Copyright (C) 2016-2023 Free Software Foundation, Inc.
-
- Contributed by Claudiu Zissulescu (claziss@synopsys.com)
-
- This file is part of libopcodes.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation,
- Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-/* Common combinations of FLAGS. */
-#define FLAGS_NONE { 0 }
-#define FLAGS_F { C_F }
-#define FLAGS_CC { C_CC }
-#define FLAGS_CCF { C_CC, C_F }
-
-/* Common combination of arguments. */
-#define ARG_NONE { 0 }
-#define ARG_32BIT_RARBRC { RA, RB, RC }
-#define ARG_32BIT_ZARBRC { ZA, RB, RC }
-#define ARG_32BIT_RBRBRC { RB, RBdup, RC }
-#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
-#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
-#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
-#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
-#define ARG_32BIT_RALIMMRC { RA, LIMM, RC }
-#define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
-#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC }
-#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
-
-#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM }
-#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 }
-#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 }
-
-#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 }
-#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup }
-#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup }
-
-#define ARG_32BIT_RBRC { RB, RC }
-#define ARG_32BIT_ZARC { ZA, RC }
-#define ARG_32BIT_RBU6 { RB, UIMM6_20 }
-#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 }
-#define ARG_32BIT_RBLIMM { RB, LIMM }
-#define ARG_32BIT_ZALIMM { ZA, LIMM }
-
-/* Macro to generate 2 operand extension instruction. */
-#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \
- { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBRC, FL }, \
- { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZARC, FL }, \
- { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBU6, FL }, \
- { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZAU6, FL }, \
- { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBLIMM, FL }, \
- { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMM, FL },
-
-#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
- EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F)
-
-/* Macro to generate 3 operand extesion instruction. */
-#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
- { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \
- ARG_32BIT_RARBRC, FLAGS_F }, \
- { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZARBRC, FLAGS_F }, \
- { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBRBRC, FLAGS_CCF }, \
- { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \
- ARG_32BIT_RARBU6, FLAGS_F }, \
- { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZARBU6, FLAGS_F }, \
- { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBRBU6, FLAGS_CCF }, \
- { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBRBS12, FLAGS_F }, \
- { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
- ARG_32BIT_RALIMMRC, FLAGS_F }, \
- { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
- ARG_32BIT_RARBLIMM, FLAGS_F }, \
- { NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMRC, FLAGS_F }, \
- { NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZARBLIMM, FLAGS_F }, \
- { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \
- { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \
- { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
- ARG_32BIT_RALIMMU6, FLAGS_F }, \
- { NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMU6, FLAGS_F }, \
- { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \
- { NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMS12, FLAGS_F }, \
- { NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \
- ARG_32BIT_RALIMMLIMM, FLAGS_F }, \
- { NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \
- { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMLIMM, FLAGS_CCF },
-
-/* Extension instruction declarations. */
-EXTINSN2OP ("dsp_fp_flt2i", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
-EXTINSN2OP ("dsp_fp_i2flt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 44)
-EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 45)
-
-EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 42)
-EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
diff --git a/opcodes/arc-flag-classes.def b/opcodes/arc-flag-classes.def
new file mode 100644
index 00000000000..bb33d033b58
--- /dev/null
+++ b/opcodes/arc-flag-classes.def
@@ -0,0 +1,125 @@
+/* ARC flag class defintions.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+ Refactored by Cupertino Miranda (cmiranda@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+FLAG_CLASS(EMPTY, F_CLASS_NONE, 0, 0, F_NULL)
+FLAG_CLASS(CC_EQ, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0 , F_EQUAL)
+FLAG_CLASS(CC_GE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0 , F_GE)
+FLAG_CLASS(CC_GT, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_GT)
+FLAG_CLASS(CC_HI, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_HI)
+FLAG_CLASS(CC_HS, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_NOTCARRY)
+FLAG_CLASS(CC_LE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LE)
+FLAG_CLASS(CC_LO, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_CARRY)
+FLAG_CLASS(CC_LS, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LS)
+FLAG_CLASS(CC_LT, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LT)
+FLAG_CLASS(CC_NE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_NOTEQUAL)
+
+FLAG_CLASS(AA_AB, F_CLASS_IMPLICIT | F_CLASS_WB, 0, 0, F_AB3)
+FLAG_CLASS(AA_AW, F_CLASS_IMPLICIT | F_CLASS_WB, 0, 0, F_AW3)
+
+FLAG_CLASS(ZZ_D, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZED)
+FLAG_CLASS(ZZ_L, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEL)
+FLAG_CLASS(ZZ_W, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEW)
+FLAG_CLASS(ZZ_H, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_H1)
+FLAG_CLASS(ZZ_B, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEB1)
+
+FLAG_CLASS(CC, F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, 0, 0, F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T)
+
+FLAG_CLASS(AA_ADDR3, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A3, F_AW3, F_AB3, F_AS3)
+FLAG_CLASS(AA27, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A3, F_AW3, F_AB3, F_AS3)
+FLAG_CLASS(AS27, F_CLASS_OPTIONAL, 0, 0, F_AS3)
+FLAG_CLASS(AA_ADDR9, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9, F_AS9)
+FLAG_CLASS(AA21, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9, F_AS9)
+FLAG_CLASS(AAB21, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9)
+FLAG_CLASS(AA_ADDR22, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22, F_AS22)
+FLAG_CLASS(AA8, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22, F_AS22)
+FLAG_CLASS(AAB8, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22)
+
+FLAG_CLASS(F, F_CLASS_OPTIONAL, 0, 0, F_FLAG)
+FLAG_CLASS(FHARD, F_CLASS_OPTIONAL, 0, 0, F_FFAKE)
+
+FLAG_CLASS(RL, F_CLASS_OPTIONAL, 0, 0, F_RL)
+FLAG_CLASS(AQ, F_CLASS_OPTIONAL, 0, 0, F_AQ)
+
+FLAG_CLASS(ATOP, F_CLASS_REQUIRED, 0, 0, F_ATO_ADD, F_ATO_OR, F_ATO_AND, F_ATO_XOR, F_ATO_MINU, F_ATO_MAXU, F_ATO_MIN, F_ATO_MAX)
+
+FLAG_CLASS(T, F_CLASS_OPTIONAL, 0, 0, F_NT, F_T)
+FLAG_CLASS(D, F_CLASS_OPTIONAL, 0, 0, F_ND, F_D)
+FLAG_CLASS(DNZ_D, F_CLASS_OPTIONAL, 0, 0, F_DNZ_ND, F_DNZ_D)
+
+FLAG_CLASS(DHARD, F_CLASS_OPTIONAL, 0, 0, F_DFAKE)
+
+FLAG_CLASS(DI20, F_CLASS_OPTIONAL, 0, 0, F_DI11)
+FLAG_CLASS(DI14, F_CLASS_OPTIONAL, 0, 0, F_DI14)
+FLAG_CLASS(DI16, F_CLASS_OPTIONAL, 0, 0, F_DI15)
+FLAG_CLASS(DI26, F_CLASS_OPTIONAL, 0, 0, F_DI5)
+
+FLAG_CLASS(X25, F_CLASS_OPTIONAL, 0, 0, F_SIGN6)
+FLAG_CLASS(X15, F_CLASS_OPTIONAL, 0, 0, F_SIGN16)
+FLAG_CLASS(XHARD, F_CLASS_OPTIONAL, 0, 0, F_SIGNX)
+FLAG_CLASS(X, F_CLASS_OPTIONAL, 0, 0, F_SIGNX)
+
+FLAG_CLASS(ZZ13, F_CLASS_OPTIONAL, 0, 0, F_SIZEB17, F_SIZEW17, F_H17)
+FLAG_CLASS(ZZ23, F_CLASS_OPTIONAL, 0, 0, F_SIZEB7, F_SIZEW7, F_H7)
+FLAG_CLASS(ZZ29, F_CLASS_OPTIONAL, 0, 0, F_SIZEB1, F_SIZEW1, F_H1)
+FLAG_CLASS(ZZW6, F_CLASS_OPTIONAL, 0, 0, F_SIZEB1)
+FLAG_CLASS(ZZH1, F_CLASS_OPTIONAL, 0, 0, F_SIZEW1, F_H1)
+
+FLAG_CLASS(AS, F_CLASS_OPTIONAL, 0, 0, F_ASFAKE)
+FLAG_CLASS(AAHARD13, F_CLASS_OPTIONAL, 0, 0, F_ASFAKE)
+FLAG_CLASS(NE, F_CLASS_REQUIRED, 0, 0, F_NE)
+
+/* ARC NPS400 Support: See comment near head of file. */
+FLAG_CLASS(NPS_CL, F_CLASS_REQUIRED, 0, 0, F_NPS_CL)
+FLAG_CLASS(NPS_NA, F_CLASS_OPTIONAL, 0, 0, F_NPS_NA)
+FLAG_CLASS(NPS_SR, F_CLASS_OPTIONAL, 0, 0, F_NPS_SR)
+FLAG_CLASS(NPS_M, F_CLASS_OPTIONAL, 0, 0, F_NPS_M)
+FLAG_CLASS(NPS_F, F_CLASS_OPTIONAL, 0, 0, F_NPS_FLAG)
+FLAG_CLASS(NPS_R, F_CLASS_OPTIONAL, 0, 0, F_NPS_R)
+FLAG_CLASS(NPS_SCHD_RW, F_CLASS_REQUIRED, 0, 0, F_NPS_RW, F_NPS_RD)
+FLAG_CLASS(NPS_SCHD_TRIG, F_CLASS_REQUIRED, 0, 0, F_NPS_WFT)
+FLAG_CLASS(NPS_SCHD_IE, F_CLASS_OPTIONAL, 0, 0, F_NPS_IE1, F_NPS_IE2, F_NPS_IE12)
+FLAG_CLASS(NPS_SYNC, F_CLASS_REQUIRED, 0, 0, F_NPS_SYNC_RD, F_NPS_SYNC_WR)
+FLAG_CLASS(NPS_HWS_OFF, F_CLASS_REQUIRED, 0, 0, F_NPS_HWS_OFF)
+FLAG_CLASS(NPS_HWS_RESTORE, F_CLASS_REQUIRED, 0, 0, F_NPS_HWS_RESTORE)
+FLAG_CLASS(NPS_SX, F_CLASS_OPTIONAL, 0, 0, F_NPS_SX)
+FLAG_CLASS(NPS_AR_AL, F_CLASS_REQUIRED, 0, 0, F_NPS_AR, F_NPS_AL)
+FLAG_CLASS(NPS_S, F_CLASS_REQUIRED, 0, 0, F_NPS_S)
+FLAG_CLASS(NPS_ZNCV, F_CLASS_REQUIRED, 0, 0, F_NPS_ZNCV_RD, F_NPS_ZNCV_WR)
+FLAG_CLASS(NPS_P0, F_CLASS_REQUIRED, 0, 0, F_NPS_P0)
+FLAG_CLASS(NPS_P1, F_CLASS_REQUIRED, 0, 0, F_NPS_P1)
+FLAG_CLASS(NPS_P2, F_CLASS_REQUIRED, 0, 0, F_NPS_P2)
+FLAG_CLASS(NPS_P3, F_CLASS_REQUIRED, 0, 0, F_NPS_P3)
+FLAG_CLASS(NPS_LDBIT_DI, F_CLASS_REQUIRED, 0, 0, F_NPS_LDBIT_DI)
+FLAG_CLASS(NPS_LDBIT_CL1, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_CL1)
+FLAG_CLASS(NPS_LDBIT_CL2, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_CL2)
+FLAG_CLASS(NPS_LDBIT_X_1, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1)
+FLAG_CLASS(NPS_LDBIT_X_2, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2)
+FLAG_CLASS(NPS_CORE, F_CLASS_REQUIRED, 0, 0, F_NPS_CORE)
+FLAG_CLASS(NPS_CLSR, F_CLASS_REQUIRED, 0, 0, F_NPS_CLSR)
+FLAG_CLASS(NPS_ALL, F_CLASS_REQUIRED, 0, 0, F_NPS_ALL)
+FLAG_CLASS(NPS_GIC, F_CLASS_REQUIRED, 0, 0, F_NPS_GIC)
+FLAG_CLASS(NPS_RSPI_GIC, F_CLASS_REQUIRED, 0, 0, F_NPS_RSPI_GIC)
+FLAG_CLASS(FPCC, F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, insert_fs2, extract_fs2, F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T)
+FLAG_CLASS(AA_128, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_AA128, F_AA128W, F_AA128B, F_AA128S)
+FLAG_CLASS(AS_128, F_CLASS_OPTIONAL, 0, 0, F_AA128S)
+FLAG_CLASS(AA_128S, F_CLASS_OPTIONAL | F_CLASS_WB, insert_qq, extract_qq, F_AA128, F_AA128W, F_AA128B, F_AA128S)
+FLAG_CLASS(AS_128S, F_CLASS_OPTIONAL, insert_qq, extract_qq, F_AA128S)
diff --git a/opcodes/arc-flag.def b/opcodes/arc-flag.def
new file mode 100644
index 00000000000..1312c464a3c
--- /dev/null
+++ b/opcodes/arc-flag.def
@@ -0,0 +1,179 @@
+/* ARC flag defintions.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+ Refactored by Cupertino Miranda (cmiranda@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+FLAG(ALWAYS, "al", 0, 0, 0, 0)
+FLAG(RA, "ra", 0, 0, 0, 0)
+FLAG(EQUAL, "eq", 1, 5, 0, 1)
+FLAG(ZERO, "z", 1, 5, 0, 0)
+FLAG(NOTEQUAL, "ne", 2, 5, 0, 1)
+FLAG(NOTZERO, "nz", 2, 5, 0, 0)
+FLAG(POZITIVE, "p", 3, 5, 0, 1)
+FLAG(PL, "pl", 3, 5, 0, 0)
+FLAG(NEGATIVE, "n", 4, 5, 0, 1)
+FLAG(MINUS, "mi", 4, 5, 0, 0)
+FLAG(CARRY, "c", 5, 5, 0, 1)
+FLAG(CARRYSET, "cs", 5, 5, 0, 0)
+FLAG(LOWER, "lo", 5, 5, 0, 0)
+FLAG(CARRYCLR, "cc", 6, 5, 0, 0)
+FLAG(NOTCARRY, "nc", 6, 5, 0, 1)
+FLAG(HIGHER, "hs", 6, 5, 0, 0)
+FLAG(OVERFLOWSET, "vs", 7, 5, 0, 0)
+FLAG(OVERFLOW, "v", 7, 5, 0, 1)
+FLAG(NOTOVERFLOW, "nv", 8, 5, 0, 1)
+FLAG(OVERFLOWCLR, "vc", 8, 5, 0, 0)
+FLAG(GT, "gt", 9, 5, 0, 1)
+FLAG(GE, "ge", 10, 5, 0, 1)
+FLAG(LT, "lt", 11, 5, 0, 1)
+FLAG(LE, "le", 12, 5, 0, 1)
+FLAG(HI, "hi", 13, 5, 0, 1)
+FLAG(LS, "ls", 14, 5, 0, 1)
+FLAG(PNZ, "pnz", 15, 5, 0, 1)
+FLAG(NJ, "nj", 21, 5, 0, 1)
+FLAG(NM, "nm", 23, 5, 0, 1)
+FLAG(NO_T, "nt", 24, 5, 0, 1)
+
+ /* FLAG. */
+FLAG(FLAG, "f", 1, 1, 15, 1)
+FLAG(FFAKE, "f", 0, 0, 0, 1)
+FLAG(AQ, "aq", 1, 1, 15, 1)
+FLAG(RL, "rl", 1, 1, 15, 1)
+
+ /* Atomic operations. */
+FLAG(ATO_ADD, "add", 0, 3, 0, 1)
+FLAG(ATO_OR, "or", 1, 3, 0, 1)
+FLAG(ATO_AND, "and", 2, 3, 0, 1)
+FLAG(ATO_XOR, "xor", 3, 3, 0, 1)
+FLAG(ATO_MINU, "minu", 4, 3, 0, 1)
+FLAG(ATO_MAXU, "maxu", 5, 3, 0, 1)
+FLAG(ATO_MIN, "min", 6, 3, 0, 1)
+FLAG(ATO_MAX, "max", 7, 3, 0, 1)
+
+ /* Delay slot. */
+FLAG(ND, "nd", 0, 1, 5, 0)
+FLAG(D, "d", 1, 1, 5, 1)
+FLAG(DFAKE, "d", 0, 0, 0, 1)
+FLAG(DNZ_ND, "nd", 0, 1, 16, 0)
+FLAG(DNZ_D, "d", 1, 1, 16, 1)
+
+ /* Data size. */
+FLAG(SIZEB1, "b", 1, 2, 1, 1)
+FLAG(SIZEB7, "b", 1, 2, 7, 1)
+FLAG(SIZEB17, "b", 1, 2, 17, 1)
+FLAG(SIZEW1, "w", 2, 2, 1, 0)
+FLAG(SIZEW7, "w", 2, 2, 7, 0)
+FLAG(SIZEW17, "w", 2, 2, 17, 0)
+
+ /* Sign extension. */
+FLAG(SIGN6, "x", 1, 1, 6, 1)
+FLAG(SIGN16, "x", 1, 1, 16, 1)
+FLAG(SIGNX, "x", 0, 0, 0, 1)
+
+ /* Address write-back modes. */
+FLAG(A3, "a", 1, 2, 3, 0)
+FLAG(A9, "a", 1, 2, 9, 0)
+FLAG(A22, "a", 1, 2, 22, 0)
+FLAG(AW3, "aw", 1, 2, 3, 1)
+FLAG(AW9, "aw", 1, 2, 9, 1)
+FLAG(AW22, "aw", 1, 2, 22, 1)
+FLAG(AB3, "ab", 2, 2, 3, 1)
+FLAG(AB9, "ab", 2, 2, 9, 1)
+FLAG(AB22, "ab", 2, 2, 22, 1)
+FLAG(AS3, "as", 3, 2, 3, 1)
+FLAG(AS9, "as", 3, 2, 9, 1)
+FLAG(AS22, "as", 3, 2, 22, 1)
+FLAG(ASFAKE, "as", 0, 0, 0, 1)
+
+/* address writebacks for 128-bit loads.
+ ,---.---.----------.
+ | X | D | mnemonic |
+ |---+---+----------|
+ | 0 | 0 | none |
+ | 0 | 1 | as |
+ | 1 | 0 | a/aw |
+ | 1 | 1 | ab |
+ `---^---^----------' */
+FLAG(AA128, "a", 2, 2, 15, 0)
+FLAG(AA128W, "aw", 2, 2, 15, 1)
+FLAG(AA128B, "ab", 3, 2, 15, 1)
+FLAG(AA128S, "as", 1, 2, 15, 1)
+
+ /* Cache bypass. */
+FLAG(DI5, "di", 1, 1, 5, 1)
+FLAG(DI11, "di", 1, 1, 11, 1)
+FLAG(DI14, "di", 1, 1, 14, 1)
+FLAG(DI15, "di", 1, 1, 15, 1)
+
+ /* ARCv2 specific. */
+FLAG(NT, "nt", 0, 1, 3, 1)
+FLAG(T, "t", 1, 1, 3, 1)
+FLAG(H1, "h", 2, 2, 1, 1)
+FLAG(H7, "h", 2, 2, 7, 1)
+FLAG(H17, "h", 2, 2, 17, 1)
+/* Fake */
+FLAG(SIZED, "dd", 8, 0, 0, 0)
+/* Fake */
+FLAG(SIZEL, "dl", 8, 0, 0, 0)
+/* Fake */
+FLAG(SIZEW, "xx", 4, 0, 0, 0)
+
+ /* Fake Flags. */
+FLAG(NE, "ne", 0, 0, 0, 1)
+
+/* ARC NPS400 Support: See comment near head of arcxx-opc.inc file. */
+FLAG(NPS_CL, "cl", 0, 0, 0, 1)
+FLAG(NPS_NA, "na", 1, 1, 9, 1)
+FLAG(NPS_SR, "s", 1, 1, 13, 1)
+FLAG(NPS_M, "m", 1, 1, 7, 1)
+FLAG(NPS_FLAG, "f", 1, 1, 20, 1)
+FLAG(NPS_R, "r", 1, 1, 15, 1)
+FLAG(NPS_RW, "rw", 0, 1, 7, 1)
+FLAG(NPS_RD, "rd", 1, 1, 7, 1)
+FLAG(NPS_WFT, "wft", 0, 0, 0, 1)
+FLAG(NPS_IE1, "ie1", 1, 2, 8, 1)
+FLAG(NPS_IE2, "ie2", 2, 2, 8, 1)
+FLAG(NPS_IE12, "ie12", 3, 2, 8, 1)
+FLAG(NPS_SYNC_RD, "rd", 0, 1, 6, 1)
+FLAG(NPS_SYNC_WR, "wr", 1, 1, 6, 1)
+FLAG(NPS_HWS_OFF, "off", 0, 0, 0, 1)
+FLAG(NPS_HWS_RESTORE, "restore", 0, 0, 0, 1)
+FLAG(NPS_SX, "sx", 1, 1, 14, 1)
+FLAG(NPS_AR, "ar", 0, 1, 0, 1)
+FLAG(NPS_AL, "al", 1, 1, 0, 1)
+FLAG(NPS_S, "s", 0, 0, 0, 1)
+FLAG(NPS_ZNCV_RD, "rd", 0, 1, 15, 1)
+FLAG(NPS_ZNCV_WR, "wr", 1, 1, 15, 1)
+FLAG(NPS_P0, "p0", 0, 0, 0, 1)
+FLAG(NPS_P1, "p1", 0, 0, 0, 1)
+FLAG(NPS_P2, "p2", 0, 0, 0, 1)
+FLAG(NPS_P3, "p3", 0, 0, 0, 1)
+FLAG(NPS_LDBIT_DI, "di", 0, 0, 0, 1)
+FLAG(NPS_LDBIT_CL1, "cl", 1, 1, 6, 1)
+FLAG(NPS_LDBIT_CL2, "cl", 1, 1, 16, 1)
+FLAG(NPS_LDBIT_X2_1, "x2", 1, 2, 9, 1)
+FLAG(NPS_LDBIT_X2_2, "x2", 1, 2, 22, 1)
+FLAG(NPS_LDBIT_X4_1, "x4", 2, 2, 9, 1)
+FLAG(NPS_LDBIT_X4_2, "x4", 2, 2, 22, 1)
+FLAG(NPS_CORE, "core", 1, 3, 6, 1)
+FLAG(NPS_CLSR, "clsr", 2, 3, 6, 1)
+FLAG(NPS_ALL, "all", 3, 3, 6, 1)
+FLAG(NPS_GIC, "gic", 4, 3, 6, 1)
+FLAG(NPS_RSPI_GIC, "gic", 5, 3, 6, 1)
diff --git a/opcodes/arc-fxi.h b/opcodes/arc-fxi.h
index e2d4de6a579..d87e7755f20 100644
--- a/opcodes/arc-fxi.h
+++ b/opcodes/arc-fxi.h
@@ -1318,3 +1318,63 @@ extract_uimm6_axx_ (unsigned long long insn ATTRIBUTE_UNUSED,
return value;
}
#endif /* EXTRACT_UIMM6_AXX_ */
+
+/* mask = 0000022000011111. */
+#ifndef INSERT_UIMM9_A32_11_S
+#define INSERT_UIMM9_A32_11_S
+ATTRIBUTE_UNUSED static unsigned long long
+insert_uimm9_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ long long int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value & 0x03)
+ *errmsg = "Target address is not 32bit aligned.";
+
+ insn |= ((value >> 2) & 0x001f) << 0;
+ insn |= ((value >> 7) & 0x0003) << 9;
+ return insn;
+}
+#endif /* INSERT_UIMM9_A32_11_S. */
+
+#ifndef EXTRACT_UIMM9_A32_11_S
+#define EXTRACT_UIMM9_A32_11_S
+ATTRIBUTE_UNUSED static long long int
+extract_uimm9_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ unsigned value = 0;
+ value |= ((insn >> 0) & 0x001f) << 2;
+ value |= ((insn >> 9) & 0x0003) << 7;
+
+ return value;
+}
+#endif /* EXTRACT_UIMM9_A32_11_S. */
+
+/* mask = 0000022222220111. */
+#ifndef INSERT_UIMM10_13_S
+#define INSERT_UIMM10_13_S
+ATTRIBUTE_UNUSED static unsigned long long
+insert_uimm10_13_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ long long int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value >> 0) & 0x0007) << 0;
+ insn |= ((value >> 3) & 0x007f) << 4;
+
+ return insn;
+}
+#endif /* INSERT_UIMM10_13_S. */
+
+#ifndef EXTRACT_UIMM10_13_S
+#define EXTRACT_UIMM10_13_S
+ATTRIBUTE_UNUSED static long long int
+extract_uimm10_13_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ unsigned value = 0;
+ value |= ((insn >> 0) & 0x0007) << 0;
+ value |= ((insn >> 4) & 0x007f) << 3;
+
+ return value;
+}
+#endif /* EXTRACT_UIMM10_13_S. */
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 4257e79fe4b..8e7c910a18c 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -19,2595 +19,103 @@
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-#include "sysdep.h"
-#include <stdio.h>
-#include "bfd.h"
-#include "opcode/arc.h"
-#include "opintl.h"
-#include "libiberty.h"
-
-/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
- instructions. All NPS400 features are built into all ARC target builds as
- this reduces the chances that regressions might creep in. */
-
-/* Insert RA register into a 32-bit opcode, with checks. */
-
-static unsigned long long
-insert_ra_chk (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value == 60)
- *errmsg = _("LP_COUNT register cannot be used as destination register");
-
- return insn | (value & 0x3F);
-}
-
-/* Insert RB register into a 32-bit opcode. */
-
-static unsigned long long
-insert_rb (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
-}
-
-/* Insert RB register with checks. */
-
-static unsigned long long
-insert_rb_chk (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value == 60)
- *errmsg = _("LP_COUNT register cannot be used as destination register");
-
- return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
-}
-
-static long long
-extract_rb (unsigned long long insn,
- bool *invalid)
-{
- int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
-
- if (value == 0x3e && invalid)
- *invalid = true; /* A limm operand, it should be extracted in a
- different way. */
-
- return value;
-}
-
-static unsigned long long
-insert_rad (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value & 0x01)
- *errmsg = _("cannot use odd number destination register");
- if (value == 60)
- *errmsg = _("LP_COUNT register cannot be used as destination register");
-
- return insn | (value & 0x3F);
-}
-
-static unsigned long long
-insert_rcd (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value & 0x01)
- *errmsg = _("cannot use odd number source register");
-
- return insn | ((value & 0x3F) << 6);
-}
-
-static unsigned long long
-insert_rbd (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value & 0x01)
- *errmsg = _("cannot use odd number source register");
- if (value == 60)
- *errmsg = _("LP_COUNT register cannot be used as destination register");
-
- return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
-}
-
-/* Dummy insert ZERO operand function. */
-
-static unsigned long long
-insert_za (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value)
- *errmsg = _("operand is not zero");
- return insn;
-}
-
-/* Insert Y-bit in bbit/br instructions. This function is called only
- when solving fixups. */
-
-static unsigned long long
-insert_Ybit (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- if (value > 0)
- insn |= 0x08;
-
- return insn;
-}
-
-/* Insert Y-bit in bbit/br instructions. This function is called only
- when solving fixups. */
-
-static unsigned long long
-insert_NYbit (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- if (value < 0)
- insn |= 0x08;
-
- return insn;
-}
-
-/* Insert H register into a 16-bit opcode. */
-
-static unsigned long long
-insert_rhv1 (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
-}
-
-static long long
-extract_rhv1 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
-
- return value;
-}
-
-/* Insert H register into a 16-bit opcode. */
-
-static unsigned long long
-insert_rhv2 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value == 0x1E)
- *errmsg = _("register R30 is a limm indicator");
- else if (value < 0 || value > 31)
- *errmsg = _("register out of range");
- return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
-}
-
-static long long
-extract_rhv2 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
-
- return value;
-}
-
-static unsigned long long
-insert_r0 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 0)
- *errmsg = _("register must be R0");
- return insn;
-}
-
-static long long
-extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-
-static unsigned long long
-insert_r1 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 1)
- *errmsg = _("register must be R1");
- return insn;
-}
-
-static long long
-extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool* invalid ATTRIBUTE_UNUSED)
-{
- return 1;
-}
-
-static unsigned long long
-insert_r2 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 2)
- *errmsg = _("register must be R2");
- return insn;
-}
-
-static long long
-extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 2;
-}
-
-static unsigned long long
-insert_r3 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 3)
- *errmsg = _("register must be R3");
- return insn;
-}
-
-static long long
-extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 3;
-}
-
-static unsigned long long
-insert_sp (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 28)
- *errmsg = _("register must be SP");
- return insn;
-}
-
-static long long
-extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 28;
-}
-
-static unsigned long long
-insert_gp (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 26)
- *errmsg = _("register must be GP");
- return insn;
-}
-
-static long long
-extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 26;
-}
-
-static unsigned long long
-insert_pcl (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 63)
- *errmsg = _("register must be PCL");
- return insn;
-}
-
-static long long
-extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 63;
-}
-
-static unsigned long long
-insert_blink (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 31)
- *errmsg = _("register must be BLINK");
- return insn;
-}
-
-static long long
-extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 31;
-}
-
-static unsigned long long
-insert_ilink1 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 29)
- *errmsg = _("register must be ILINK1");
- return insn;
-}
-
-static long long
-extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 29;
-}
-
-static unsigned long long
-insert_ilink2 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 30)
- *errmsg = _("register must be ILINK2");
- return insn;
-}
-
-static long long
-extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 30;
-}
-
-static unsigned long long
-insert_ras (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- insn |= value;
- break;
- case 12:
- case 13:
- case 14:
- case 15:
- insn |= (value - 8);
- break;
- default:
- *errmsg = _("register must be either r0-r3 or r12-r15");
- break;
- }
- return insn;
-}
-
-static long long
-extract_ras (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = insn & 0x07;
-
- if (value > 3)
- return (value + 8);
- else
- return value;
-}
-
-static unsigned long long
-insert_rbs (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- insn |= value << 8;
- break;
- case 12:
- case 13:
- case 14:
- case 15:
- insn |= ((value - 8)) << 8;
- break;
- default:
- *errmsg = _("register must be either r0-r3 or r12-r15");
- break;
- }
- return insn;
-}
-
-static long long
-extract_rbs (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = (insn >> 8) & 0x07;
-
- if (value > 3)
- return (value + 8);
- else
- return value;
-}
-
-static unsigned long long
-insert_rcs (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- insn |= value << 5;
- break;
- case 12:
- case 13:
- case 14:
- case 15:
- insn |= ((value - 8)) << 5;
- break;
- default:
- *errmsg = _("register must be either r0-r3 or r12-r15");
- break;
- }
- return insn;
-}
-
-static long long
-extract_rcs (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = (insn >> 5) & 0x07;
-
- if (value > 3)
- return (value + 8);
- else
- return value;
-}
-
-static unsigned long long
-insert_simm3s (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- int tmp = 0;
- switch (value)
- {
- case -1:
- tmp = 0x07;
- break;
- case 0:
- tmp = 0x00;
- break;
- case 1:
- tmp = 0x01;
- break;
- case 2:
- tmp = 0x02;
- break;
- case 3:
- tmp = 0x03;
- break;
- case 4:
- tmp = 0x04;
- break;
- case 5:
- tmp = 0x05;
- break;
- case 6:
- tmp = 0x06;
- break;
- default:
- *errmsg = _("accepted values are from -1 to 6");
- break;
- }
-
- insn |= tmp << 8;
- return insn;
-}
-
-static long long
-extract_simm3s (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = (insn >> 8) & 0x07;
-
- if (value == 7)
- return -1;
- else
- return value;
-}
-
-static unsigned long long
-insert_rrange (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- int reg1 = (value >> 16) & 0xFFFF;
- int reg2 = value & 0xFFFF;
-
- if (reg1 != 13)
- *errmsg = _("first register of the range should be r13");
- else if (reg2 < 13 || reg2 > 26)
- *errmsg = _("last register of the range doesn't fit");
- else
- insn |= ((reg2 - 12) & 0x0F) << 1;
- return insn;
-}
-
-static long long
-extract_rrange (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn >> 1) & 0x0F;
-}
-
-static unsigned long long
-insert_r13el (unsigned long long insn,
- long long int value,
- const char **errmsg)
-{
- if (value != 13)
- {
- *errmsg = _("invalid register number, should be fp");
- return insn;
- }
-
- insn |= 0x02;
- return insn;
-}
-
-static unsigned long long
-insert_fpel (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 27)
- {
- *errmsg = _("invalid register number, should be fp");
- return insn;
- }
-
- insn |= 0x0100;
- return insn;
-}
-
-static long long
-extract_fpel (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn & 0x0100) ? 27 : -1;
-}
-
-static unsigned long long
-insert_blinkel (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 31)
- {
- *errmsg = _("invalid register number, should be blink");
- return insn;
- }
-
- insn |= 0x0200;
- return insn;
-}
-
-static long long
-extract_blinkel (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn & 0x0200) ? 31 : -1;
-}
-
-static unsigned long long
-insert_pclel (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 63)
- {
- *errmsg = _("invalid register number, should be pcl");
- return insn;
- }
-
- insn |= 0x0400;
- return insn;
-}
-
-static long long
-extract_pclel (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn & 0x0400) ? 63 : -1;
-}
-
-#define INSERT_W6
-
-/* mask = 00000000000000000000111111000000
- insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
-
-static unsigned long long
-insert_w6 (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- insn |= ((value >> 0) & 0x003f) << 6;
-
- return insn;
-}
-
-#define EXTRACT_W6
-
-/* mask = 00000000000000000000111111000000. */
-
-static long long
-extract_w6 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = 0;
-
- value |= ((insn >> 6) & 0x003f) << 0;
-
- /* Extend the sign. */
- int signbit = 1 << 5;
- value = (value ^ signbit) - signbit;
-
- return value;
-}
-
-#define INSERT_G_S
-
-/* mask = 0000011100022000
- insn = 01000ggghhhGG0HH. */
-
-static unsigned long long
-insert_g_s (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- insn |= ((value >> 0) & 0x0007) << 8;
- insn |= ((value >> 3) & 0x0003) << 3;
-
- return insn;
-}
-
-#define EXTRACT_G_S
-
-/* mask = 0000011100022000. */
-
-static long long
-extract_g_s (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = 0;
- int signbit = 1 << (6 - 1);
-
- value |= ((insn >> 8) & 0x0007) << 0;
- value |= ((insn >> 3) & 0x0003) << 3;
-
- /* Extend the sign. */
- value = (value ^ signbit) - signbit;
-
- return value;
-}
-
-/* ARC NPS400 Support: See comment near head of file. */
-#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
-static unsigned long long \
-insert_nps_3bit_reg_at_##OFFSET##_##NAME \
- (unsigned long long insn, \
- long long value, \
- const char ** errmsg) \
-{ \
- switch (value) \
- { \
- case 0: \
- case 1: \
- case 2: \
- case 3: \
- insn |= value << (OFFSET); \
- break; \
- case 12: \
- case 13: \
- case 14: \
- case 15: \
- insn |= (value - 8) << (OFFSET); \
- break; \
- default: \
- *errmsg = _("register must be either r0-r3 or r12-r15"); \
- break; \
- } \
- return insn; \
-} \
- \
-static long long \
-extract_nps_3bit_reg_at_##OFFSET##_##NAME \
- (unsigned long long insn, \
- bool *invalid ATTRIBUTE_UNUSED) \
-{ \
- int value = (insn >> (OFFSET)) & 0x07; \
- if (value > 3) \
- value += 8; \
- return value; \
-} \
-
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
-
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
-
-static unsigned long long
-insert_nps_bitop_size_2b (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 1:
- value = 0;
- break;
- case 2:
- value = 1;
- break;
- case 4:
- value = 2;
- break;
- case 8:
- value = 3;
- break;
- default:
- value = 0;
- *errmsg = _("invalid size, should be 1, 2, 4, or 8");
- break;
- }
-
- insn |= value << 10;
- return insn;
-}
-
-static long long
-extract_nps_bitop_size_2b (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 1 << ((insn >> 10) & 0x3);
-}
-
-static unsigned long long
-insert_nps_bitop_uimm8 (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- insn |= ((value >> 5) & 7) << 12;
- insn |= (value & 0x1f);
- return insn;
-}
-
-static long long
-extract_nps_bitop_uimm8 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
-}
-
-static unsigned long long
-insert_nps_rflt_uimm6 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 1:
- case 2:
- case 4:
- break;
-
- default:
- *errmsg = _("invalid immediate, must be 1, 2, or 4");
- value = 0;
- }
-
- insn |= (value << 6);
- return insn;
-}
-
-static long long
-extract_nps_rflt_uimm6 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn >> 6) & 0x3f;
-}
-
-static unsigned long long
-insert_nps_dst_pos_and_size (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
- return insn;
-}
-
-static long long
-extract_nps_dst_pos_and_size (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn & 0x1f);
-}
-
-static unsigned long long
-insert_nps_cmem_uimm16 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- int top = (value >> 16) & 0xffff;
-
- if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
- *errmsg = _("invalid value for CMEM ld/st immediate");
- insn |= (value & 0xffff);
- return insn;
-}
-
-static long long
-extract_nps_cmem_uimm16 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
-}
-
-static unsigned long long
-insert_nps_imm_offset (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 0:
- case 16:
- case 32:
- case 48:
- case 64:
- value = value >> 4;
- break;
- default:
- *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64.");
- value = 0;
- }
- insn |= (value << 10);
- return insn;
-}
-
-static long long
-extract_nps_imm_offset (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return ((insn >> 10) & 0x7) * 16;
-}
-
-static unsigned long long
-insert_nps_imm_entry (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 16:
- value = 0;
- break;
- case 32:
- value = 1;
- break;
- case 64:
- value = 2;
- break;
- case 128:
- value = 3;
- break;
- default:
- *errmsg = _("invalid position, should be 16, 32, 64 or 128.");
- value = 0;
- }
- insn |= (value << 2);
- return insn;
-}
-
-static long long
-extract_nps_imm_entry (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int imm_entry = ((insn >> 2) & 0x7);
- return (1 << (imm_entry + 4));
-}
-
-static unsigned long long
-insert_nps_size_16bit (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if ((value < 1) || (value > 64))
- {
- *errmsg = _("invalid size value must be on range 1-64.");
- value = 0;
- }
- value = value & 0x3f;
- insn |= (value << 6);
- return insn;
-}
-
-static long long
-extract_nps_size_16bit (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64;
-}
-
-
-#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
-static unsigned long long \
-insert_nps_##NAME##_pos (unsigned long long insn, \
- long long value, \
- const char ** errmsg) \
-{ \
- switch (value) \
- { \
- case 0: \
- case 8: \
- case 16: \
- case 24: \
- value = value / 8; \
- break; \
- default: \
- *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \
- value = 0; \
- } \
- insn |= (value << SHIFT); \
- return insn; \
-} \
- \
-static long long \
-extract_nps_##NAME##_pos (unsigned long long insn, \
- bool *invalid ATTRIBUTE_UNUSED) \
-{ \
- return ((insn >> SHIFT) & 0x3) * 8; \
-}
-
-MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
-MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
-
-#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \
-static unsigned long long \
-insert_nps_##NAME (unsigned long long insn, \
- long long value, \
- const char ** errmsg) \
- { \
- if (value < LOWER || value > UPPER) \
- { \
- *errmsg = _("invalid size, value must be " \
- #LOWER " to " #UPPER "."); \
- return insn; \
- } \
- value -= BIAS; \
- insn |= (value << SHIFT); \
- return insn; \
- } \
- \
-static long long \
-extract_nps_##NAME (unsigned long long insn, \
- bool *invalid ATTRIBUTE_UNUSED) \
-{ \
- return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
-}
-
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
-
-static long long
-extract_nps_qcmp_m3 (unsigned long long insn,
- bool *invalid)
-{
- int m3 = (insn >> 5) & 0xf;
- if (m3 == 0xf)
- *invalid = true;
- return m3;
-}
-
-static long long
-extract_nps_qcmp_m2 (unsigned long long insn,
- bool *invalid)
-{
- bool tmp_invalid = false;
- int m2 = (insn >> 15) & 0x1;
- int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
-
- if (m2 == 0 && m3 == 0xf)
- *invalid = true;
- return m2;
-}
-
-static long long
-extract_nps_qcmp_m1 (unsigned long long insn,
- bool *invalid)
-{
- bool tmp_invalid = false;
- int m1 = (insn >> 14) & 0x1;
- int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
- int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
-
- if (m1 == 0 && m2 == 0 && m3 == 0xf)
- *invalid = true;
- return m1;
-}
-
-static unsigned long long
-insert_nps_calc_entry_size (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- unsigned pwr;
-
- if (value < 1 || value > 256)
- {
- *errmsg = _("value out of range 1 - 256");
- return 0;
- }
-
- for (pwr = 0; (value & 1) == 0; value >>= 1)
- ++pwr;
-
- if (value != 1)
- {
- *errmsg = _("value must be power of 2");
- return 0;
- }
-
- return insn | (pwr << 8);
-}
-
-static long long
-extract_nps_calc_entry_size (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- unsigned entry_size = (insn >> 8) & 0xf;
- return 1 << entry_size;
-}
-
-static unsigned long long
-insert_nps_bitop_mod4 (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
-}
-
-static long long
-extract_nps_bitop_mod4 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
-}
-
-static unsigned long long
-insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- return insn | (value << 42) | (value << 37);
-}
-
-static long long
-extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
- bool *invalid)
-{
- if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
- *invalid = true;
- return ((insn >> 37) & 0x1f);
-}
-
-static unsigned long long
-insert_nps_bitop_ins_ext (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value < 0 || value > 28)
- *errmsg = _("value must be in the range 0 to 28");
- return insn | (value << 20);
-}
-
-static long long
-extract_nps_bitop_ins_ext (unsigned long long insn,
- bool *invalid)
-{
- int value = (insn >> 20) & 0x1f;
-
- if (value > 28)
- *invalid = true;
- return value;
-}
-
-#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
-static unsigned long long \
-insert_nps_##NAME (unsigned long long insn, \
- long long value, \
- const char ** errmsg) \
-{ \
- if (value < 1 || value > UPPER) \
- *errmsg = _("value must be in the range 1 to " #UPPER); \
- if (value == UPPER) \
- value = 0; \
- return insn | (value << SHIFT); \
-} \
- \
-static long long \
-extract_nps_##NAME (unsigned long long insn, \
- bool *invalid ATTRIBUTE_UNUSED) \
-{ \
- int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
- if (value == 0) \
- value = UPPER; \
- return value; \
-}
-
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
-
-static unsigned long long
-insert_nps_min_hofs (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value < 0 || value > 240)
- *errmsg = _("value must be in the range 0 to 240");
- if ((value % 16) != 0)
- *errmsg = _("value must be a multiple of 16");
- value = value / 16;
- return insn | (value << 6);
-}
-
-static long long
-extract_nps_min_hofs (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = (insn >> 6) & 0xF;
- return value * 16;
-}
-
-#define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \
-static unsigned long long \
-insert_nps_##NAME (unsigned long long insn, \
- long long value, \
- const char ** errmsg) \
-{ \
- if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
- *errmsg = _("invalid address type for operand"); \
- return insn; \
-} \
- \
-static long long \
-extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
- bool *invalid ATTRIBUTE_UNUSED) \
-{ \
- return ARC_NPS400_ADDRTYPE_##VALUE; \
-}
-
-MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
-MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
-MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
-MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
-MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
-MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
-MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
-MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
-MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
-MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
-MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
-MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
-MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
-MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
-MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
-MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
-
-static unsigned long long
-insert_nps_rbdouble_64 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value < 0 || value > 31)
- *errmsg = _("value must be in the range 0 to 31");
- return insn | (value << 43) | (value << 48);
-}
-
-
-static long long
-extract_nps_rbdouble_64 (unsigned long long insn,
- bool *invalid)
-{
- int value1 = (insn >> 43) & 0x1F;
- int value2 = (insn >> 48) & 0x1F;
-
- if (value1 != value2)
- *invalid = true;
-
- return value1;
-}
-
-static unsigned long long
-insert_nps_misc_imm_offset (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value & 0x3)
- {
- *errmsg = _("invalid position, should be one of: 0,4,8,...124.");
- value = 0;
- }
- insn |= (value << 6);
- return insn;
-}
-
-static long long int
-extract_nps_misc_imm_offset (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return ((insn >> 8) & 0x1f) * 4;
-}
-
-static long long int
-extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = 0;
-
- value |= ((insn >> 6) & 0x003f) << 0;
- value |= ((insn >> 0) & 0x003f) << 6;
-
- return value;
-}
-
-/* Include the generic extract/insert functions. Order is important
- as some of the functions present in the .h may be disabled via
- defines. */
-#include "arc-fxi.h"
-
-/* The flag operands table.
-
- The format of the table is
- NAME CODE BITS SHIFT FAVAIL. */
-const struct arc_flag_operand arc_flag_operands[] =
-{
-#define F_NULL 0
- { 0, 0, 0, 0, 0},
-#define F_ALWAYS (F_NULL + 1)
- { "al", 0, 0, 0, 0 },
-#define F_RA (F_ALWAYS + 1)
- { "ra", 0, 0, 0, 0 },
-#define F_EQUAL (F_RA + 1)
- { "eq", 1, 5, 0, 1 },
-#define F_ZERO (F_EQUAL + 1)
- { "z", 1, 5, 0, 0 },
-#define F_NOTEQUAL (F_ZERO + 1)
- { "ne", 2, 5, 0, 1 },
-#define F_NOTZERO (F_NOTEQUAL + 1)
- { "nz", 2, 5, 0, 0 },
-#define F_POZITIVE (F_NOTZERO + 1)
- { "p", 3, 5, 0, 1 },
-#define F_PL (F_POZITIVE + 1)
- { "pl", 3, 5, 0, 0 },
-#define F_NEGATIVE (F_PL + 1)
- { "n", 4, 5, 0, 1 },
-#define F_MINUS (F_NEGATIVE + 1)
- { "mi", 4, 5, 0, 0 },
-#define F_CARRY (F_MINUS + 1)
- { "c", 5, 5, 0, 1 },
-#define F_CARRYSET (F_CARRY + 1)
- { "cs", 5, 5, 0, 0 },
-#define F_LOWER (F_CARRYSET + 1)
- { "lo", 5, 5, 0, 0 },
-#define F_CARRYCLR (F_LOWER + 1)
- { "cc", 6, 5, 0, 0 },
-#define F_NOTCARRY (F_CARRYCLR + 1)
- { "nc", 6, 5, 0, 1 },
-#define F_HIGHER (F_NOTCARRY + 1)
- { "hs", 6, 5, 0, 0 },
-#define F_OVERFLOWSET (F_HIGHER + 1)
- { "vs", 7, 5, 0, 0 },
-#define F_OVERFLOW (F_OVERFLOWSET + 1)
- { "v", 7, 5, 0, 1 },
-#define F_NOTOVERFLOW (F_OVERFLOW + 1)
- { "nv", 8, 5, 0, 1 },
-#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
- { "vc", 8, 5, 0, 0 },
-#define F_GT (F_OVERFLOWCLR + 1)
- { "gt", 9, 5, 0, 1 },
-#define F_GE (F_GT + 1)
- { "ge", 10, 5, 0, 1 },
-#define F_LT (F_GE + 1)
- { "lt", 11, 5, 0, 1 },
-#define F_LE (F_LT + 1)
- { "le", 12, 5, 0, 1 },
-#define F_HI (F_LE + 1)
- { "hi", 13, 5, 0, 1 },
-#define F_LS (F_HI + 1)
- { "ls", 14, 5, 0, 1 },
-#define F_PNZ (F_LS + 1)
- { "pnz", 15, 5, 0, 1 },
-#define F_NJ (F_PNZ + 1)
- { "nj", 21, 5, 0, 1 },
-#define F_NM (F_NJ + 1)
- { "nm", 23, 5, 0, 1 },
-#define F_NO_T (F_NM + 1)
- { "nt", 24, 5, 0, 1 },
-
- /* FLAG. */
-#define F_FLAG (F_NO_T + 1)
- { "f", 1, 1, 15, 1 },
-#define F_FFAKE (F_FLAG + 1)
- { "f", 0, 0, 0, 1 },
-
- /* Delay slot. */
-#define F_ND (F_FFAKE + 1)
- { "nd", 0, 1, 5, 0 },
-#define F_D (F_ND + 1)
- { "d", 1, 1, 5, 1 },
-#define F_DFAKE (F_D + 1)
- { "d", 0, 0, 0, 1 },
-#define F_DNZ_ND (F_DFAKE + 1)
- { "nd", 0, 1, 16, 0 },
-#define F_DNZ_D (F_DNZ_ND + 1)
- { "d", 1, 1, 16, 1 },
-
- /* Data size. */
-#define F_SIZEB1 (F_DNZ_D + 1)
- { "b", 1, 2, 1, 1 },
-#define F_SIZEB7 (F_SIZEB1 + 1)
- { "b", 1, 2, 7, 1 },
-#define F_SIZEB17 (F_SIZEB7 + 1)
- { "b", 1, 2, 17, 1 },
-#define F_SIZEW1 (F_SIZEB17 + 1)
- { "w", 2, 2, 1, 0 },
-#define F_SIZEW7 (F_SIZEW1 + 1)
- { "w", 2, 2, 7, 0 },
-#define F_SIZEW17 (F_SIZEW7 + 1)
- { "w", 2, 2, 17, 0 },
-
- /* Sign extension. */
-#define F_SIGN6 (F_SIZEW17 + 1)
- { "x", 1, 1, 6, 1 },
-#define F_SIGN16 (F_SIGN6 + 1)
- { "x", 1, 1, 16, 1 },
-#define F_SIGNX (F_SIGN16 + 1)
- { "x", 0, 0, 0, 1 },
-
- /* Address write-back modes. */
-#define F_A3 (F_SIGNX + 1)
- { "a", 1, 2, 3, 0 },
-#define F_A9 (F_A3 + 1)
- { "a", 1, 2, 9, 0 },
-#define F_A22 (F_A9 + 1)
- { "a", 1, 2, 22, 0 },
-#define F_AW3 (F_A22 + 1)
- { "aw", 1, 2, 3, 1 },
-#define F_AW9 (F_AW3 + 1)
- { "aw", 1, 2, 9, 1 },
-#define F_AW22 (F_AW9 + 1)
- { "aw", 1, 2, 22, 1 },
-#define F_AB3 (F_AW22 + 1)
- { "ab", 2, 2, 3, 1 },
-#define F_AB9 (F_AB3 + 1)
- { "ab", 2, 2, 9, 1 },
-#define F_AB22 (F_AB9 + 1)
- { "ab", 2, 2, 22, 1 },
-#define F_AS3 (F_AB22 + 1)
- { "as", 3, 2, 3, 1 },
-#define F_AS9 (F_AS3 + 1)
- { "as", 3, 2, 9, 1 },
-#define F_AS22 (F_AS9 + 1)
- { "as", 3, 2, 22, 1 },
-#define F_ASFAKE (F_AS22 + 1)
- { "as", 0, 0, 0, 1 },
-
- /* Cache bypass. */
-#define F_DI5 (F_ASFAKE + 1)
- { "di", 1, 1, 5, 1 },
-#define F_DI11 (F_DI5 + 1)
- { "di", 1, 1, 11, 1 },
-#define F_DI14 (F_DI11 + 1)
- { "di", 1, 1, 14, 1 },
-#define F_DI15 (F_DI14 + 1)
- { "di", 1, 1, 15, 1 },
-
- /* ARCv2 specific. */
-#define F_NT (F_DI15 + 1)
- { "nt", 0, 1, 3, 1},
-#define F_T (F_NT + 1)
- { "t", 1, 1, 3, 1},
-#define F_H1 (F_T + 1)
- { "h", 2, 2, 1, 1 },
-#define F_H7 (F_H1 + 1)
- { "h", 2, 2, 7, 1 },
-#define F_H17 (F_H7 + 1)
- { "h", 2, 2, 17, 1 },
-#define F_SIZED (F_H17 + 1)
- { "dd", 8, 0, 0, 0 }, /* Fake. */
-
- /* Fake Flags. */
-#define F_NE (F_SIZED + 1)
- { "ne", 0, 0, 0, 1 },
-
- /* ARC NPS400 Support: See comment near head of file. */
-#define F_NPS_CL (F_NE + 1)
- { "cl", 0, 0, 0, 1 },
-
-#define F_NPS_NA (F_NPS_CL + 1)
- { "na", 1, 1, 9, 1 },
-
-#define F_NPS_SR (F_NPS_NA + 1)
- { "s", 1, 1, 13, 1 },
-
-#define F_NPS_M (F_NPS_SR + 1)
- { "m", 1, 1, 7, 1 },
-
-#define F_NPS_FLAG (F_NPS_M + 1)
- { "f", 1, 1, 20, 1 },
-
-#define F_NPS_R (F_NPS_FLAG + 1)
- { "r", 1, 1, 15, 1 },
-
-#define F_NPS_RW (F_NPS_R + 1)
- { "rw", 0, 1, 7, 1 },
-
-#define F_NPS_RD (F_NPS_RW + 1)
- { "rd", 1, 1, 7, 1 },
-
-#define F_NPS_WFT (F_NPS_RD + 1)
- { "wft", 0, 0, 0, 1 },
-
-#define F_NPS_IE1 (F_NPS_WFT + 1)
- { "ie1", 1, 2, 8, 1 },
-
-#define F_NPS_IE2 (F_NPS_IE1 + 1)
- { "ie2", 2, 2, 8, 1 },
-
-#define F_NPS_IE12 (F_NPS_IE2 + 1)
- { "ie12", 3, 2, 8, 1 },
-
-#define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
- { "rd", 0, 1, 6, 1 },
-
-#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
- { "wr", 1, 1, 6, 1 },
-
-#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
- { "off", 0, 0, 0, 1 },
-
-#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
- { "restore", 0, 0, 0, 1 },
-
-#define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
- { "sx", 1, 1, 14, 1 },
-
-#define F_NPS_AR (F_NPS_SX + 1)
- { "ar", 0, 1, 0, 1 },
-
-#define F_NPS_AL (F_NPS_AR + 1)
- { "al", 1, 1, 0, 1 },
-
-#define F_NPS_S (F_NPS_AL + 1)
- { "s", 0, 0, 0, 1 },
-
-#define F_NPS_ZNCV_RD (F_NPS_S + 1)
- { "rd", 0, 1, 15, 1 },
-
-#define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
- { "wr", 1, 1, 15, 1 },
-
-#define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
- { "p0", 0, 0, 0, 1 },
-
-#define F_NPS_P1 (F_NPS_P0 + 1)
- { "p1", 0, 0, 0, 1 },
-
-#define F_NPS_P2 (F_NPS_P1 + 1)
- { "p2", 0, 0, 0, 1 },
-
-#define F_NPS_P3 (F_NPS_P2 + 1)
- { "p3", 0, 0, 0, 1 },
-
-#define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
- { "di", 0, 0, 0, 1 },
-
-#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
- { "cl", 1, 1, 6, 1 },
-
-#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
- { "cl", 1, 1, 16, 1 },
-
-#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
- { "x2", 1, 2, 9, 1 },
-
-#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
- { "x2", 1, 2, 22, 1 },
-
-#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
- { "x4", 2, 2, 9, 1 },
-
-#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
- { "x4", 2, 2, 22, 1 },
-
-#define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1)
- { "core", 1, 3, 6, 1 },
-
-#define F_NPS_CLSR (F_NPS_CORE + 1)
- { "clsr", 2, 3, 6, 1 },
-
-#define F_NPS_ALL (F_NPS_CLSR + 1)
- { "all", 3, 3, 6, 1 },
-
-#define F_NPS_GIC (F_NPS_ALL + 1)
- { "gic", 4, 3, 6, 1 },
-
-#define F_NPS_RSPI_GIC (F_NPS_GIC + 1)
- { "gic", 5, 3, 6, 1 },
-};
-
-const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
-
-/* Table of the flag classes.
-
- The format of the table is
- CLASS {FLAG_CODE}. */
-const struct arc_flag_class arc_flag_classes[] =
-{
-#define C_EMPTY 0
- { F_CLASS_NONE, { F_NULL } },
-
-#define C_CC_EQ (C_EMPTY + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} },
-
-#define C_CC_GE (C_CC_EQ + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} },
-
-#define C_CC_GT (C_CC_GE + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} },
-
-#define C_CC_HI (C_CC_GT + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} },
-
-#define C_CC_HS (C_CC_HI + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} },
-
-#define C_CC_LE (C_CC_HS + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} },
-
-#define C_CC_LO (C_CC_LE + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} },
-
-#define C_CC_LS (C_CC_LO + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} },
-
-#define C_CC_LT (C_CC_LS + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} },
-
-#define C_CC_NE (C_CC_LT + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
-
-#define C_AA_AB (C_CC_NE + 1)
- {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} },
-
-#define C_AA_AW (C_AA_AB + 1)
- {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} },
-
-#define C_ZZ_D (C_AA_AW + 1)
- {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} },
-
-#define C_ZZ_H (C_ZZ_D + 1)
- {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} },
-
-#define C_ZZ_B (C_ZZ_H + 1)
- {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
-
-#define C_CC (C_ZZ_B + 1)
- { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
- { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
- F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
- F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
- F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
- F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } },
-
-#define C_AA_ADDR3 (C_CC + 1)
-#define C_AA27 (C_CC + 1)
- { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
-#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
-#define C_AA21 (C_AA_ADDR3 + 1)
- { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
-#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
-#define C_AA8 (C_AA_ADDR9 + 1)
- { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
-
-#define C_F (C_AA_ADDR22 + 1)
- { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
-#define C_FHARD (C_F + 1)
- { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
-
-#define C_T (C_FHARD + 1)
- { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
-#define C_D (C_T + 1)
- { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
-#define C_DNZ_D (C_D + 1)
- { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
-
-#define C_DHARD (C_DNZ_D + 1)
- { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
-
-#define C_DI20 (C_DHARD + 1)
- { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
-#define C_DI14 (C_DI20 + 1)
- { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
-#define C_DI16 (C_DI14 + 1)
- { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
-#define C_DI26 (C_DI16 + 1)
- { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
-
-#define C_X25 (C_DI26 + 1)
- { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
-#define C_X15 (C_X25 + 1)
- { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
-#define C_XHARD (C_X15 + 1)
-#define C_X (C_X15 + 1)
- { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
-
-#define C_ZZ13 (C_X + 1)
- { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
-#define C_ZZ23 (C_ZZ13 + 1)
- { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
-#define C_ZZ29 (C_ZZ23 + 1)
- { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
-
-#define C_AS (C_ZZ29 + 1)
- { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
-
-#define C_NE (C_AS + 1)
- { F_CLASS_REQUIRED, { F_NE, F_NULL}},
-
- /* ARC NPS400 Support: See comment near head of file. */
-#define C_NPS_CL (C_NE + 1)
- { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
-
-#define C_NPS_NA (C_NPS_CL + 1)
- { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
-
-#define C_NPS_SR (C_NPS_NA + 1)
- { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}},
-
-#define C_NPS_M (C_NPS_SR + 1)
- { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}},
-
-#define C_NPS_F (C_NPS_M + 1)
- { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
-
-#define C_NPS_R (C_NPS_F + 1)
- { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
-
-#define C_NPS_SCHD_RW (C_NPS_R + 1)
- { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
-
-#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
- { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
-
-#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
- { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
-
-#define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
- { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
-
-#define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
- { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
-
-#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
- { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
-
-#define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
- { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
-
-#define C_NPS_AR_AL (C_NPS_SX + 1)
- { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
-
-#define C_NPS_S (C_NPS_AR_AL + 1)
- { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
-
-#define C_NPS_ZNCV (C_NPS_S + 1)
- { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
-
-#define C_NPS_P0 (C_NPS_ZNCV + 1)
- { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
-
-#define C_NPS_P1 (C_NPS_P0 + 1)
- { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
-
-#define C_NPS_P2 (C_NPS_P1 + 1)
- { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
-
-#define C_NPS_P3 (C_NPS_P2 + 1)
- { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
-
-#define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
- { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
-
-#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
-
-#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
-
-#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
-
-#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
-
-#define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1)
- { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}},
-
-#define C_NPS_CLSR (C_NPS_CORE + 1)
- { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}},
-
-#define C_NPS_ALL (C_NPS_CLSR + 1)
- { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}},
-
-#define C_NPS_GIC (C_NPS_ALL + 1)
- { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}},
-
-#define C_NPS_RSPI_GIC (C_NPS_GIC + 1)
- { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}},
-};
-
-const unsigned char flags_none[] = { 0 };
-const unsigned char flags_f[] = { C_F };
-const unsigned char flags_cc[] = { C_CC };
-const unsigned char flags_ccf[] = { C_CC, C_F };
-
-/* The operands table.
-
- The format of the operands table is:
-
- BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
-const struct arc_operand arc_operands[] =
-{
- /* The fields are bits, shift, insert, extract, flags. The zero
- index is used to indicate end-of-list. */
-#define UNUSED 0
- { 0, 0, 0, 0, 0, 0 },
-
-#define IGNORED (UNUSED + 1)
- { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
-
- /* The plain integer register fields. Used by 32 bit
- instructions. */
-#define RA (IGNORED + 1)
- { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
-#define RA_CHK (RA + 1)
- { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
-#define RB (RA_CHK + 1)
- { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
-#define RB_CHK (RB + 1)
- { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
-#define RC (RB_CHK + 1)
- { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
-#define RBdup (RC + 1)
- { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
-
-#define RAD (RBdup + 1)
- { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
-#define RAD_CHK (RAD + 1)
- { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
-#define RCD (RAD_CHK + 1)
- { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
-#define RBD (RCD + 1)
- { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb },
-#define RBDdup (RBD + 1)
- { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_TRUNCATE,
- insert_rbd, extract_rb },
-
- /* The plain integer register fields. Used by short
- instructions. */
-#define RA16 (RBDdup + 1)
-#define RA_S (RBDdup + 1)
- { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
-#define RB16 (RA16 + 1)
-#define RB_S (RA16 + 1)
- { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
-#define RB16dup (RB16 + 1)
-#define RB_Sdup (RB16 + 1)
- { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
-#define RC16 (RB16dup + 1)
-#define RC_S (RB16dup + 1)
- { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
-#define R6H (RC16 + 1) /* 6bit register field 'h' used
- by V1 cpus. */
- { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
-#define R5H (R6H + 1) /* 5bit register field 'h' used
- by V2 cpus. */
-#define RH_S (R6H + 1) /* 5bit register field 'h' used
- by V2 cpus. */
- { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
-#define R5Hdup (R5H + 1)
-#define RH_Sdup (R5H + 1)
- { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
- insert_rhv2, extract_rhv2 },
-
-#define RG (R5Hdup + 1)
-#define G_S (R5Hdup + 1)
- { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
-
- /* Fix registers. */
-#define R0 (RG + 1)
-#define R0_S (RG + 1)
- { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
-#define R1 (R0 + 1)
-#define R1_S (R0 + 1)
- { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
-#define R2 (R1 + 1)
-#define R2_S (R1 + 1)
- { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
-#define R3 (R2 + 1)
-#define R3_S (R2 + 1)
- { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
-#define RSP (R3 + 1)
-#define SP_S (R3 + 1)
- { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
-#define SPdup (RSP + 1)
-#define SP_Sdup (RSP + 1)
- { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
-#define GP (SPdup + 1)
-#define GP_S (SPdup + 1)
- { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
-
-#define PCL_S (GP + 1)
- { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
-
-#define BLINK (PCL_S + 1)
-#define BLINK_S (PCL_S + 1)
- { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
-
-#define ILINK1 (BLINK + 1)
- { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
-#define ILINK2 (ILINK1 + 1)
- { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
-
- /* Long immediate. */
-#define LIMM (ILINK2 + 1)
-#define LIMM_S (ILINK2 + 1)
- { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
-#define LIMMdup (LIMM + 1)
- { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
-
- /* Special operands. */
-#define ZA (LIMMdup + 1)
-#define ZB (LIMMdup + 1)
-#define ZA_S (LIMMdup + 1)
-#define ZB_S (LIMMdup + 1)
-#define ZC_S (LIMMdup + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
-
-#define RRANGE_EL (ZA + 1)
- { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
- insert_rrange, extract_rrange},
-#define R13_EL (RRANGE_EL + 1)
- { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
- insert_r13el, extract_rrange },
-#define FP_EL (R13_EL + 1)
- { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
- insert_fpel, extract_fpel },
-#define BLINK_EL (FP_EL + 1)
- { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
- insert_blinkel, extract_blinkel },
-#define PCL_EL (BLINK_EL + 1)
- { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
- insert_pclel, extract_pclel },
-
- /* Fake operand to handle the T flag. */
-#define BRAKET (PCL_EL + 1)
-#define BRAKETdup (PCL_EL + 1)
- { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
-
- /* Fake operand to handle the T flag. */
-#define FKT_T (BRAKET + 1)
- { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
- /* Fake operand to handle the T flag. */
-#define FKT_NT (FKT_T + 1)
- { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
-
- /* UIMM6_20 mask = 00000000000000000000111111000000. */
-#define UIMM6_20 (FKT_NT + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
-
- /* Exactly like the above but used by relaxation. */
-#define UIMM6_20R (UIMM6_20 + 1)
- {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
- insert_uimm6_20, extract_uimm6_20},
-
- /* SIMM12_20 mask = 00000000000000000000111111222222. */
-#define SIMM12_20 (UIMM6_20R + 1)
- {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
-
- /* Exactly like the above but used by relaxation. */
-#define SIMM12_20R (SIMM12_20 + 1)
- {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
- insert_simm12_20, extract_simm12_20},
-
- /* UIMM12_20 mask = 00000000000000000000111111222222. */
-#define UIMM12_20 (SIMM12_20R + 1)
- {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20},
-
- /* SIMM3_5_S mask = 0000011100000000. */
-#define SIMM3_5_S (UIMM12_20 + 1)
- {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
- insert_simm3s, extract_simm3s},
-
- /* UIMM7_A32_11_S mask = 0000000000011111. */
-#define UIMM7_A32_11_S (SIMM3_5_S + 1)
- {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
- extract_uimm7_a32_11_s},
-
- /* The same as above but used by relaxation. */
-#define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1)
- {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
- insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
-
- /* UIMM7_9_S mask = 0000000001111111. */
-#define UIMM7_9_S (UIMM7_A32_11R_S + 1)
- {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
-
- /* UIMM3_13_S mask = 0000000000000111. */
-#define UIMM3_13_S (UIMM7_9_S + 1)
- {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
-
- /* Exactly like the above but used for relaxation. */
-#define UIMM3_13R_S (UIMM3_13_S + 1)
- {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
- insert_uimm3_13_s, extract_uimm3_13_s},
-
- /* SIMM11_A32_7_S mask = 0000000111111111. */
-#define SIMM11_A32_7_S (UIMM3_13R_S + 1)
- {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
-
- /* UIMM6_13_S mask = 0000000002220111. */
-#define UIMM6_13_S (SIMM11_A32_7_S + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
- /* UIMM5_11_S mask = 0000000000011111. */
-#define UIMM5_11_S (UIMM6_13_S + 1)
- {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
- extract_uimm5_11_s},
-
- /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
-#define SIMM9_A16_8 (UIMM5_11_S + 1)
- {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
- extract_simm9_a16_8},
-
- /* UIMM6_8 mask = 00000000000000000000111111000000. */
-#define UIMM6_8 (SIMM9_A16_8 + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
-
- /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
-#define SIMM21_A16_5 (UIMM6_8 + 1)
- {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
- | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
- insert_simm21_a16_5, extract_simm21_a16_5},
-
- /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
-#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
- {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
- | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
- insert_simm25_a16_5, extract_simm25_a16_5},
-
- /* SIMM10_A16_7_S mask = 0000000111111111. */
-#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
- {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
- extract_simm10_a16_7_s},
-
-#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
- {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
-
- /* SIMM7_A16_10_S mask = 0000000000111111. */
-#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
- {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
- extract_simm7_a16_10_s},
-
- /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
-#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
- {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
- extract_simm21_a32_5},
-
- /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
-#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
- {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
- extract_simm25_a32_5},
-
- /* SIMM13_A32_5_S mask = 0000011111111111. */
-#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
- {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
- extract_simm13_a32_5_s},
-
- /* SIMM8_A16_9_S mask = 0000000001111111. */
-#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
- {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
- extract_simm8_a16_9_s},
-
-/* UIMM10_6_S_JLIOFF mask = 0000001111111111. */
-#define UIMM10_6_S_JLIOFF (SIMM8_A16_9_S + 1)
- {12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED
- | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s,
- extract_uimm10_6_s},
-
- /* UIMM3_23 mask = 00000000000000000000000111000000. */
-#define UIMM3_23 (UIMM10_6_S_JLIOFF + 1)
- {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
-
- /* UIMM10_6_S mask = 0000001111111111. */
-#define UIMM10_6_S (UIMM3_23 + 1)
- {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
-
- /* UIMM6_11_S mask = 0000002200011110. */
-#define UIMM6_11_S (UIMM10_6_S + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
-
- /* SIMM9_8 mask = 00000000111111112000000000000000. */
-#define SIMM9_8 (UIMM6_11_S + 1)
- {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
- insert_simm9_8, extract_simm9_8},
-
- /* The same as above but used by relaxation. */
-#define SIMM9_8R (SIMM9_8 + 1)
- {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
- | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
-
- /* UIMM10_A32_8_S mask = 0000000011111111. */
-#define UIMM10_A32_8_S (SIMM9_8R + 1)
- {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
- extract_uimm10_a32_8_s},
-
- /* SIMM9_7_S mask = 0000000111111111. */
-#define SIMM9_7_S (UIMM10_A32_8_S + 1)
- {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
- extract_simm9_7_s},
-
- /* UIMM6_A16_11_S mask = 0000000000011111. */
-#define UIMM6_A16_11_S (SIMM9_7_S + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
- extract_uimm6_a16_11_s},
-
- /* UIMM5_A32_11_S mask = 0000020000011000. */
-#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
- {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
- extract_uimm5_a32_11_s},
-
- /* SIMM11_A32_13_S mask = 0000022222200111. */
-#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
- {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
-
- /* UIMM7_13_S mask = 0000000022220111. */
-#define UIMM7_13_S (SIMM11_A32_13_S + 1)
- {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
-
- /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
-#define UIMM6_A16_21 (UIMM7_13_S + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
-
- /* UIMM7_11_S mask = 0000022200011110. */
-#define UIMM7_11_S (UIMM6_A16_21 + 1)
- {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
-
- /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
-#define UIMM7_A16_20 (UIMM7_11_S + 1)
- {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
- extract_uimm7_a16_20},
-
- /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
-#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
- {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
- extract_simm13_a16_20},
-
- /* UIMM8_8_S mask = 0000000011111111. */
-#define UIMM8_8_S (SIMM13_A16_20 + 1)
- {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
-
- /* The same as above but used for relaxation. */
-#define UIMM8_8R_S (UIMM8_8_S + 1)
- {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
- insert_uimm8_8_s, extract_uimm8_8_s},
-
- /* W6 mask = 00000000000000000000111111000000. */
-#define W6 (UIMM8_8R_S + 1)
- {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
-
- /* UIMM6_5_S mask = 0000011111100000. */
-#define UIMM6_5_S (W6 + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
-
- /* ARC NPS400 Support: See comment near head of file. */
-#define NPS_R_DST_3B (UIMM6_5_S + 1)
- { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
-
-#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
- { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
-
-#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
- { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
-
-#define NPS_R_DST (NPS_R_SRC2_3B + 1)
- { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
-
-#define NPS_R_SRC1 (NPS_R_DST + 1)
- { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
-
-#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
- { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
-
-#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
- { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
-
-#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
- { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bitop_size, extract_nps_bitop_size },
-
-#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
- { 5, 0, 0, ARC_OPERAND_UNSIGNED,
- insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
-
-#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
-
-#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
- { 8, 0, 0, ARC_OPERAND_UNSIGNED,
- insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
-
-#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
- { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_SIMM16 (NPS_UIMM16 + 1)
- { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
-
-#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
- { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
-
-#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
- { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
-
-#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_src2_pos, extract_nps_src2_pos },
-
-#define NPS_SRC1_POS (NPS_SRC2_POS + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_src1_pos, extract_nps_src1_pos },
-
-#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_addb_size, extract_nps_addb_size },
-
-#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_andb_size, extract_nps_andb_size },
-
-#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_fxorb_size, extract_nps_fxorb_size },
-
-#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_wxorb_size, extract_nps_wxorb_size },
-
-#define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
- { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
-
-#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
- { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_qcmp_size, extract_nps_qcmp_size },
-
-#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
- { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
-
-#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
- { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
-
-#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
- { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
-
-#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_calc_entry_size, extract_nps_calc_entry_size },
-
-#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
- { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
-
-#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
- { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
-
-#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
- { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
-
-#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
- { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bitop2_size, extract_nps_bitop2_size },
-
-#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
- { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bitop1_size, extract_nps_bitop1_size },
-
-#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
- { 5, 0, 0, ARC_OPERAND_UNSIGNED,
- insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
-
-#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
- { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
- { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
- { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
- { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
- { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
- { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
- { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
- { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
- { 2, 0, 0, ARC_OPERAND_UNSIGNED,
- insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
-
-#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
- { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
- { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
- { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
- { 5, 20, 0, ARC_OPERAND_UNSIGNED,
- insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
-
-#define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
- { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
- { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_field_size, extract_nps_field_size },
-
-#define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
- { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_shift_factor, extract_nps_shift_factor },
-
-#define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
- { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
-
-#define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
- { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
- { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
-
-#define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
- { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_min_hofs, extract_nps_min_hofs },
-
-#define NPS_PSBC (NPS_MIN_HOFS + 1)
- { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_DPI_DST (NPS_PSBC + 1)
- { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
-
- /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B
- but doesn't duplicate an operand. */
-#define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
- { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
-
-#define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
- { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_hash_width, extract_nps_hash_width },
-
-#define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
- { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
- { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
- { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
- { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_hash_len, extract_nps_hash_len },
-
-#define NPS_HASH_OFS (NPS_HASH_LEN + 1)
- { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
- { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
- { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
- { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
- { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
- { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_index3, extract_nps_index3 },
-
-#define COLON (NPS_E4BY_INDEX3 + 1)
- { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
-
-#define NPS_BD (COLON + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_bd, extract_nps_bd },
-
-#define NPS_JID (NPS_BD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_jid, extract_nps_jid },
-
-#define NPS_LBD (NPS_JID + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_lbd, extract_nps_lbd },
-
-#define NPS_MBD (NPS_LBD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_mbd, extract_nps_mbd },
-
-#define NPS_SD (NPS_MBD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_sd, extract_nps_sd },
-
-#define NPS_SM (NPS_SD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_sm, extract_nps_sm },
-
-#define NPS_XA (NPS_SM + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_xa, extract_nps_xa },
-
-#define NPS_XD (NPS_XA + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_xd, extract_nps_xd },
-
-#define NPS_CD (NPS_XD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cd, extract_nps_cd },
-
-#define NPS_CBD (NPS_CD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cbd, extract_nps_cbd },
-
-#define NPS_CJID (NPS_CBD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cjid, extract_nps_cjid },
-
-#define NPS_CLBD (NPS_CJID + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_clbd, extract_nps_clbd },
-
-#define NPS_CM (NPS_CLBD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cm, extract_nps_cm },
-
-#define NPS_CSD (NPS_CM + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_csd, extract_nps_csd },
-
-#define NPS_CXA (NPS_CSD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cxa, extract_nps_cxa },
-
-#define NPS_CXD (NPS_CXA + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cxd, extract_nps_cxd },
-
-#define NPS_BD_TYPE (NPS_CXD + 1)
- { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
- { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bd_num_buff, extract_nps_bd_num_buff },
-
-#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
- { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1)
- { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_size_16bit, extract_nps_size_16bit },
-
-#define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1)
- { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_pmu_num_job, extract_nps_pmu_num_job },
-
-#define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1)
- { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_imm_entry, extract_nps_imm_entry },
-
-#define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1)
- { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_imm_offset, extract_nps_imm_offset },
-
-#define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1)
- { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL },
-
-#define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1)
- { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_misc_imm_offset, extract_nps_misc_imm_offset },
-
-#define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1)
- { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
-
-#define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
- { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
-
-#define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
- { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
-
-#define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
- { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
-
-#define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
- { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
-
-#define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
- { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
-
-#define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
- { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL },
-
-#define NPS_RB_64 (NPS_RA_64 + 1)
- { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL },
-
-#define NPS_RBdup_64 (NPS_RB_64 + 1)
- { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
-
-#define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
- { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_rbdouble_64, extract_nps_rbdouble_64 },
-
-#define NPS_RC_64 (NPS_RBdouble_64 + 1)
- { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL },
-
-#define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
- { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
- { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_proto_size, extract_nps_proto_size }
-};
-const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
-
-const unsigned arc_Toperand = FKT_T;
-const unsigned arc_NToperand = FKT_NT;
-
-const unsigned char arg_none[] = { 0 };
-const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
-const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
-const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
-const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
-const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
-const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
-const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
-const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
-const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
-const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
-const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
-
-const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
-const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
-const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
-
-const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
-const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
-const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
-
-const unsigned char arg_32bit_rbrc[] = { RB, RC };
-const unsigned char arg_32bit_zarc[] = { ZA, RC };
-const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
-const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
-const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
-const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
-
-const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
-const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
-const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
-const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
-
-const unsigned char arg_32bit_rc[] = { RC };
-const unsigned char arg_32bit_u6[] = { UIMM6_20 };
-const unsigned char arg_32bit_limm[] = { LIMM };
+#include "arcxx-opc.inc"
+
+/* Common combinations of FLAGS. */
+#define FLAGS_NONE { 0 }
+#define FLAGS_F { C_F }
+#define FLAGS_CC { C_CC }
+#define FLAGS_CCF { C_CC, C_F }
+
+/* Common combination of arguments. */
+#define ARG_NONE { 0 }
+#define ARG_32BIT_RARBRC { RA, RB, RC }
+#define ARG_32BIT_ZARBRC { ZA, RB, RC }
+#define ARG_32BIT_RBRBRC { RB, RBdup, RC }
+#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
+#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
+#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
+#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
+#define ARG_32BIT_RALIMMRC { RA, LIMM, RC }
+#define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
+#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC }
+#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
+
+#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM }
+#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 }
+#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 }
+
+#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 }
+#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup }
+#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup }
+
+#define ARG_32BIT_RBRC { RB, RC }
+#define ARG_32BIT_ZARC { ZA, RC }
+#define ARG_32BIT_RBU6 { RB, UIMM6_20 }
+#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 }
+#define ARG_32BIT_RBLIMM { RB, LIMM }
+#define ARG_32BIT_ZALIMM { ZA, LIMM }
+
+/* Macro to generate 2 operand extension instruction. */
+#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \
+ { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRC, FL }, \
+ { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARC, FL }, \
+ { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBU6, FL }, \
+ { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZAU6, FL }, \
+ { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBLIMM, FL }, \
+ { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMM, FL },
+
+#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
+ EXTINSN2OPF (NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F)
+
+/* Macro to generate 3 operand extesion instruction. */
+#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
+ { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBRC, FLAGS_CCF }, \
+ { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBU6, FLAGS_CCF }, \
+ { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBS12, FLAGS_F }, \
+ { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \
+ { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \
+ { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMU6, FLAGS_F }, \
+ { NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMU6, FLAGS_F }, \
+ { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \
+ { NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMS12, FLAGS_F }, \
+ { NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMLIMM, FLAGS_CCF },
/* The opcode table.
@@ -2644,307 +152,19 @@ const unsigned char arg_32bit_limm[] = { LIMM };
mnemonic, so we end up with two groups for the sync instruction, the
first within the core arc instruction table, and the second within the
nps extension instructions. */
+
const struct arc_opcode arc_opcodes[] =
{
#include "arc-tbl.h"
#include "arc-nps400-tbl.h"
-#include "arc-ext-tbl.h"
-
- { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
-};
-
-/* List with special cases instructions and the applicable flags. */
-const struct arc_flag_special arc_flag_special_cases[] =
-{
- { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM,
- F_NO_T, F_NULL } },
- { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
- { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
-};
-
-const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
-
-/* Relocations. */
-const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
-{
- { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
- { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
- { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
- { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
-
- /* Next two entries will cover the undefined behavior ldb/stb with
- address scaling. */
- { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
- { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
-
- { "sda", "ld", { F_ASFAKE, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
- { "sda", "st", { F_ASFAKE, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
- { "sda", "ldd", { F_ASFAKE, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
- { "sda", "std", { F_ASFAKE, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
-
- /* Short instructions. */
- { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
- { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
- { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
- { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
-
- { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
- { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
-
- { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
- BFD_RELOC_ARC_S25H_PCREL_PLT },
- { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
- BFD_RELOC_ARC_S21H_PCREL_PLT },
- { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
- BFD_RELOC_ARC_S25W_PCREL_PLT },
- { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
- BFD_RELOC_ARC_S21W_PCREL_PLT },
-
- { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
-};
-
-const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
-
-const struct arc_pseudo_insn arc_pseudo_insns[] =
-{
- { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
- { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
- { BRAKETdup, 1, 0, 4} } },
- { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
- { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
- { BRAKETdup, 1, 0, 4} } },
-
- { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
-
- { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
-
- { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
-
- { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
-};
-
-const unsigned arc_num_pseudo_insn =
- sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
-
-const struct arc_aux_reg arc_aux_regs[] =
-{
-#undef DEF
-#define DEF(ADDR, CPU, SUBCLASS, NAME) \
- { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
-
-#include "arc-regs.h"
-#undef DEF
-};
-
-const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
-
-/* NOTE: The order of this array MUST be consistent with 'enum
- arc_rlx_types' located in tc-arc.h! */
-const struct arc_opcode arc_relax_opcodes[] =
-{
- { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
-
- /* bl_s s13 11111sssssssssss. */
- { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
- { SIMM13_A32_5_S }, { 0 }},
-
- /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
- { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
- { SIMM25_A32_5 }, { C_D }},
-
- /* b_s s10 1111000sssssssss. */
- { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
- { SIMM10_A16_7_S }, { 0 }},
-
- /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
- { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
- { SIMM25_A16_5 }, { C_D }},
-
- /* add_s c,b,u3 01101bbbccc00uuu. */
- { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
-
- /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
- { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RA, RB, UIMM6_20R }, { C_F }},
-
- /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
- { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RA, RB, LIMM }, { C_F }},
-
- /* ld_s c,b,u7 10000bbbcccuuuuu. */
- { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
-
- /* ld<.di><.aa><.x><zz> a,b,s9
- 00010bbbssssssssSBBBDaaZZXAAAAAA. */
- { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
- { C_ZZ23, C_DI20, C_AA21, C_X25 }},
-
- /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
- { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RA, BRAKET, RB, LIMM, BRAKETdup },
- { C_ZZ13, C_DI16, C_AA8, C_X15 }},
-
- /* mov_s b,u8 11011bbbuuuuuuuu. */
- { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB_S, UIMM8_8R_S }, { 0 }},
-
- /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
- { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB, SIMM12_20R }, { C_F }},
+ /* Extension instruction declarations. */
+ EXTINSN2OP ("dsp_fp_flt2i", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
+ EXTINSN2OP ("dsp_fp_i2flt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 44)
+ EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 45)
- /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
- { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB, LIMM }, { C_F }},
+ EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 42)
+ EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
- /* sub_s c,b,u3 01101bbbccc01uuu. */
- { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
-
- /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
- { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RA, RB, UIMM6_20R }, { C_F }},
-
- /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
- { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RA, RB, LIMM }, { C_F }},
-
- /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
- { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
- | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
-
- /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
- { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
- | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
-
- /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
- { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB, UIMM6_20R }, { C_F, C_CC }},
-
- /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
- { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB, LIMM }, { C_F, C_CC }},
-
- /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
- { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
-
- /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
- { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RB, RBdup, LIMM }, { C_F, C_CC }}
+ { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
};
-
-const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
-
-/* Return length of an opcode in bytes. */
-
-int
-arc_opcode_len (const struct arc_opcode *opcode)
-{
- if (opcode->mask < 0x10000ull)
- return 2;
-
- if (opcode->mask < 0x100000000ull)
- return 4;
-
- if (opcode->mask < 0x1000000000000ull)
- return 6;
-
- return 8;
-}
diff --git a/opcodes/arc-operands.def b/opcodes/arc-operands.def
new file mode 100644
index 00000000000..b7aae00e5d8
--- /dev/null
+++ b/opcodes/arc-operands.def
@@ -0,0 +1,502 @@
+/* ARC operands defintions.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+ Refactored by Cupertino Miranda (cmiranda@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+
+/*
+ * ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, FUN)
+ *
+ * BITS => The number of bits in the operand.
+ * SHIFT => How far the operand is left shifted in the instruction.
+ * RELO => The default relocation type for this operand.
+ * FLAGS => One bit syntax flags.
+ * FUN => Insertion function. This is used by the assembler.
+*/
+
+ARC_OPERAND(IGNORED, 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0)
+
+/* The plain integer register fields. Used by 32 bit instructions. */
+ARC_OPERAND(RA, 6, 0, 0, ARC_OPERAND_IR, 0, 0)
+ARC_OPERAND(RA_CHK, 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0)
+ARC_OPERAND(RB, 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb)
+ARC_OPERAND(RB_CHK, 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb)
+ARC_OPERAND(RBB_S, 6, 12, 0, ARC_OPERAND_IR, insert_rbb, extract_rbb)
+ARC_OPERAND(RC, 6, 6, 0, ARC_OPERAND_IR, 0, 0)
+ARC_OPERAND(RC_CHK, 6, 6, 0, ARC_OPERAND_IR, 0, 0)
+ARC_OPERAND(RBdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb)
+
+ARC_OPERAND(RAD, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0)
+ARC_OPERAND(RAD_CHK, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0)
+ARC_OPERAND(RCD, 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0)
+ARC_OPERAND(RBD, 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb)
+ARC_OPERAND(RBDdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb)
+
+/* The plain integer register fields. Used by short instructions. */
+ARC_OPERAND(RA16, 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras)
+ARC_OPERAND(RA_S, 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras)
+ARC_OPERAND(RB16, 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs)
+ARC_OPERAND(RB_S, 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs)
+ARC_OPERAND(RB16dup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs)
+ARC_OPERAND(RB_Sdup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs)
+ARC_OPERAND(RC16, 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs)
+ARC_OPERAND(RC_S, 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs)
+
+/* 6bit register field 'h' used by V1 cpus. */
+ARC_OPERAND(R6H, 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1)
+/* 5bit register field 'h' used by V2 cpus. */
+ARC_OPERAND(R5H, 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2)
+ARC_OPERAND(RH_S, 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2)
+ARC_OPERAND(R5Hdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rhv2, extract_rhv2)
+ARC_OPERAND(RH_Sdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rhv2, extract_rhv2)
+
+ARC_OPERAND(RG, 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s)
+ARC_OPERAND(G_S, 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s)
+
+/* Fix registers. */
+ARC_OPERAND(R0, 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0)
+ARC_OPERAND(R0_S, 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0)
+ARC_OPERAND(R1, 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1)
+ARC_OPERAND(R1_S, 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1)
+ARC_OPERAND(R2, 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2)
+ARC_OPERAND(R2_S, 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2)
+ARC_OPERAND(R3, 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3)
+ARC_OPERAND(R3_S, 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3)
+ARC_OPERAND(RSP, 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp)
+ARC_OPERAND(SP_S, 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp)
+ARC_OPERAND(SPdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp)
+ARC_OPERAND(SP_Sdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp)
+ARC_OPERAND(GP, 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp)
+ARC_OPERAND(GP_S, 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp)
+
+ARC_OPERAND(PCL_S, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl)
+
+ARC_OPERAND(BLINK, 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink)
+ARC_OPERAND(BLINK_S, 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink)
+
+ARC_OPERAND(ILINK1, 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1)
+ARC_OPERAND(ILINK2, 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2)
+
+ /* Long immediate. */
+ARC_OPERAND(LIMM, 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0)
+ARC_OPERAND(LIMM_S, 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0)
+ARC_OPERAND(LO32, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM, insert_limm, 0)
+ARC_OPERAND(HI32, 32, 0, BFD_RELOC_ARC_HI32_ME, ARC_OPERAND_LIMM, insert_limm, 0)
+ARC_OPERAND(LIMM34, 34, 0, BFD_RELOC_ARC_PCLO32_ME_2, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_limm, 0)
+ARC_OPERAND(XIMM_S, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_limm, 0)
+ARC_OPERAND(XIMM, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_limm, 0)
+ARC_OPERAND(LIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0)
+ARC_OPERAND(XIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE | ARC_OPERAND_SIGNED, insert_limm, 0)
+
+ /* Special operands. */
+ARC_OPERAND(ZA, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0)
+ARC_OPERAND(ZB, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0)
+ARC_OPERAND(ZA_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0)
+ARC_OPERAND(ZB_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0)
+ARC_OPERAND(ZC_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0)
+
+ARC_OPERAND(RRANGE_EL, 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, insert_rrange, extract_rrange)
+ARC_OPERAND(R13_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_r13el, extract_rrange)
+ARC_OPERAND(FP_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_fpel, extract_fpel)
+ARC_OPERAND(BLINK_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_blinkel, extract_blinkel)
+ARC_OPERAND(PCL_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_pclel, extract_pclel)
+
+ /* Fake operand to handle the T flag. */
+ARC_OPERAND(BRAKET, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0)
+ARC_OPERAND(BRAKETdup, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0)
+
+ /* Fake operand to handle the T flag. */
+ARC_OPERAND(FKT_T, 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0)
+ /* Fake operand to handle the T flag. */
+ARC_OPERAND(FKT_NT, 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0)
+
+ /* UIMM6_20 mask = 00000000000000000000111111000000. */
+ARC_OPERAND(UIMM6_20, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20)
+
+ /* Exactly like the above but used by relaxation. */
+ARC_OPERAND(UIMM6_20R, 6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm6_20, extract_uimm6_20)
+
+ /* SIMM12_20 mask = 00000000000000000000111111222222. */
+ARC_OPERAND(SIMM12_20, 12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20)
+
+ /* Exactly like the above but used by relaxation. */
+ARC_OPERAND(SIMM12_20R, 12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL, insert_simm12_20, extract_simm12_20)
+
+ /* UIMM12_20 mask = 00000000000000000000111111222222. */
+ARC_OPERAND(UIMM12_20, 12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20)
+
+ /* SIMM3_5_S mask = 0000011100000000. */
+ARC_OPERAND(SIMM3_5_S, 3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, insert_simm3s, extract_simm3s)
+
+ /* UIMM7_A32_11_S mask = 0000000000011111. */
+ARC_OPERAND(UIMM7_A32_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s, extract_uimm7_a32_11_s)
+
+ /* The same as above but used by relaxation. */
+ARC_OPERAND(UIMM7_A32_11R_S, 7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, insert_uimm7_a32_11_s, extract_uimm7_a32_11_s)
+
+ARC_OPERAND(UIMM9_A32_11_S, 9, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm9_a32_11_s, extract_uimm9_a32_11_s)
+
+ /* UIMM7_9_S mask = 0000000001111111. */
+ARC_OPERAND(UIMM7_9_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s)
+
+ /* UIMM3_13_S mask = 0000000000000111. */
+ARC_OPERAND(UIMM3_13_S, 3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s)
+
+ /* Exactly like the above but used for relaxation. */
+ARC_OPERAND(UIMM3_13R_S, 3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm3_13_s, extract_uimm3_13_s)
+
+ /* SIMM11_A32_7_S mask = 0000000111111111. */
+ARC_OPERAND(SIMM11_A32_7_S, 11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s)
+
+ /* UIMM6_13_S mask = 0000000002220111. */
+ARC_OPERAND(UIMM6_13_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s)
+ /* UIMM5_11_S mask = 0000000000011111. */
+ARC_OPERAND(UIMM5_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s, extract_uimm5_11_s)
+
+ /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
+ARC_OPERAND(SIMM9_A16_8, 9, 0, BFD_RELOC_ARC_S9H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8, extract_simm9_a16_8)
+
+ /* UIMM6_8 mask = 00000000000000000000111111000000. */
+ARC_OPERAND(UIMM6_8, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8)
+
+ /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
+ARC_OPERAND(SIMM21_A16_5, 21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a16_5, extract_simm21_a16_5)
+
+ /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
+ARC_OPERAND(SIMM25_A16_5, 25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a16_5, extract_simm25_a16_5)
+
+ /* SIMM10_A16_7_S mask = 0000000111111111. */
+ARC_OPERAND(SIMM10_A16_7_S, 10, 0, BFD_RELOC_ARC_S10H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s, extract_simm10_a16_7_s)
+
+ARC_OPERAND(SIMM10_A16_7_Sbis, 10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s)
+
+ /* SIMM7_A16_10_S mask = 0000000000111111. */
+ARC_OPERAND(SIMM7_A16_10_S, 7, 0, BFD_RELOC_ARC_S7H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s, extract_simm7_a16_10_s)
+
+ /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
+ARC_OPERAND(SIMM21_A32_5, 21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5, extract_simm21_a32_5)
+
+ /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
+ARC_OPERAND(SIMM25_A32_5, 25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5, extract_simm25_a32_5)
+
+ /* SIMM13_A32_5_S mask = 0000011111111111. */
+ARC_OPERAND(SIMM13_A32_5_S, 13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s, extract_simm13_a32_5_s)
+
+ /* SIMM8_A16_9_S mask = 0000000001111111. */
+ARC_OPERAND(SIMM8_A16_9_S, 8, 0, BFD_RELOC_ARC_S8H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s, extract_simm8_a16_9_s)
+
+/* UIMM10_6_S_JLIOFF mask = 0000001111111111. */
+ARC_OPERAND(UIMM10_6_S_JLIOFF, 12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s, extract_uimm10_6_s)
+
+ /* UIMM3_23 mask = 00000000000000000000000111000000. */
+ARC_OPERAND(UIMM3_23, 3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23)
+
+ /* UIMM10_6_S mask = 0000001111111111. */
+ARC_OPERAND(UIMM10_6_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s)
+
+ARC_OPERAND(UIMM10_13_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_13_s, extract_uimm10_13_s)
+
+ /* UIMM6_11_S mask = 0000002200011110. */
+ARC_OPERAND(UIMM6_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s)
+
+ /* SIMM9_8 mask = 00000000111111112000000000000000. */
+ARC_OPERAND(SIMM9_8, 9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, insert_simm9_8, extract_simm9_8)
+
+ /* The same as above but used by relaxation. */
+ARC_OPERAND(SIMM9_8R, 9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8)
+
+ /* UIMM10_A32_8_S mask = 0000000011111111. */
+ARC_OPERAND(UIMM10_A32_8_S, 10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s, extract_uimm10_a32_8_s)
+
+ /* SIMM9_7_S mask = 0000000111111111. */
+ARC_OPERAND(SIMM9_7_S, 9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s, extract_simm9_7_s)
+
+ /* UIMM6_A16_11_S mask = 0000000000011111. */
+ARC_OPERAND(UIMM6_A16_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s, extract_uimm6_a16_11_s)
+
+ /* UIMM5_A32_11_S mask = 0000020000011000. */
+ARC_OPERAND(UIMM5_A32_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s, extract_uimm5_a32_11_s)
+
+ /* SIMM11_A32_13_S mask = 0000022222200111. */
+ARC_OPERAND(SIMM11_A32_13_S, 11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s)
+
+ /* UIMM7_13_S mask = 0000000022220111. */
+ARC_OPERAND(UIMM7_13_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s)
+
+ /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
+ARC_OPERAND(UIMM6_A16_21, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21)
+
+ /* UIMM7_11_S mask = 0000022200011110. */
+ARC_OPERAND(UIMM7_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s)
+
+ /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
+ARC_OPERAND(UIMM7_A16_20, 7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20, extract_uimm7_a16_20)
+
+ /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
+ARC_OPERAND(SIMM13_A16_20, 13, 0, BFD_RELOC_ARC_S13H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20, extract_simm13_a16_20)
+
+ /* UIMM8_8_S mask = 0000000011111111. */
+ARC_OPERAND(UIMM8_8_S, 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s)
+
+ /* The same as above but used for relaxation. */
+ARC_OPERAND(UIMM8_8R_S, 8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm8_8_s, extract_uimm8_8_s)
+
+ /* W6 mask = 00000000000000000000111111000000. */
+ARC_OPERAND(W6, 6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6)
+
+ /* UIMM6_5_S mask = 0000011111100000. */
+ARC_OPERAND(UIMM6_5_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s)
+
+ /* ARC NPS400 Support: See comment near head of file. */
+ARC_OPERAND(NPS_R_DST_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst)
+
+ARC_OPERAND(NPS_R_SRC1_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst)
+
+ARC_OPERAND(NPS_R_SRC2_3B, 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2)
+
+ARC_OPERAND(NPS_R_DST, 6, 21, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ARC_OPERAND(NPS_R_SRC1, 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_DST_POS, 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0)
+
+ARC_OPERAND(NPS_BITOP_SRC_POS, 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0)
+
+ARC_OPERAND(NPS_BITOP_SIZE, 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size)
+
+ARC_OPERAND(NPS_BITOP_DST_POS_SZ, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size)
+
+ARC_OPERAND(NPS_BITOP_SIZE_2B, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b)
+
+ARC_OPERAND(NPS_BITOP_UIMM8, 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8)
+
+ARC_OPERAND(NPS_UIMM16, 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_SIMM16, 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_RFLT_UIMM6, 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6)
+
+ARC_OPERAND(NPS_XLDST_UIMM16, 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16)
+
+ARC_OPERAND(NPS_SRC2_POS, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos)
+
+ARC_OPERAND(NPS_SRC1_POS, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos)
+
+ARC_OPERAND(NPS_ADDB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size)
+
+ARC_OPERAND(NPS_ANDB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size)
+
+ARC_OPERAND(NPS_FXORB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size)
+
+ARC_OPERAND(NPS_WXORB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size)
+
+ARC_OPERAND(NPS_R_XLDST, 6, 5, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ARC_OPERAND(NPS_DIV_UIMM4, 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_QCMP_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size)
+
+ARC_OPERAND(NPS_QCMP_M1, 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1)
+
+ARC_OPERAND(NPS_QCMP_M2, 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2)
+
+ARC_OPERAND(NPS_QCMP_M3, 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3)
+
+ARC_OPERAND(NPS_CALC_ENTRY_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size)
+
+ARC_OPERAND(NPS_R_DST_3B_SHORT, 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst)
+
+ARC_OPERAND(NPS_R_SRC1_3B_SHORT, 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst)
+
+ARC_OPERAND(NPS_R_SRC2_3B_SHORT, 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2)
+
+ARC_OPERAND(NPS_BITOP_SIZE2, 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size)
+
+ARC_OPERAND(NPS_BITOP_SIZE1, 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size)
+
+ARC_OPERAND(NPS_BITOP_DST_POS3_POS4, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4)
+
+ARC_OPERAND(NPS_BITOP_DST_POS4, 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_DST_POS3, 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_DST_POS2, 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_DST_POS1, 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_SRC_POS4, 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_SRC_POS3, 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_SRC_POS2, 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_SRC_POS1, 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_MOD4, 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4, extract_nps_bitop_mod4)
+
+ARC_OPERAND(NPS_BITOP_MOD3, 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_MOD2, 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_MOD1, 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_INS_EXT, 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext)
+
+ARC_OPERAND(NPS_FIELD_START_POS, 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_FIELD_SIZE, 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size)
+
+ARC_OPERAND(NPS_SHIFT_FACTOR, 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor)
+
+ARC_OPERAND(NPS_BITS_TO_SCRAMBLE, 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble)
+
+ARC_OPERAND(NPS_SRC2_POS_5B, 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BDLEN_MAX_LEN, 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len)
+
+ARC_OPERAND(NPS_MIN_HOFS, 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs)
+
+ARC_OPERAND(NPS_PSBC, 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_DPI_DST, 5, 11, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B
+ but doesn't duplicate an operand. */
+ARC_OPERAND(NPS_DPI_SRC1_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst)
+
+ARC_OPERAND(NPS_HASH_WIDTH, 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width)
+
+ARC_OPERAND(NPS_HASH_PERM, 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_HASH_NONLINEAR, 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_HASH_BASEMAT, 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_HASH_LEN, 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len)
+
+ARC_OPERAND(NPS_HASH_OFS, 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_HASH_BASEMAT2, 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_E4BY_INDEX0, 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_E4BY_INDEX1, 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_E4BY_INDEX2, 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_E4BY_INDEX3, 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3)
+
+ARC_OPERAND(COLON, 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL)
+
+ARC_OPERAND(NPS_BD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd)
+
+ARC_OPERAND(NPS_JID, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid)
+
+ARC_OPERAND(NPS_LBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd)
+
+ARC_OPERAND(NPS_MBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd)
+
+ARC_OPERAND(NPS_SD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd)
+
+ARC_OPERAND(NPS_SM, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm)
+
+ARC_OPERAND(NPS_XA, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa)
+
+ARC_OPERAND(NPS_XD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd)
+
+ARC_OPERAND(NPS_CD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd)
+
+ARC_OPERAND(NPS_CBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd)
+
+ARC_OPERAND(NPS_CJID, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid)
+
+ARC_OPERAND(NPS_CLBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd)
+
+ARC_OPERAND(NPS_CM, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm)
+
+ARC_OPERAND(NPS_CSD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd)
+
+ARC_OPERAND(NPS_CXA, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa)
+
+ARC_OPERAND(NPS_CXD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd)
+
+ARC_OPERAND(NPS_BD_TYPE, 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BMU_NUM, 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff)
+
+ARC_OPERAND(NPS_PMU_NXT_DST, 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_WHASH_SIZE, 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_size_16bit, extract_nps_size_16bit)
+
+ARC_OPERAND(NPS_PMU_NUM_JOB, 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job)
+
+ARC_OPERAND(NPS_DMA_IMM_ENTRY, 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_entry, extract_nps_imm_entry)
+
+ARC_OPERAND(NPS_DMA_IMM_OFFSET, 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_offset, extract_nps_imm_offset)
+
+ARC_OPERAND(NPS_MISC_IMM_SIZE, 7, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_MISC_IMM_OFFSET, 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_misc_imm_offset, extract_nps_misc_imm_offset)
+
+ARC_OPERAND(NPS_R_DST_3B_48, 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst)
+
+ARC_OPERAND(NPS_R_SRC1_3B_48, 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst)
+
+ARC_OPERAND(NPS_R_SRC2_3B_48, 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2)
+
+ARC_OPERAND(NPS_R_DST_3B_64, 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst)
+
+ARC_OPERAND(NPS_R_SRC1_3B_64, 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst)
+
+ARC_OPERAND(NPS_R_SRC2_3B_64, 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2)
+
+ARC_OPERAND(NPS_RA_64, 6, 53, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ARC_OPERAND(NPS_RB_64, 5, 48, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ARC_OPERAND(NPS_RBdup_64, 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL)
+
+ARC_OPERAND(NPS_RBdouble_64, 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_rbdouble_64, extract_nps_rbdouble_64)
+
+ARC_OPERAND(NPS_RC_64, 5, 43, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ARC_OPERAND(NPS_UIMM16_0_64, 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_PROTO_SIZE, 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_proto_size, extract_nps_proto_size)
+
+ /* ARC64's floating point registers. */
+ARC_OPERAND(FA, 5, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0)
+ARC_OPERAND(FB, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0)
+ARC_OPERAND(FC, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, insert_fs2, extract_fs2)
+ARC_OPERAND(FD, 5, 19, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0)
+
+ /* Double 128 registers, the same like above but only the odd ones
+ allowed. */
+ARC_OPERAND(FDA, 5, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0)
+ARC_OPERAND(FDB, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0)
+ARC_OPERAND(FDC, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, insert_fs2, extract_fs2)
+ARC_OPERAND(FDD, 5, 19, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0)
+
+ /* 5bit integer registers used by fp instructions. */
+ARC_OPERAND(FRD, 5, 6, 0, ARC_OPERAND_IR, 0, 0)
+ARC_OPERAND(FRB, 5, 0, 0, ARC_OPERAND_IR, insert_fs2, extract_fs2)
+
+ /* 5bit unsigned immediate used by vfext and vfins. */
+ARC_OPERAND(UIMM5_FP, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_fs2, extract_fs2)
diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h
index 2699ce8f02e..9864f16d206 100644
--- a/opcodes/arc-regs.h
+++ b/opcodes/arc-regs.h
@@ -208,7 +208,7 @@ DEF (0xad, ARC_OPCODE_ARCALL, NONE, se_watch)
DEF (0xc0, ARC_OPCODE_ARCALL, NONE, bpu_build)
DEF (0xc1, ARC_OPCODE_ARC600, NONE, arc600_build_config)
DEF (0xc1, ARC_OPCODE_ARC700, NONE, isa_config)
-DEF (0xc1, ARC_OPCODE_ARCV2, NONE, isa_config)
+DEF (0xc1, ARC_OPCODE_ARCVx, NONE, isa_config)
DEF (0xf4, ARC_OPCODE_ARCALL, NONE, hwp_build)
DEF (0xf5, ARC_OPCODE_ARCALL, NONE, pct_build)
DEF (0xf6, ARC_OPCODE_ARCALL, NONE, cc_build)
@@ -346,11 +346,17 @@ DEF (0x451, ARC_OPCODE_ARC600, NONE, wake)
DEF (0x452, ARC_OPCODE_ARC600, NONE, dvfs_performance)
DEF (0x453, ARC_OPCODE_ARC600, NONE, pwr_ctrl)
DEF (0x460, ARC_OPCODE_ARCv2HS, NONE, tlbpd0)
+DEF (0x460, ARC_OPCODE_ARC64, NONE, mmu_rtp0_lo)
DEF (0x461, ARC_OPCODE_ARCv2HS, NONE, tlbpd1)
+DEF (0x461, ARC_OPCODE_ARC64, NONE, mmu_rtp0_hi)
+DEF (0x462, ARC_OPCODE_ARC64, NONE, mmu_rtp1_lo)
+DEF (0x463, ARC_OPCODE_ARC64, NONE, mmu_rtp1_hi)
DEF (0x464, ARC_OPCODE_ARCv2HS, NONE, tlbindex)
DEF (0x465, ARC_OPCODE_ARCv2HS, NONE, tlbcommand)
DEF (0x468, ARC_OPCODE_ARCv2HS, NONE, pid)
DEF (0x46c, ARC_OPCODE_ARCv2HS, NONE, scratch_data0)
+DEF (0x468, ARC_OPCODE_ARC64, NONE, mmu_ctrl)
+DEF (0x469, ARC_OPCODE_ARC64, NONE, mmu_ttbc)
DEF (0x500, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_idx)
DEF (0x501, ARC_OPCODE_ARC700, NONE, aux_vlc_read_buf)
DEF (0x502, ARC_OPCODE_ARC700, NONE, aux_vlc_valid_bits)
diff --git a/opcodes/arc64-opc.c b/opcodes/arc64-opc.c
new file mode 100644
index 00000000000..f1e79376c44
--- /dev/null
+++ b/opcodes/arc64-opc.c
@@ -0,0 +1,834 @@
+/* Opcode table for ARC64.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#include "arcxx-opc.inc"
+
+#define F32_BR0 0x00
+#define F32_BR1 0x01
+#define F32_LD_OFFSET 0x02
+#define F32_ST_OFFSET 0x03
+#define F32_GEN4 0x04
+#define F32_EXT5 0x05
+#define F32_EXT6 0x06
+#define F32_APEX 0x07
+
+#define F16_COMPACT0 0x08
+#define F16_COMPACT1 0x08
+#define F16_MOVL 0x08
+
+#define F16_LD_ADD_SUB 0x09
+
+#define LD_ST_R01 0x0A
+#define LDI_S 0x0A
+#define JLI_S_U10 0x0A
+
+#define F16_JLI_EI 0x0B
+#define F32_GEN_OP64 0x0B
+
+/* Macros required for ARCv3 floating point instructions. */
+/* Flags. */
+#define FL_NONE { 0 }
+#define FL_CC { C_FPCC }
+
+/* Arguments. */
+#define ARG_NONE { 0 }
+#define ARG_64FP_3OP { FA, FB, FC, FD }
+#define ARG_128FP_3OP { FDA, FDB, FDC, FDD }
+#define ARG_64FP_2OP { FA, FB, FC }
+#define ARG_64FP_CMP { FB, FC }
+#define ARG_128FP_2OP { FDA, FDB, FDC }
+#define ARG_64FP_1OP { FA, FC }
+#define ARG_64FP_SOP { FA, FB }
+#define ARG_128FP_SOP { FDA, FDB }
+
+#define ARG_64FP_CVI2F { FA, FRB }
+#define ARG_64FP_CVF2I { FRD, FC }
+
+/* Macros to help generating floating point pattern instructions. */
+/* Define FP_TOP. */
+#define FIELDS1(word) (word & 0x1F)
+#define FIELDS2(word) (((word & 0x07) << 24) | (((word >> 3) & 0x03) << 12))
+#define FIELDS3(word) ((word & 0x1F) << 19)
+#define FIELDD(word) ((word & 0x1F) << 6)
+#define FIELDTOP(word) (((word & 0x01) << 5) | ((word >> 1) & 0x07) << 16)
+#define FIELDP(word) ((word & 0x03) << 14)
+#define MASK_32BIT(VAL) (0xffffffff & (VAL))
+
+#define INSNFP3OP(TOPF, P) \
+ ((0x1C << 27) | FIELDTOP (TOPF) | FIELDP (P) | (1 << 11))
+#define MINSNFP3OP \
+ (MASK_32BIT (~(FIELDS1 (31) | FIELDS2 (31) | FIELDS3 (31) | FIELDD (31))))
+
+/* Define FP_DOP. */
+#define FIELDDOP(ops) ((ops & 0x1f) << 16)
+
+#define INSNFP2OP(DOPF, P) \
+ ((0x1C << 27) | FIELDDOP (DOPF) | FIELDP (P) | (1 << 5))
+#define MINSNFP2OP \
+ (MASK_32BIT (~(FIELDS2 (31) | FIELDS1 (31) | FIELDD (31))))
+
+/* Define FP_CVF2F. */
+#define FIELDCVTF(WORD) ((WORD & 0x03) << 16)
+#define FIELDU0(BIT) (BIT & 0x01)
+#define FIELDU1(BIT) (BIT & 0x02)
+#define FIELDU3(BIT) (BIT & 0x08)
+#define FIELDU4(BIT) (BIT & 0x10)
+
+#define FP_CVF2F_MACHINE(CVTF, BIT) \
+ ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | (1 << 2) | FIELDU0 (BIT) | FIELDU3 (BIT) | FIELDU4 (BIT))
+#define MFP_CVF2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_RND. */
+#define FP_RND_MACHINE(CVTF, BIT) \
+((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) | (1 << 5) | (0x03 << 1) \
+ | FIELDU3 (BIT))
+#define MFP_RND (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_CVF2I. */
+#define FP_CVF2I_MACHINE(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) \
+ | FIELDCVTF (CVTF) | (1 << 5) | 1 \
+ | FIELDU3 (BIT) | FIELDU1 (BIT))
+#define MFP_CVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FMVVF2I. */
+#define FM_VVF2I(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | 1 << 4 | 1)
+#define MFM_VVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_SOP. */
+#define FP_SOP_MACHINE(SOPF, P) \
+ ((0x1C << 27) | (0x02 << 21) | FIELDCVTF (SOPF) | FIELDP (P) | (1 << 5))
+#define MFP_SOP_MACHINE (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31))))
+
+/* Define FP_COP. */
+#define FP_COP_MACHINE(COPF, P) \
+ ((0x1C << 27) | (0x09 << 19) | FIELDCVTF (COPF) | FIELDP (P) | (1 << 5))
+#define MFP_COP_MACHINE \
+ (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2(31))))
+
+/* Define FP_ZOP. */
+#define INSNFPZOP(COPF) \
+ ((0x1C << 27) | (0x07 << 20) | FIELDCVTF (COPF) | (1 << 5))
+
+/* Define FP_VMVI. */
+#define INSNFPVMVI(WMVF, P) \
+ ((0x1C << 27) | (0x05 << 20) | FIELDCVTF (WMVF) | FIELDP (P) | (1 << 5))
+#define MINSNFPCOP (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2 (31))))
+#define MINSNFPVMVIZ (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31))))
+
+/* Define FP_VMVR. */
+#define INSNFPVMVR(WMVF, P) \
+ ((0x1C << 27) | (0x01 << 23) | FIELDCVTF (WMVF) | FIELDP (P) | (1 << 5))
+#define MINSNFPVMVR (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2 (31))))
+
+/* Define FP_CVI2F. */
+#define INSNFPCVI2F(CVTF, BIT) ((0x1C << 27) | (0x07 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | FIELDU3 (BIT) | FIELDU1 (BIT))
+#define MINSNFPCVI2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FMVI2F. */
+#define INSNFMVI2F(CVTF, BIT) ((0x1C << 27) | (0x07 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | (1 << 4))
+#define MINSNFMVI2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FMVF2I. */
+#define INSNFMVF2I(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | (1 << 4) | (1))
+#define MINSNFMVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_LOAD. */
+#define FP_LOAD_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \
+ | ((D & 0x01) << 5))
+#define MSK_FP_LOAD (MASK_32BIT (~(FIELDB (63) | FIELDD (31) | (0x03 << 3) \
+ | (0x1FF << 15))))
+
+#define FP_LSYM_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \
+ | FIELDB(62) | ((D & 0x01) << 5))
+#define MSK_FP_SYM (MASK_32BIT (~(FIELDD (31))))
+
+/* Define FP_STORE. */
+#define FP_STORE_ENCODING(SIZE, D) ((0x0D << 27) | ((SIZE & 0x03) << 1) \
+ | ((D & 0x01) << 5) | (1))
+#define MSK_FP_STORE (MASK_32BIT (~(FIELDB (63) | FIELDD (31) | (0x03 << 3) \
+ | (0x1FF << 15))))
+#define FP_SSYM_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \
+ | FIELDB(62) | ((D & 0x01) << 5) | (1))
+
+/* FP Load/Store. */
+#define FP_LOAD(NAME, SIZE, D) \
+ { #NAME, FP_LOAD_ENCODING (SIZE, D), MSK_FP_LOAD, ARC_OPCODE_ARC64, LOAD, \
+ NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }, \
+ { #NAME, FP_LSYM_ENCODING (SIZE, D), MSK_FP_SYM, ARC_OPCODE_ARC64, LOAD, \
+ NONE, { FA, BRAKET, LIMM, BRAKETdup }, FL_NONE },
+
+#define FP_STORE(NAME, SIZE, D) \
+ { #NAME, FP_STORE_ENCODING (SIZE, D), MSK_FP_STORE, ARC_OPCODE_ARC64, STORE, \
+ NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }, \
+ { #NAME, FP_SSYM_ENCODING (SIZE, D), MSK_FP_SYM, ARC_OPCODE_ARC64, LOAD, \
+ NONE, { FA, BRAKET, LIMM, BRAKETdup }, FL_NONE },
+
+/* Macros used to generate conversion instructions. */
+#define FMVF2I_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, INSNFMVF2I (OPS, BIT), MINSNFMVF2I, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FMVF2I(NAME, OPS, BIT) \
+ FMVF2I_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVF2I)
+
+#define FMVI2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, INSNFMVI2F (OPS, BIT), MINSNFMVI2F, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FMVI2F(NAME, OPS, BIT) \
+ FMVI2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVI2F)
+
+#define FP_RND_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, FP_RND_MACHINE (OPS, BIT), MFP_RND, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_RND(NAME, OPS, BIT) \
+ FP_RND_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_1OP)
+
+#define FP_CVF2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, FP_CVF2F_MACHINE (OPS, BIT), MFP_CVF2F, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_CVF2F(NAME, OPS, BIT) \
+ FP_CVF2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_1OP)
+
+#define FP_CVF2I_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, FP_CVF2I_MACHINE (OPS, BIT), MFP_CVF2I, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_CVF2I(NAME, OPS, BIT) \
+ FP_CVF2I_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVF2I)
+
+#define FP_CVI2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, INSNFPCVI2F (OPS, BIT), MINSNFPCVI2F, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_CVI2F(NAME, OPS, BIT) \
+ FP_CVI2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVI2F)
+
+/* Macro to generate 1 operand extension instruction. */
+#define FP_SOP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, FP_SOP_MACHINE (OPS, PRC), MFP_SOP_MACHINE, CPU, CLASS, SCLASS, \
+ ARG, FL_NONE },
+
+#define FP_SOP(NAME, OPS, PRECISION) \
+ FP_SOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, SOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_SOP)
+
+#define FP_SOP_D(NAME, OPS, PRECISION) \
+ FP_SOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, SOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_128FP_SOP)
+
+/* Macro to generate 2 operand extension instruction. */
+#define FP_DOP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, INSNFP2OP (OPS, PRC), MINSNFP2OP, CPU, CLASS, SCLASS, \
+ ARG, FL_NONE },
+
+#define FP_DOP(NAME, OPS, PRECISION) \
+ FP_DOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_2OP)
+
+#define FP_DOPC_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, INSNFP2OP (OPS, PRC) | FIELDD (0), MINSNFP2OP, CPU, \
+ CLASS, SCLASS, ARG, FL_NONE },
+
+#define FP_DOP_C(NAME, OPS, PRECISION) \
+ FP_DOPC_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_CMP)
+
+#define FP_DOP_D(NAME, OPS, PRECISION) \
+ FP_DOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_128FP_2OP)
+
+/* Macro to generate 3 operand generic instruction. */
+#define FP_TOP_INSN(NAME, CPU, CLASS, SCLASS, TOPF, P, ARG) \
+ { NAME, INSNFP3OP (TOPF, P), MINSNFP3OP, CPU, CLASS, SCLASS, \
+ ARG, FL_NONE },
+
+#define FP_TOP(NAME, OPS, PRECISION) \
+ FP_TOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, TOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_3OP)
+
+#define FP_TOP_D(NAME, OPS, PRECISION) \
+ FP_TOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, TOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_128FP_3OP)
+
+/* Conditional mov instructions. */
+#define FP_COP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, FP_COP_MACHINE (OPS, PRC), MFP_COP_MACHINE, CPU, CLASS, SCLASS, \
+ ARG, FL_CC },
+
+#define FP_COP(NAME, OPS, PRECISION) \
+ FP_COP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, COPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_SOP)
+
+#define FP_EXT(NAME, PRECISION) \
+ {#NAME, INSNFPVMVI (0x00, P_ ## PRECISION), MINSNFPCOP, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, UIMM5_FP, \
+ BRAKETdup }, FL_NONE }, \
+ {#NAME, INSNFPVMVR (0x00, P_ ## PRECISION), MINSNFPVMVR, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, FRB, BRAKETdup}, \
+ FL_NONE },
+
+#define FP_INS(NAME, PRECISION) \
+ {#NAME, INSNFPVMVI (0x01, P_ ## PRECISION), MINSNFPCOP, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, UIMM5_FP, BRAKETdup, \
+ FB }, FL_NONE }, \
+ {#NAME, INSNFPVMVR (0x01, P_ ## PRECISION), MINSNFPVMVR, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, FRB, BRAKETdup, \
+ FB }, FL_NONE },
+
+#define FP_REP(NAME, PRECISION) \
+ {#NAME, INSNFPVMVI (0x02, P_ ## PRECISION) | FIELDS2 (0x00), \
+ MINSNFPVMVIZ, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, FL_NONE },
+
+
+/* Common combinations of FLAGS. */
+#define FLAGS_NONE { 0 }
+#define FLAGS_F { C_F }
+#define FLAGS_CC { C_CC }
+#define FLAGS_CCF { C_CC, C_F }
+
+/* Common combination of arguments. */
+#define ARG_NONE { 0 }
+#define ARG_32BIT_RARBRC { RA, RB, RC }
+#define ARG_32BIT_ZARBRC { ZA, RB, RC }
+#define ARG_32BIT_RBRBRC { RB, RBdup, RC }
+#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
+#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
+#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
+#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
+#define ARG_32BIT_RALIMMRC { RA, LIMM, RC }
+#define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
+#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC }
+#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
+
+#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM }
+#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 }
+#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 }
+
+#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 }
+#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup }
+#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup }
+
+#define ARG_32BIT_RBRC { RB, RC }
+#define ARG_32BIT_ZARC { ZA, RC }
+#define ARG_32BIT_RBU6 { RB, UIMM6_20 }
+#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 }
+#define ARG_32BIT_RBLIMM { RB, LIMM }
+#define ARG_32BIT_ZALIMM { ZA, LIMM }
+
+#define ARG_32BIT_RAXIMMRC { RA, XIMM, RC }
+#define ARG_32BIT_RARBXIMM { RA, RB, XIMM }
+#define ARG_32BIT_RBRBXIMM { RB, RBdup, XIMM }
+#define ARG_32BIT_RAXIMMU6 { RA, XIMM, UIMM6_20 }
+
+/* Macro to generate 2 operand extension instruction. */
+#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \
+ { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRC, FL }, \
+ { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARC, FL }, \
+ { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBU6, FL }, \
+ { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZAU6, FL }, \
+ { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBLIMM, FL }, \
+ { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMM, FL },
+
+#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
+ EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F)
+
+/* Macro to generate 3 operand extesion instruction. */
+#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
+ { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBRC, FLAGS_CCF }, \
+ { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBU6, FLAGS_CCF }, \
+ { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBS12, FLAGS_F }, \
+ { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \
+ { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \
+ { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMU6, FLAGS_F }, \
+ { NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMU6, FLAGS_F }, \
+ { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \
+ { NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMS12, FLAGS_F }, \
+ { NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMLIMM, FLAGS_CCF },
+
+
+/* Generate sign extend 32-bit immediate instructions. */
+#define INSN3OP_AXC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (60))
+#define INSN3OP_ABX(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (60))
+#define INSN3OP_CBBX(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (60))
+#define INSN3OP_AXU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (60))
+
+/* Macro to generate 3 operand 64bit instruction. */
+#define OP64INSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
+ { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBRC, FLAGS_CCF }, \
+ { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBU6, FLAGS_CCF }, \
+ { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBS12, FLAGS_F }, \
+ { NAME, INSN3OP_AXC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RAXIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_ABX (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBXIMM, FLAGS_F }, \
+ { NAME, INSN3OP_CBBX (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBXIMM, FLAGS_CCF }, \
+ { NAME, INSN3OP_AXU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RAXIMMU6, FLAGS_F }, \
+ { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \
+ { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMU6, FLAGS_F },
+
+
+#define STDL_ENCODING(K, ZZ) ((F32_ST_OFFSET << 27) | (1 << 5) | (ZZ << 1) \
+ | (K))
+#define MSK_STDL (MASK_32BIT (~(FIELDB (63) | (0x1ff << 15) | FIELDC (63) \
+ | (0x3 << 3))))
+#define STDL_ASYM_ENCODING(K, ZZ, X) ((F32_ST_OFFSET << 27) | FIELDB (X) \
+ | (1 << 5) | (ZZ << 1) | (K))
+#define STDL_DIMM_ENCODING(K, ZZ, X) ((F32_ST_OFFSET << 27) | FIELDC (X) \
+ | (1 << 5) | (ZZ << 1) | (K))
+
+/* stdl<.aa> c,[b,s9]
+ stdl<.aa> w6,[b,s9]
+ stdl<.as> c,[ximm]
+ stdl<.as> w6,[ximm]
+ stdl<.aa> ximm,[b,s9]
+ stdl<.aa> limm,[b,s9]
+*/
+#define STDL \
+ { "stdl", STDL_ENCODING (0, 0x03), MSK_STDL, ARC_OPCODE_ARC64, STORE, \
+ NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stdl", STDL_ENCODING (1, 0x02), MSK_STDL, ARC_OPCODE_ARC64, STORE, \
+ NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stdl", STDL_ASYM_ENCODING (0, 0x03, 60), 0xFF007027, ARC_OPCODE_ARC64, \
+ STORE, NONE, { RCD, BRAKET, XIMM, BRAKETdup }, {C_AS27 }}, \
+ { "stdl", STDL_ASYM_ENCODING (1, 0x02, 60), 0xFF007027, ARC_OPCODE_ARC64, \
+ STORE, NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stdl", STDL_ASYM_ENCODING (0, 0x03, 62), 0xFF007027, ARC_OPCODE_ARC64, \
+ STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, {C_AS27 }}, \
+ { "stdl", STDL_ASYM_ENCODING (1, 0x02, 62), 0xFF007027, ARC_OPCODE_ARC64, \
+ STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stdl", STDL_DIMM_ENCODING (0, 0x03, 60), 0XF8000FE7, ARC_OPCODE_ARC64, \
+ STORE, NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stdl", STDL_DIMM_ENCODING (0, 0x03, 62), 0xF8000FE7, ARC_OPCODE_ARC64, \
+ STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }},
+
+#define STL_ENCODING(DI) ((F32_ST_OFFSET << 27) | (DI << 5) | (0X03 << 1) \
+ | (1))
+#define MSK_STL (MASK_32BIT (~(FIELDB (63) | (0x1ff << 15) | FIELDC (63) \
+ | (0x03 << 3))))
+#define STL_ASYM_ENCODING(DI, X) ((F32_ST_OFFSET << 27) | (DI << 5) \
+ | (0X03 << 1) | FIELDB (X) | (1))
+#define STL_DSYM_ENCODING(X) ((F32_ST_OFFSET << 27) | (0X03 << 1) \
+ | FIELDC (X) | (1))
+
+/* stl<.aa> c,[b,s9]
+ stl<.aa> w6,[b,s9]
+ stl<.as> c,[ximm]
+ stl<.as> w6,[ximm]
+ stl<.aa> ximm,[b,s9]
+ stl<.aa> limm,[b,s9]
+*/
+#define STL \
+ { "stl", STL_ENCODING (0), MSK_STL, ARC_OPCODE_ARC64, STORE, NONE, \
+ { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stl", STL_ENCODING (1), MSK_STL, ARC_OPCODE_ARC64, STORE, NONE, \
+ { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stl", STL_ASYM_ENCODING (0, 60), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \
+ NONE, { RC, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stl", STL_ASYM_ENCODING (1, 60), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \
+ NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stl", STL_ASYM_ENCODING (0, 62), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \
+ NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stl", STL_ASYM_ENCODING (1, 62), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \
+ NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stl", STL_DSYM_ENCODING (60), 0xF8000FC7, ARC_OPCODE_ARC64, STORE, \
+ NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stl", STL_DSYM_ENCODING (62), 0xF8000FC7, ARC_OPCODE_ARC64, STORE, \
+ NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }},
+
+/* The opcode table.
+
+ The format of the opcode table is:
+
+ NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
+
+ The table is organised such that, where possible, all instructions with
+ the same mnemonic are together in a block. When the assembler searches
+ for a suitable instruction the entries are checked in table order, so
+ more specific, or specialised cases should appear earlier in the table.
+
+ As an example, consider two instructions 'add a,b,u6' and 'add
+ a,b,limm'. The first takes a 6-bit immediate that is encoded within the
+ 32-bit instruction, while the second takes a 32-bit immediate that is
+ encoded in a follow-on 32-bit, making the total instruction length
+ 64-bits. In this case the u6 variant must appear first in the table, as
+ all u6 immediates could also be encoded using the 'limm' extension,
+ however, we want to use the shorter instruction wherever possible.
+
+ It is possible though to split instructions with the same mnemonic into
+ multiple groups. However, the instructions are still checked in table
+ order, even across groups. The only time that instructions with the
+ same mnemonic should be split into different groups is when different
+ variants of the instruction appear in different architectures, in which
+ case, grouping all instructions from a particular architecture together
+ might be preferable to merging the instruction into the main instruction
+ table.
+
+ An example of this split instruction groups can be found with the 'sync'
+ instruction. The core arc architecture provides a 'sync' instruction,
+ while the nps instruction set extension provides 'sync.rd' and
+ 'sync.wr'. The rd/wr flags are instruction flags, not part of the
+ mnemonic, so we end up with two groups for the sync instruction, the
+ first within the core arc instruction table, and the second within the
+ nps extension instructions. */
+
+const struct arc_opcode arc_opcodes[] =
+{
+
+ /* STL and STDL instructions. */
+ STL
+ STDL
+
+#include "arc64-tbl.h"
+
+ FP_TOP (fhmadd , FMADD , HALF)
+ FP_TOP (fhmsub , FMSUB , HALF)
+ FP_TOP (fhnmadd, FNMADD, HALF)
+ FP_TOP (fhnmsub, FNMSUB, HALF)
+
+ FP_TOP (fsmadd , FMADD , SINGLE)
+ FP_TOP (fsmsub , FMSUB , SINGLE)
+ FP_TOP (fsnmadd, FNMADD, SINGLE)
+ FP_TOP (fsnmsub, FNMSUB, SINGLE)
+
+ FP_TOP (fdmadd , FMADD , DOUBLE)
+ FP_TOP (fdmsub , FMSUB , DOUBLE)
+ FP_TOP (fdnmadd, FNMADD, DOUBLE)
+ FP_TOP (fdnmsub, FNMSUB, DOUBLE)
+
+ /* Vectors. */
+ FP_TOP (vfhmadd , VFMADD , HALF)
+ FP_TOP (vfhmsub , VFMSUB , HALF)
+ FP_TOP (vfhnmadd, VFNMADD, HALF)
+ FP_TOP (vfhnmsub, VFNMSUB, HALF)
+ FP_TOP (vfhmadds , VFMADDS , HALF)
+ FP_TOP (vfhmsubs , VFMSUBS , HALF)
+ FP_TOP (vfhnmadds, VFNMADDS, HALF)
+ FP_TOP (vfhnmsubs, VFNMSUBS, HALF)
+
+ FP_TOP (vfsmadd , VFMADD , SINGLE)
+ FP_TOP (vfsmsub , VFMSUB , SINGLE)
+ FP_TOP (vfsnmadd, VFNMADD, SINGLE)
+ FP_TOP (vfsnmsub, VFNMSUB, SINGLE)
+ FP_TOP (vfsmadds , VFMADDS , SINGLE)
+ FP_TOP (vfsmsubs , VFMSUBS , SINGLE)
+ FP_TOP (vfsnmadds, VFNMADDS, SINGLE)
+ FP_TOP (vfsnmsubs, VFNMSUBS, SINGLE)
+
+ FP_TOP_D (vfdmadd , VFMADD , DOUBLE)
+ FP_TOP_D (vfdmsub , VFMSUB , DOUBLE)
+ FP_TOP_D (vfdnmadd, VFNMADD, DOUBLE)
+ FP_TOP_D (vfdnmsub, VFNMSUB, DOUBLE)
+ FP_TOP_D (vfdmadds , VFMADDS , DOUBLE)
+ FP_TOP_D (vfdmsubs , VFMSUBS , DOUBLE)
+ FP_TOP_D (vfdnmadds, VFNMADDS, DOUBLE)
+ FP_TOP_D (vfdnmsubs, VFNMSUBS, DOUBLE)
+
+ /* 2OPS. */
+ FP_DOP (fhadd , FADD , HALF)
+ FP_DOP (fhsub , FSUB , HALF)
+ FP_DOP (fhmul , FMUL , HALF)
+ FP_DOP (fhdiv , FDIV , HALF)
+ FP_DOP (fhmin , FMIN , HALF)
+ FP_DOP (fhmax , FMAX , HALF)
+ FP_DOP (fhsgnj , FSGNJ , HALF)
+ FP_DOP (fhsgnjn, FSGNJN, HALF)
+ FP_DOP (fhsgnjx, FSGNJX, HALF)
+
+ FP_DOP (fsadd , FADD , SINGLE)
+ FP_DOP (fssub , FSUB , SINGLE)
+ FP_DOP (fsmul , FMUL , SINGLE)
+ FP_DOP (fsdiv , FDIV , SINGLE)
+ FP_DOP (fsmin , FMIN , SINGLE)
+ FP_DOP (fsmax , FMAX , SINGLE)
+ FP_DOP (fssgnj , FSGNJ , SINGLE)
+ FP_DOP (fssgnjn, FSGNJN, SINGLE)
+ FP_DOP (fssgnjx, FSGNJX, SINGLE)
+
+ FP_DOP (fdadd , FADD , DOUBLE)
+ FP_DOP (fdsub , FSUB , DOUBLE)
+ FP_DOP (fdmul , FMUL , DOUBLE)
+ FP_DOP (fddiv , FDIV , DOUBLE)
+ FP_DOP (fdmin , FMIN , DOUBLE)
+ FP_DOP (fdmax , FMAX , DOUBLE)
+ FP_DOP (fdsgnj , FSGNJ , DOUBLE)
+ FP_DOP (fdsgnjn, FSGNJN, DOUBLE)
+ FP_DOP (fdsgnjx, FSGNJX, DOUBLE)
+
+ FP_DOP_C (fhcmp , FCMP , HALF)
+ FP_DOP_C (fhcmpf, FCMPF, HALF)
+ FP_DOP_C (fscmp , FCMP , SINGLE)
+ FP_DOP_C (fscmpf, FCMPF, SINGLE)
+ FP_DOP_C (fdcmp , FCMP , DOUBLE)
+ FP_DOP_C (fdcmpf, FCMPF, DOUBLE)
+
+ /* Vectors. */
+ FP_DOP (vfhadd , VFADD , HALF)
+ FP_DOP (vfhsub , VFSUB , HALF)
+ FP_DOP (vfhmul , VFMUL , HALF)
+ FP_DOP (vfhdiv , VFDIV , HALF)
+ FP_DOP (vfhadds, VFADDS, HALF)
+ FP_DOP (vfhsubs, VFSUBS, HALF)
+ FP_DOP (vfhmuls, VFMULS, HALF)
+ FP_DOP (vfhdivs, VFDIVS, HALF)
+
+ FP_DOP (vfhunpkl , VFUNPKL , HALF)
+ FP_DOP (vfhunpkm , VFUNPKM , HALF)
+ FP_DOP (vfhpackl , VFPACKL , HALF)
+ FP_DOP (vfhpackm , VFPACKM , HALF)
+ FP_DOP (vfhbflyl , VFBFLYL , HALF)
+ FP_DOP (vfhbflym , VFBFLYM , HALF)
+ FP_DOP (vfhaddsub, VFADDSUB, HALF)
+ FP_DOP (vfhsubadd, VFSUBADD, HALF)
+
+ FP_DOP (vfsadd , VFADD , SINGLE)
+ FP_DOP (vfssub , VFSUB , SINGLE)
+ FP_DOP (vfsmul , VFMUL , SINGLE)
+ FP_DOP (vfsdiv , VFDIV , SINGLE)
+ FP_DOP (vfsadds, VFADDS, SINGLE)
+ FP_DOP (vfssubs, VFSUBS, SINGLE)
+ FP_DOP (vfsmuls, VFMULS, SINGLE)
+ FP_DOP (vfsdivs, VFDIVS, SINGLE)
+
+ FP_DOP (vfsunpkl , VFUNPKL , SINGLE)
+ FP_DOP (vfsunpkm , VFUNPKM , SINGLE)
+ FP_DOP (vfspackl , VFPACKL , SINGLE)
+ FP_DOP (vfspackm , VFPACKM , SINGLE)
+ FP_DOP (vfsbflyl , VFBFLYL , SINGLE)
+ FP_DOP (vfsbflym , VFBFLYM , SINGLE)
+ FP_DOP (vfsaddsub, VFADDSUB, SINGLE)
+ FP_DOP (vfssubadd, VFSUBADD, SINGLE)
+
+ FP_DOP_D (vfdadd , VFADD , DOUBLE)
+ FP_DOP_D (vfdsub , VFSUB , DOUBLE)
+ FP_DOP_D (vfdmul , VFMUL , DOUBLE)
+ FP_DOP_D (vfddiv , VFDIV , DOUBLE)
+ FP_DOP_D (vfdadds, VFADDS, DOUBLE)
+ FP_DOP_D (vfdsubs, VFSUBS, DOUBLE)
+ FP_DOP_D (vfdmuls, VFMULS, DOUBLE)
+ FP_DOP_D (vfddivs, VFDIVS, DOUBLE)
+
+ FP_DOP_D (vfdunpkl , VFUNPKL , DOUBLE)
+ FP_DOP_D (vfdunpkm , VFUNPKM , DOUBLE)
+ FP_DOP_D (vfdpackl , VFPACKL , DOUBLE)
+ FP_DOP_D (vfdpackm , VFPACKM , DOUBLE)
+ FP_DOP_D (vfdbflyl , VFBFLYL , DOUBLE)
+ FP_DOP_D (vfdbflym , VFBFLYM , DOUBLE)
+ FP_DOP_D (vfdaddsub, VFADDSUB, DOUBLE)
+ FP_DOP_D (vfdsubadd, VFSUBADD, DOUBLE)
+
+ FP_SOP (fhsqrt, FSQRT, HALF)
+ FP_SOP (fssqrt, FSQRT, SINGLE)
+ FP_SOP (fdsqrt, FSQRT, DOUBLE)
+ FP_SOP (vfhsqrt, VFSQRT, HALF)
+ FP_SOP (vfssqrt, VFSQRT, SINGLE)
+ FP_SOP_D (vfdsqrt, VFSQRT,DOUBLE)
+
+ FP_SOP (vfhexch, VFEXCH, HALF)
+ FP_SOP (vfsexch, VFEXCH, SINGLE)
+ FP_SOP_D (vfdexch, VFEXCH, DOUBLE)
+
+ FP_COP (fhmov, FMOV, HALF)
+ FP_COP (fsmov, FMOV, SINGLE)
+ FP_COP (fdmov, FMOV, DOUBLE)
+ FP_COP (vfhmov, VFMOV, HALF)
+ FP_COP (vfsmov, VFMOV, SINGLE)
+ FP_COP (vfdmov, VFMOV, DOUBLE)
+
+ FP_CVI2F (fuint2s, FUINT2S, 0x00)
+ FP_CVI2F (fuint2d, FUINT2D, 0x00)
+ FP_CVI2F (ful2s, FUL2S, 0x00)
+ FP_CVI2F (ful2d, FUL2D, 0x00)
+
+ FP_CVF2I (fs2uint, FS2UINT, 0x01)
+ FP_CVF2I (fs2ul, FS2UL, 0x01)
+ FP_CVF2I (fd2uint, FD2UINT, 0x01)
+ FP_CVF2I (fd2ul, FD2UL, 0x01)
+
+ FP_CVI2F (fint2s, FINT2S, 0x02)
+ FP_CVI2F (fint2d, FINT2D, 0x02)
+ FP_CVI2F (fl2s, FL2S, 0x02)
+ FP_CVI2F (fl2d, FL2D, 0x02)
+
+ FP_CVF2I (fs2int, FS2INT, 0x03)
+ FP_CVF2I (fs2l, FS2L, 0x03)
+ FP_CVF2I (fd2int, FD2INT, 0x03)
+ FP_CVF2I (fd2l, FD2L, 0x03)
+
+ FP_CVF2F (fs2d, FS2D, 0x04)
+ FP_CVF2F (fd2s, FD2S, 0x04)
+
+ FP_RND (fsrnd, FSRND, 0x06)
+ FP_RND (fdrnd, FDRND, 0x06)
+
+ FP_CVF2I (fs2uint_rz, F2UINT_RZ, 0x09)
+ FP_CVF2I (fs2ul_rz, FS2UL_RZ, 0x09)
+ FP_CVF2I (fd2uint_rz, FD2UINT_RZ, 0x09)
+ FP_CVF2I (fd2ul_rz, FD2UL_RZ, 0x09)
+
+ FP_CVF2I (fs2int_rz, FSINT_RZ, 0x0B)
+ FP_CVF2I (fs2l_rz, FS2L_RZ, 0x0B)
+ FP_CVF2I (fd2int_rz, FD2INT_RZ, 0x0B)
+ FP_CVF2I (fd2l_rz, FD2L_RZ, 0x0B)
+
+ FP_RND (fsrnd_rz, FSRND_RZ, 0x0E)
+ FP_RND (fdrnd_rz, FDRND_RZ, 0x0E)
+
+ FMVI2F (fmvi2s, FMVI2S, 0x10)
+ FMVI2F (fmvl2d, FMVL2D, 0x10)
+
+ FMVF2I (fmvs2i, FMVS2I, 0x11)
+ FMVF2I (fmvd2l, FMVD2L, 0x11)
+
+ FP_CVF2F (fs2h, FS2H, 0x14)
+ FP_CVF2F (fh2s, FH2S, 0x15)
+ FP_CVF2F (fs2h_rz, FS2H_RZ, 0x1C)
+
+ FP_LOAD (fld16, 0x02, 0)
+ FP_LOAD (fld32, 0x00, 0)
+ FP_LOAD (fld64, 0x01, 0)
+ FP_LOAD (fldd32, 0x00, 1)
+ FP_LOAD (fldd64, 0x01, 1)
+
+ FP_STORE (fst16, 0x02, 0)
+ FP_STORE (fst32, 0x00, 0)
+ FP_STORE (fst64, 0x01, 0)
+ FP_STORE (fstd32, 0x00, 1)
+ FP_STORE (fstd64, 0x01, 1)
+
+ FP_EXT (vfhext, HALF)
+ FP_EXT (vfsext, SINGLE)
+ FP_EXT (vfdext, DOUBLE)
+
+ FP_INS (vfhins, HALF)
+ FP_INS (vfsins, SINGLE)
+ FP_INS (vfdins, DOUBLE)
+
+ FP_REP (vfhrep, HALF)
+ FP_REP (vfsrep, SINGLE)
+ FP_REP (vfdrep, DOUBLE)
+
+#undef FLAGS_F
+#define FLAGS_F { 0 }
+
+#undef FLAGS_CCF
+#define FLAGS_CCF { C_CC }
+
+#undef FIELDF
+#define FIELDF 0x0
+
+ EXTINSN3OP ("vmin2", ARC_OPCODE_ARC32, MOVE, NONE, F32_GEN4, 0x11)
+ EXTINSN3OP ("vmax2", ARC_OPCODE_ARC32, MOVE, NONE, F32_GEN4, 0x0b)
+
+#undef HARD_FIELDF
+#define HARD_FIELDF (0x01 << 15)
+
+ EXTINSN3OP ("vmin2", ARC_OPCODE_ARC64, MOVE, NONE, F32_EXT5, 0x38)
+ EXTINSN3OP ("vmax2", ARC_OPCODE_ARC64, MOVE, NONE, F32_EXT5, 0x39)
+
+ EXTINSN3OP ("vpack4hl", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x30)
+ EXTINSN3OP ("vpack4hm", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x31)
+ EXTINSN3OP ("vpack2wl", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x32)
+ EXTINSN3OP ("vpack2wm", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x33)
+ EXTINSN3OP ("vpack2hm", ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE,
+ F32_EXT5, 0x29)
+
+#undef HARD_FIELDF
+#define HARD_FIELDF (0x0)
+
+ OP64INSN3OP ("mpyl", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x30)
+ OP64INSN3OP ("mpyml", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x31)
+ OP64INSN3OP ("mpymul", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x32)
+ OP64INSN3OP ("mpymsul", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x33)
+
+ EXTINSN3OP ("vpack2hl", ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE,
+ F32_EXT5, 0x29)
+
+ { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
+};
diff --git a/opcodes/arcxx-opc.inc b/opcodes/arcxx-opc.inc
new file mode 100644
index 00000000000..7c72e5f9019
--- /dev/null
+++ b/opcodes/arcxx-opc.inc
@@ -0,0 +1,1840 @@
+/* Opcode table for the ARC.
+ Copyright (C) 1994-2023 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "bfd.h"
+#include "opcode/arc.h"
+#include "opintl.h"
+#include "libiberty.h"
+
+/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some
+ custom instructions. All NPS400 features are built into all ARC
+ target builds as this reduces the chances that regressions might
+ creep in. */
+
+/* Insert RA register into a 32-bit opcode, with checks. */
+
+static unsigned long long
+insert_ra_chk (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | (value & 0x3F);
+}
+
+/* Insert RB register into a 32-bit opcode. */
+
+static unsigned long long
+insert_rb (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
+
+/* Insert RB register into a push(d)l/pop(d)l instruction. */
+
+static unsigned long long
+insert_rbb (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x07) << 8) | (((value >> 3) & 0x07) << 1);
+}
+
+/* Insert RB register with checks. */
+
+static unsigned long long
+insert_rb_chk (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
+
+/* Insert a floating point register into fs2 slot. */
+
+static unsigned long long
+insert_fs2 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x03) << 12);
+}
+
+/* Insert address writeback mode for 128-bit loads. */
+
+static unsigned long long
+insert_qq (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x01) << 11) | ((value & 0x02) << (6-1));
+}
+
+static long long
+extract_rb (unsigned long long insn,
+ bool *invalid)
+{
+ int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
+
+ if (value == 0x3e && invalid)
+ *invalid = true; /* A limm operand, it should be extracted in a
+ different way. */
+
+ return value;
+}
+
+static long long
+extract_rbb (unsigned long long insn,
+ bool *invalid)
+{
+ int value = (((insn >> 1) & 0x07) << 3) | ((insn >> 8) & 0x07);
+
+ if (value == 0x3e && invalid)
+ *invalid = true; /* A limm operand, it should be extracted in a
+ different way. */
+
+ return value;
+}
+
+/* Extract the floating point register number from fs2 slot. */
+
+static long long
+extract_fs2 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ long long value;
+ value = (((insn >> 12) & 0x03) << 3) | ((insn >> 24) & 0x07);
+ return value;
+}
+
+/* Extract address writeback mode for 128-bit loads. */
+
+static long long
+extract_qq (unsigned long long insn,
+ bool * invalid ATTRIBUTE_UNUSED)
+{
+ long long value;
+ value = ((insn & 0x800) >> 11) | ((insn & 0x40) >> (6 - 1));
+ return value;
+}
+
+static unsigned long long
+insert_rad (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value & 0x01)
+ *errmsg = _("cannot use odd number destination register");
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | (value & 0x3F);
+}
+
+static unsigned long long
+insert_rcd (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value & 0x01)
+ *errmsg = _("cannot use odd number source register");
+
+ return insn | ((value & 0x3F) << 6);
+}
+
+static unsigned long long
+insert_rbd (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value & 0x01)
+ *errmsg = _("cannot use odd number source register");
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
+
+/* Dummy insert ZERO operand function. */
+
+static unsigned long long
+insert_za (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value)
+ *errmsg = _("operand is not zero");
+ return insn;
+}
+
+/* Insert Y-bit in bbit/br instructions. This function is called only
+ when solving fixups. */
+
+static unsigned long long
+insert_Ybit (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value > 0)
+ insn |= 0x08;
+
+ return insn;
+}
+
+/* Insert Y-bit in bbit/br instructions. This function is called only
+ when solving fixups. */
+
+static unsigned long long
+insert_NYbit (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value < 0)
+ insn |= 0x08;
+
+ return insn;
+}
+
+/* Insert H register into a 16-bit opcode. */
+
+static unsigned long long
+insert_rhv1 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
+}
+
+static long long
+extract_rhv1 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
+
+ return value;
+}
+
+/* Insert H register into a 16-bit opcode. */
+
+static unsigned long long
+insert_rhv2 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value == 0x1E)
+ *errmsg = _("register R30 is a limm indicator");
+ else if (value < 0 || value > 31)
+ *errmsg = _("register out of range");
+ return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
+}
+
+static long long
+extract_rhv2 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
+
+ return value;
+}
+
+static unsigned long long
+insert_r0 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 0)
+ *errmsg = _("register must be R0");
+ return insn;
+}
+
+static long long
+extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+
+static unsigned long long
+insert_r1 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 1)
+ *errmsg = _("register must be R1");
+ return insn;
+}
+
+static long long
+extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool* invalid ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+static unsigned long long
+insert_r2 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 2)
+ *errmsg = _("register must be R2");
+ return insn;
+}
+
+static long long
+extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 2;
+}
+
+static unsigned long long
+insert_r3 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 3)
+ *errmsg = _("register must be R3");
+ return insn;
+}
+
+static long long
+extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 3;
+}
+
+static unsigned long long
+insert_sp (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 28)
+ *errmsg = _("register must be SP");
+ return insn;
+}
+
+static long long
+extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 28;
+}
+
+static unsigned long long
+insert_gp (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 26
+ && value != 30)
+ *errmsg = _("register must be GP");
+ return insn;
+}
+
+static long long
+extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 26;
+}
+
+static unsigned long long
+insert_pcl (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 63)
+ *errmsg = _("register must be PCL");
+ return insn;
+}
+
+static long long
+extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 63;
+}
+
+static unsigned long long
+insert_blink (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 31)
+ *errmsg = _("register must be BLINK");
+ return insn;
+}
+
+static long long
+extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 31;
+}
+
+static unsigned long long
+insert_ilink1 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 29)
+ *errmsg = _("register must be ILINK1");
+ return insn;
+}
+
+static long long
+extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 29;
+}
+
+static unsigned long long
+insert_ilink2 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 30)
+ *errmsg = _("register must be ILINK2");
+ return insn;
+}
+
+static long long
+extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 30;
+}
+
+static unsigned long long
+insert_ras (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8);
+ break;
+ default:
+ *errmsg = _("register must be either r0-r3 or r12-r15");
+ break;
+ }
+ return insn;
+}
+
+static long long
+extract_ras (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = insn & 0x07;
+
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned long long
+insert_rbs (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 8;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= ((value - 8)) << 8;
+ break;
+ default:
+ *errmsg = _("register must be either r0-r3 or r12-r15");
+ break;
+ }
+ return insn;
+}
+
+static long long
+extract_rbs (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 8) & 0x07;
+
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned long long
+insert_rcs (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 5;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= ((value - 8)) << 5;
+ break;
+ default:
+ *errmsg = _("register must be either r0-r3 or r12-r15");
+ break;
+ }
+ return insn;
+}
+
+static long long
+extract_rcs (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 5) & 0x07;
+
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned long long
+insert_simm3s (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ int tmp = 0;
+ switch (value)
+ {
+ case -1:
+ tmp = 0x07;
+ break;
+ case 0:
+ tmp = 0x00;
+ break;
+ case 1:
+ tmp = 0x01;
+ break;
+ case 2:
+ tmp = 0x02;
+ break;
+ case 3:
+ tmp = 0x03;
+ break;
+ case 4:
+ tmp = 0x04;
+ break;
+ case 5:
+ tmp = 0x05;
+ break;
+ case 6:
+ tmp = 0x06;
+ break;
+ default:
+ *errmsg = _("accepted values are from -1 to 6");
+ break;
+ }
+
+ insn |= tmp << 8;
+ return insn;
+}
+
+static long long
+extract_simm3s (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 8) & 0x07;
+
+ if (value == 7)
+ return -1;
+ else
+ return value;
+}
+
+static unsigned long long
+insert_rrange (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ int reg1 = (value >> 16) & 0xFFFF;
+ int reg2 = value & 0xFFFF;
+
+ if (reg1 != 13)
+ *errmsg = _("first register of the range should be r13");
+ else if (reg2 < 13 || reg2 > 26)
+ *errmsg = _("last register of the range doesn't fit");
+ else
+ insn |= ((reg2 - 12) & 0x0F) << 1;
+ return insn;
+}
+
+static long long
+extract_rrange (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn >> 1) & 0x0F;
+}
+
+static unsigned long long
+insert_r13el (unsigned long long insn,
+ long long int value,
+ const char **errmsg)
+{
+ if (value != 13)
+ {
+ *errmsg = _("invalid register number, should be fp");
+ return insn;
+ }
+
+ insn |= 0x02;
+ return insn;
+}
+
+static unsigned long long
+insert_fpel (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 27)
+ {
+ *errmsg = _("invalid register number, should be fp");
+ return insn;
+ }
+
+ insn |= 0x0100;
+ return insn;
+}
+
+static long long
+extract_fpel (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn & 0x0100) ? 27 : -1;
+}
+
+static unsigned long long
+insert_blinkel (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 31)
+ {
+ *errmsg = _("invalid register number, should be blink");
+ return insn;
+ }
+
+ insn |= 0x0200;
+ return insn;
+}
+
+static long long
+extract_blinkel (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn & 0x0200) ? 31 : -1;
+}
+
+static unsigned long long
+insert_pclel (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 63)
+ {
+ *errmsg = _("invalid register number, should be pcl");
+ return insn;
+ }
+
+ insn |= 0x0400;
+ return insn;
+}
+
+static long long
+extract_pclel (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn & 0x0400) ? 63 : -1;
+}
+
+#define INSERT_W6
+
+/* mask = 00000000000000000000111111000000
+ insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
+
+static unsigned long long
+insert_w6 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value >> 0) & 0x003f) << 6;
+
+ return insn;
+}
+
+#define EXTRACT_W6
+
+/* mask = 00000000000000000000111111000000. */
+
+static long long
+extract_w6 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = 0;
+
+ value |= ((insn >> 6) & 0x003f) << 0;
+
+ /* Extend the sign. */
+ int signbit = 1 << 5;
+ value = (value ^ signbit) - signbit;
+
+ return value;
+}
+
+#define INSERT_G_S
+
+/* mask = 0000011100022000
+ insn = 01000ggghhhGG0HH. */
+
+static unsigned long long
+insert_g_s (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value >> 0) & 0x0007) << 8;
+ insn |= ((value >> 3) & 0x0003) << 3;
+
+ return insn;
+}
+
+#define EXTRACT_G_S
+
+/* mask = 0000011100022000. */
+
+static long long
+extract_g_s (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = 0;
+ int signbit = 1 << (6 - 1);
+
+ value |= ((insn >> 8) & 0x0007) << 0;
+ value |= ((insn >> 3) & 0x0003) << 3;
+
+ /* Extend the sign. */
+ value = (value ^ signbit) - signbit;
+
+ return value;
+}
+
+/* ARC NPS400 Support: See comment near head of file. */
+#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
+static unsigned long long \
+ insert_nps_3bit_reg_at_##OFFSET##_##NAME \
+ (unsigned long long insn, \
+ long long value, \
+ const char **errmsg) \
+{ \
+ switch (value) \
+ { \
+ case 0: \
+ case 1: \
+ case 2: \
+ case 3: \
+ insn |= value << (OFFSET); \
+ break; \
+ case 12: \
+ case 13: \
+ case 14: \
+ case 15: \
+ insn |= (value - 8) << (OFFSET); \
+ break; \
+ default: \
+ *errmsg = _("register must be either r0-r3 or r12-r15"); \
+ break; \
+ } \
+ return insn; \
+} \
+ \
+static long long \
+extract_nps_3bit_reg_at_##OFFSET##_##NAME \
+ (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
+{ \
+ int value = (insn >> (OFFSET)) & 0x07; \
+ if (value > 3) \
+ value += 8; \
+ return value; \
+} \
+
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,8)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,24)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,40)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,56)
+
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,5)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,21)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,37)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,53)
+
+static unsigned long long
+insert_nps_bitop_size_2b (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 1:
+ value = 0;
+ break;
+ case 2:
+ value = 1;
+ break;
+ case 4:
+ value = 2;
+ break;
+ case 8:
+ value = 3;
+ break;
+ default:
+ value = 0;
+ *errmsg = _("invalid size, should be 1, 2, 4, or 8");
+ break;
+ }
+
+ insn |= value << 10;
+ return insn;
+}
+
+static long long
+extract_nps_bitop_size_2b (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 1 << ((insn >> 10) & 0x3);
+}
+
+static unsigned long long
+insert_nps_bitop_uimm8 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value >> 5) & 7) << 12;
+ insn |= (value & 0x1f);
+ return insn;
+}
+
+static long long
+extract_nps_bitop_uimm8 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
+}
+
+static unsigned long long
+insert_nps_rflt_uimm6 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 1:
+ case 2:
+ case 4:
+ break;
+
+ default:
+ *errmsg = _("invalid immediate, must be 1, 2, or 4");
+ value = 0;
+ }
+
+ insn |= (value << 6);
+ return insn;
+}
+
+static long long
+extract_nps_rflt_uimm6 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn >> 6) & 0x3f;
+}
+
+static unsigned long long
+insert_nps_dst_pos_and_size (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
+ return insn;
+}
+
+static long long
+extract_nps_dst_pos_and_size (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn & 0x1f);
+}
+
+static unsigned long long
+insert_nps_cmem_uimm16 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ int top = (value >> 16) & 0xffff;
+
+ if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
+ *errmsg = _("invalid value for CMEM ld/st immediate");
+ insn |= (value & 0xffff);
+ return insn;
+}
+
+static long long
+extract_nps_cmem_uimm16 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
+}
+
+static unsigned long long
+insert_nps_imm_offset (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 0:
+ case 16:
+ case 32:
+ case 48:
+ case 64:
+ value = value >> 4;
+ break;
+ default:
+ *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64.");
+ value = 0;
+ }
+ insn |= (value << 10);
+ return insn;
+}
+
+static long long
+extract_nps_imm_offset (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 10) & 0x7) * 16;
+}
+
+static unsigned long long
+insert_nps_imm_entry (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 16:
+ value = 0;
+ break;
+ case 32:
+ value = 1;
+ break;
+ case 64:
+ value = 2;
+ break;
+ case 128:
+ value = 3;
+ break;
+ default:
+ *errmsg = _("invalid position, should be 16, 32, 64 or 128.");
+ value = 0;
+ }
+ insn |= (value << 2);
+ return insn;
+}
+
+static long long
+extract_nps_imm_entry (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int imm_entry = ((insn >> 2) & 0x7);
+ return (1 << (imm_entry + 4));
+}
+
+static unsigned long long
+insert_nps_size_16bit (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if ((value < 1) || (value > 64))
+ {
+ *errmsg = _("invalid size value must be on range 1-64.");
+ value = 0;
+ }
+ value = value & 0x3f;
+ insn |= (value << 6);
+ return insn;
+}
+
+static long long
+extract_nps_size_16bit (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64;
+}
+
+
+#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
+ static unsigned long long \
+ insert_nps_##NAME##_pos (unsigned long long insn, \
+ long long value, \
+ const char **errmsg) \
+{ \
+ switch (value) \
+ { \
+ case 0: \
+ case 8: \
+ case 16: \
+ case 24: \
+ value = value / 8; \
+ break; \
+ default: \
+ *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \
+ value = 0; \
+ } \
+ insn |= (value << SHIFT); \
+ return insn; \
+} \
+ \
+ static long long \
+ extract_nps_##NAME##_pos (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
+ { \
+ return ((insn >> SHIFT) & 0x3) * 8; \
+ }
+
+MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
+MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
+
+#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \
+static unsigned long long \
+insert_nps_##NAME (unsigned long long insn, \
+ long long value, \
+ const char **errmsg) \
+{ \
+ if (value < LOWER || value > UPPER) \
+ { \
+ *errmsg = _("invalid size, value must be " \
+ #LOWER " to " #UPPER "."); \
+ return insn; \
+ } \
+ value -= BIAS; \
+ insn |= (value << SHIFT); \
+ return insn; \
+} \
+ \
+static long long \
+extract_nps_##NAME (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
+{ \
+ return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
+}
+
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
+
+static long long
+extract_nps_qcmp_m3 (unsigned long long insn,
+ bool *invalid)
+{
+ int m3 = (insn >> 5) & 0xf;
+ if (m3 == 0xf)
+ *invalid = true;
+ return m3;
+}
+
+static long long
+extract_nps_qcmp_m2 (unsigned long long insn,
+ bool *invalid)
+{
+ bool tmp_invalid = false;
+ int m2 = (insn >> 15) & 0x1;
+ int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
+
+ if (m2 == 0 && m3 == 0xf)
+ *invalid = true;
+ return m2;
+}
+
+static long long
+extract_nps_qcmp_m1 (unsigned long long insn,
+ bool *invalid)
+{
+ bool tmp_invalid = false;
+ int m1 = (insn >> 14) & 0x1;
+ int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
+ int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
+
+ if (m1 == 0 && m2 == 0 && m3 == 0xf)
+ *invalid = true;
+ return m1;
+}
+
+static unsigned long long
+insert_nps_calc_entry_size (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ unsigned pwr;
+
+ if (value < 1 || value > 256)
+ {
+ *errmsg = _("value out of range 1 - 256");
+ return 0;
+ }
+
+ for (pwr = 0; (value & 1) == 0; value >>= 1)
+ ++pwr;
+
+ if (value != 1)
+ {
+ *errmsg = _("value must be power of 2");
+ return 0;
+ }
+
+ return insn | (pwr << 8);
+}
+
+static long long
+extract_nps_calc_entry_size (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ unsigned entry_size = (insn >> 8) & 0xf;
+ return 1 << entry_size;
+}
+
+static unsigned long long
+insert_nps_bitop_mod4 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
+}
+
+static long long
+extract_nps_bitop_mod4 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
+}
+
+static unsigned long long
+insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | (value << 42) | (value << 37);
+}
+
+static long long
+extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
+ bool *invalid)
+{
+ if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
+ *invalid = true;
+ return ((insn >> 37) & 0x1f);
+}
+
+static unsigned long long
+insert_nps_bitop_ins_ext (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value < 0 || value > 28)
+ *errmsg = _("value must be in the range 0 to 28");
+ return insn | (value << 20);
+}
+
+static long long
+extract_nps_bitop_ins_ext (unsigned long long insn,
+ bool *invalid)
+{
+ int value = (insn >> 20) & 0x1f;
+
+ if (value > 28)
+ *invalid = true;
+ return value;
+}
+
+#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
+static unsigned long long \
+insert_nps_##NAME (unsigned long long insn, \
+ long long value, \
+ const char **errmsg) \
+{ \
+ if (value < 1 || value > UPPER) \
+ *errmsg = _("value must be in the range 1 to " #UPPER); \
+ if (value == UPPER) \
+ value = 0; \
+ return insn | (value << SHIFT); \
+} \
+ \
+static long long \
+extract_nps_##NAME (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
+{ \
+ int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
+ if (value == 0) \
+ value = UPPER; \
+ return value; \
+}
+
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
+
+static unsigned long long
+insert_nps_min_hofs (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value < 0 || value > 240)
+ *errmsg = _("value must be in the range 0 to 240");
+ if ((value % 16) != 0)
+ *errmsg = _("value must be a multiple of 16");
+ value = value / 16;
+ return insn | (value << 6);
+}
+
+static long long
+extract_nps_min_hofs (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 6) & 0xF;
+ return value * 16;
+}
+
+#define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \
+ static unsigned long long \
+insert_nps_##NAME (unsigned long long insn, \
+ long long value, \
+ const char **errmsg) \
+{ \
+ if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
+ *errmsg = _("invalid address type for operand"); \
+ return insn; \
+} \
+ \
+static long long \
+extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
+ bool *invalid ATTRIBUTE_UNUSED) \
+{ \
+ return ARC_NPS400_ADDRTYPE_##VALUE; \
+}
+
+MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
+MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
+MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
+MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
+MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
+MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
+MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
+MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
+MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
+MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
+MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
+MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
+MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
+MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
+MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
+MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
+
+static unsigned long long
+insert_nps_rbdouble_64 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value < 0 || value > 31)
+ *errmsg = _("value must be in the range 0 to 31");
+ return insn | (value << 43) | (value << 48);
+}
+
+
+static long long
+extract_nps_rbdouble_64 (unsigned long long insn,
+ bool *invalid)
+{
+ int value1 = (insn >> 43) & 0x1F;
+ int value2 = (insn >> 48) & 0x1F;
+
+ if (value1 != value2)
+ *invalid = true;
+
+ return value1;
+}
+
+static unsigned long long
+insert_nps_misc_imm_offset (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value & 0x3)
+ {
+ *errmsg = _("invalid position, should be one of: 0,4,8,...124.");
+ value = 0;
+ }
+ insn |= (value << 6);
+ return insn;
+}
+
+static long long int
+extract_nps_misc_imm_offset (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 8) & 0x1f) * 4;
+}
+
+static long long int
+extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = 0;
+
+ value |= ((insn >> 6) & 0x003f) << 0;
+ value |= ((insn >> 0) & 0x003f) << 6;
+
+ return value;
+}
+
+/* Include the generic extract/insert functions. Order is important
+ as some of the functions present in the .h may be disabled via
+ defines. */
+#include "arc-fxi.h"
+
+/* The flag operands enum. */
+#define FLAG(NAME, NAMESTR, CODE, BITS, SHIFT, FAVAIL) \
+ F_##NAME,
+enum arc_flag_operand_enum {
+ F_INVALID = -1,
+ F_NULL = 0,
+#include "arc-flag.def"
+ F_SIZE,
+};
+#undef FLAG
+
+/* The flag operands name. */
+#define FLAG(NAME, NAMESTR, CODE, BITS, SHIFT, FAVAIL) \
+ "F_" #NAME,
+const char *flag_operand_name[F_SIZE] = {
+ "F_NULL",
+#include "arc-flag.def"
+};
+#undef FLAG
+
+/* The flag operands table.
+
+ The format of the table is
+ NAME CODE BITS SHIFT FAVAIL. */
+#define FLAG(NAME, NAMESTR, CODE, BITS, SHIFT, FAVAIL) \
+ [F_##NAME] = { NAMESTR, CODE, BITS, SHIFT, FAVAIL },
+const struct arc_flag_operand arc_flag_operands[F_SIZE] =
+{
+ [F_NULL] = { 0, 0, 0, 0, 0 },
+ #include "arc-flag.def"
+};
+#undef FLAG
+
+const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
+
+/* Enum of the flag classes. */
+#define FLAG_CLASS(NAME, CLASS, INSERT_FN, EXTRACT_FN, ...) \
+ C_##NAME,
+enum arc_flag_class_enum {
+ C_INVALID = -1,
+ #include "arc-flag-classes.def"
+ C_SIZE
+};
+#undef FLAG_CLASS
+
+/* Table of the flag classes.
+
+ The format of the table is
+ CLASS {FLAG_CODE}. */
+#define FLAG_CLASS(NAME, CLASS, INSERT_FN, EXTRACT_FN, ...) \
+ [C_##NAME] = { \
+ .flag_class = CLASS, \
+ .insert = INSERT_FN, \
+ .extract = EXTRACT_FN, \
+ .flags = { __VA_ARGS__, F_NULL } \
+ },
+const struct arc_flag_class arc_flag_classes[C_SIZE] =
+{
+ #include "arc-flag-classes.def"
+};
+#undef FLAG_CLASS
+
+const unsigned char flags_none[] = { 0 };
+const unsigned char flags_f[] = { C_F };
+const unsigned char flags_cc[] = { C_CC };
+const unsigned char flags_ccf[] = { C_CC, C_F };
+
+/* The operands enum. */
+#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, INSERT_FN, EXTRACT_FN) \
+ NAME,
+enum arc_operand_enum {
+ ARC_OPERAND_INVALID = -1,
+ UNUSED = 0,
+#include "arc-operands.def"
+ ARC_OPERAND_SIZE
+};
+#undef ARC_OPERAND
+
+/* The operands name. */
+#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, INSERT_FN, EXTRACT_FN) \
+ #NAME,
+const char *arc_operand_name[ARC_OPERAND_SIZE] = {
+ "UNUSED",
+#include "arc-operands.def"
+};
+#undef ARC_OPERAND
+/* The operands table.
+
+ The format of the operands table is:
+
+ BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
+#define ARC_OPERAND(NAME, BITS, SHIFT, RELOC, FLAGS, INSERT_FN, EXTRACT_FN) \
+ [NAME] = { \
+ .bits = BITS, \
+ .shift = SHIFT, \
+ .default_reloc = RELOC, \
+ .flags = FLAGS, \
+ .insert = INSERT_FN, \
+ .extract = EXTRACT_FN \
+ },
+const struct arc_operand arc_operands[ARC_OPERAND_SIZE] =
+{
+ /* The fields are bits, shift, insert, extract, flags. The zero
+ index is used to indicate end-of-list. */
+ [UNUSED] = { 0, 0, 0, 0, 0, 0 },
+#include "arc-operands.def"
+};
+#undef ARC_OPERAND
+
+const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
+
+const unsigned arc_Toperand = FKT_T;
+const unsigned arc_NToperand = FKT_NT;
+
+const unsigned char arg_none[] = { 0 };
+const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
+const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
+const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
+const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
+const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
+const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
+const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
+const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
+const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
+const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
+const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
+
+const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
+const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
+const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
+
+const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
+const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
+const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
+
+const unsigned char arg_32bit_rbrc[] = { RB, RC };
+const unsigned char arg_32bit_zarc[] = { ZA, RC };
+const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
+const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
+const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
+const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
+
+const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
+const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
+const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
+const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
+
+const unsigned char arg_32bit_rc[] = { RC };
+const unsigned char arg_32bit_u6[] = { UIMM6_20 };
+const unsigned char arg_32bit_limm[] = { LIMM };
+
+/* List with special cases instructions and the applicable flags. */
+const struct arc_flag_special arc_flag_special_cases[] =
+{
+ { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM,
+ F_NO_T, F_NULL } },
+ { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
+ { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
+};
+
+const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
+
+/* Relocations. */
+const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
+{
+ { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+
+ /* Next two entries will cover the undefined behavior ldb/stb with
+ address scaling. */
+ { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
+ { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
+
+ { "sda", "ld", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
+ { "sda", "st", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
+ { "sda", "ldd", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
+ { "sda", "std", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
+
+ /* Short instructions. */
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
+ { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
+
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
+
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
+ BFD_RELOC_ARC_S25H_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
+ BFD_RELOC_ARC_S21H_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
+ BFD_RELOC_ARC_S25W_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
+ BFD_RELOC_ARC_S21W_PCREL_PLT },
+
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
+};
+
+const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
+
+const struct arc_pseudo_insn arc_pseudo_insns[] =
+{
+ { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+ { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+
+ { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+
+ { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+
+ { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+
+ { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+};
+
+const unsigned arc_num_pseudo_insn =
+ sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
+
+/* ARC64 pseudo instructions. */
+const struct arc_pseudo_insn arc64_pseudo_insns[] =
+{
+ { "pushl", "stl", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, -8, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+ { "popl", "ldl", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, 8, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+};
+
+const unsigned arc64_num_pseudo_insn =
+ sizeof (arc64_pseudo_insns) / sizeof (*arc64_pseudo_insns);
+
+const struct arc_aux_reg arc_aux_regs[] =
+{
+#undef DEF
+#define DEF(ADDR, CPU, SUBCLASS, NAME) \
+ { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
+
+#include "arc-regs.h"
+
+#undef DEF
+};
+
+const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
+
+/* NOTE: The order of this array MUST be consistent with 'enum
+ arc_rlx_types' located in tc-arc.h! */
+const struct arc_opcode arc_relax_opcodes[] =
+{
+ { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
+
+ /* bl_s s13 11111sssssssssss. */
+ { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM13_A32_5_S }, { 0 }},
+
+ /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
+ { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM25_A32_5 }, { C_D }},
+
+ /* b_s s10 1111000sssssssss. */
+ { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM10_A16_7_S }, { 0 }},
+
+ /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
+ { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM25_A16_5 }, { C_D }},
+
+ /* add_s c,b,u3 01101bbbccc00uuu. */
+ { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
+
+ /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
+ { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, UIMM6_20R }, { C_F }},
+
+ /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
+ { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, LIMM }, { C_F }},
+
+ /* ld_s c,b,u7 10000bbbcccuuuuu. */
+ { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
+
+ /* ld<.di><.aa><.x><zz> a,b,s9
+ 00010bbbssssssssSBBBDaaZZXAAAAAA. */
+ { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
+ { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+
+ /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
+ { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RA, BRAKET, RB, LIMM, BRAKETdup },
+ { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+
+ /* mov_s b,u8 11011bbbuuuuuuuu. */
+ { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB_S, UIMM8_8R_S }, { 0 }},
+
+ /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
+ { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, SIMM12_20R }, { C_F }},
+
+ /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
+ { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, LIMM }, { C_F }},
+
+ /* sub_s c,b,u3 01101bbbccc01uuu. */
+ { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
+
+ /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
+ { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, UIMM6_20R }, { C_F }},
+
+ /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
+ { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, LIMM }, { C_F }},
+
+ /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
+ { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
+ | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
+
+ /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
+ { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
+ | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
+
+ /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
+ { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, UIMM6_20R }, { C_F, C_CC }},
+
+ /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
+ { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, LIMM }, { C_F, C_CC }},
+
+ /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
+ { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
+
+ /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
+ { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RB, RBdup, LIMM }, { C_F, C_CC }}
+};
+
+const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
+
+/* Return length of an opcode in bytes. */
+
+int
+arc_opcode_len (const struct arc_opcode *opcode)
+{
+ if (opcode->mask < 0x10000ull)
+ return 2;
+
+ if (opcode->mask < 0x100000000ull)
+ return 4;
+
+ if (opcode->mask < 0x1000000000000ull)
+ return 6;
+
+ return 8;
+}
diff --git a/opcodes/configure b/opcodes/configure
index a65b0a2f95b..f1c077f4d42 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12551,6 +12551,7 @@ if test x${all_targets} = xfalse ; then
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
bfd_amdgcn_arch) ;;
bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
+ bfd_arc64_arch) ta="$ta arc-dis.lo arc64-opc.lo arc-ext.lo" ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
bfd_avr_arch) ta="$ta avr-dis.lo" ;;
bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
diff --git a/opcodes/configure.ac b/opcodes/configure.ac
index cae2a67ff10..d11257453b2 100644
--- a/opcodes/configure.ac
+++ b/opcodes/configure.ac
@@ -268,6 +268,7 @@ if test x${all_targets} = xfalse ; then
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
bfd_amdgcn_arch) ;;
bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
+ bfd_arc64_arch) ta="$ta arc-dis.lo arc64-opc.lo arc-ext.lo" ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
bfd_avr_arch) ta="$ta avr-dis.lo" ;;
bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 3067445485b..dff0995c926 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -38,6 +38,7 @@
#define ARCH_tilegx
#endif
#define ARCH_arc
+#define ARCH_arc64
#define ARCH_arm
#define ARCH_avr
#define ARCH_bfin
@@ -136,6 +137,11 @@ disassembler (enum bfd_architecture a,
disassemble = arc_get_disassembler (abfd);
break;
#endif
+#ifdef ARCH_arc64
+ case bfd_arch_arc64:
+ disassemble = arc_get_disassembler (abfd);
+ break;
+#endif
#ifdef ARCH_arm
case bfd_arch_arm:
if (big)
--
2.30.2
^ permalink raw reply [flat|nested] 14+ messages in thread
* [committed 08/10] arc: New ARCv3 ISA instruction table
2023-09-25 8:35 [committed 01/10] arc: Add new GAS tests for ARCv3 Claudiu Zissulescu
` (5 preceding siblings ...)
2023-09-25 8:35 ` [committed 07/10] arc: Add new opcode functions for " Claudiu Zissulescu
@ 2023-09-25 8:35 ` Claudiu Zissulescu
2023-09-25 8:35 ` [committed 09/10] arc: Update arc's gas tests Claudiu Zissulescu
` (3 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Claudiu Zissulescu @ 2023-09-25 8:35 UTC (permalink / raw)
To: binutils; +Cc: fbedard, Claudiu Zissulescu
From: Claudiu Zissulescu <claziss@synopsys.com>
opcodes/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* opcodes/arc64-tbl.h: New file.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
---
opcodes/arc64-tbl.h | 11422 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 11422 insertions(+)
create mode 100644 opcodes/arc64-tbl.h
diff --git a/opcodes/arc64-tbl.h b/opcodes/arc64-tbl.h
new file mode 100644
index 00000000000..8db1953d732
--- /dev/null
+++ b/opcodes/arc64-tbl.h
@@ -0,0 +1,11422 @@
+/* ARCv3 instruction defintions.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+/* abs<.f> b,c 00100bbb00101111FBBBCCCCCC001001. */
+{ "abs", 0x202F0009, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* abs<.f> 0,c 0010011000101111F111CCCCCC001001. */
+{ "abs", 0x262F7009, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* abs<.f> b,u6 00100bbb01101111FBBBuuuuuu001001. */
+{ "abs", 0x206F0009, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* abs<.f> 0,u6 0010011001101111F111uuuuuu001001. */
+{ "abs", 0x266F7009, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* abs<.f> b,limm 00100bbb00101111FBBB111110001001. */
+{ "abs", 0x202F0F89, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* abs<.f> 0,limm 0010011000101111F111111110001001. */
+{ "abs", 0x262F7F89, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* absl<.f> RB,RC 01011bbb00101111FBBBcccccc001001. */
+{ "absl", 0x582F0009, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* absl<.f> 0,RC 0101111000101111F111cccccc001001. */
+{ "absl", 0x5E2F7009, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* absl<.f> RB,u6 01011bbb01101111FBBBuuuuuu001001. */
+{ "absl", 0x586F0009, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* absl<.f> 0,u6 0101111001101111F111uuuuuu001001. */
+{ "absl", 0x5E6F7009, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* absl<.f> RB,ximm 01011bbb00101111FBBB111100001001. */
+{ "absl", 0x582F0F09, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* absl<.f> 0,ximm 0101111000101111F111111100001001. */
+{ "absl", 0x5E2F7F09, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* absl<.f> RB,limm 01011bbb00101111FBBB111110001001. */
+{ "absl", 0x582F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* absl<.f> 0,limm 0101111000101111F111111110001001. */
+{ "absl", 0x5E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* abs_s b,c 01111bbbccc10001. */
+{ "abs_s", 0x00007811, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* adc<.f> a,b,c 00100bbb00000001FBBBCCCCCCAAAAAA. */
+{ "adc", 0x20010000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* adc<.f> 0,b,c 00100bbb00000001FBBBCCCCCC111110. */
+{ "adc", 0x2001003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* adc<.f><.cc> b,b,c 00100bbb11000001FBBBCCCCCC0QQQQQ. */
+{ "adc", 0x20C10000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* adc<.f> a,b,u6 00100bbb01000001FBBBuuuuuuAAAAAA. */
+{ "adc", 0x20410000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* adc<.f> 0,b,u6 00100bbb01000001FBBBuuuuuu111110. */
+{ "adc", 0x2041003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* adc<.f><.cc> b,b,u6 00100bbb11000001FBBBuuuuuu1QQQQQ. */
+{ "adc", 0x20C10020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* adc<.f> b,b,s12 00100bbb10000001FBBBssssssSSSSSS. */
+{ "adc", 0x20810000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* adc<.f> a,limm,c 0010011000000001F111CCCCCCAAAAAA. */
+{ "adc", 0x26017000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* adc<.f> a,b,limm 00100bbb00000001FBBB111110AAAAAA. */
+{ "adc", 0x20010F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* adc<.f> 0,limm,c 0010011000000001F111CCCCCC111110. */
+{ "adc", 0x2601703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* adc<.f> 0,b,limm 00100bbb00000001FBBB111110111110. */
+{ "adc", 0x20010FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* adc<.f><.cc> b,b,limm 00100bbb11000001FBBB1111100QQQQQ. */
+{ "adc", 0x20C10F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* adc<.f><.cc> 0,limm,c 0010011011000001F111CCCCCC0QQQQQ. */
+{ "adc", 0x26C17000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* adc<.f> a,limm,u6 0010011001000001F111uuuuuuAAAAAA. */
+{ "adc", 0x26417000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adc<.f> 0,limm,u6 0010011001000001F111uuuuuu111110. */
+{ "adc", 0x2641703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adc<.f><.cc> 0,limm,u6 0010011011000001F111uuuuuu1QQQQQ. */
+{ "adc", 0x26C17020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* adc<.f> 0,limm,s12 0010011010000001F111ssssssSSSSSS. */
+{ "adc", 0x26817000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* adc<.f> a,limm,limm 0010011000000001F111111110AAAAAA. */
+{ "adc", 0x26017F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* adc<.f> 0,limm,limm 0010011000000001F111111110111110. */
+{ "adc", 0x26017FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* adc<.f><.cc> 0,limm,limm 0010011011000001F1111111100QQQQQ. */
+{ "adc", 0x26C17F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* adcl<.f> RA,RB,RC 01011bbb00000001FBBBccccccaaaaaa. */
+{ "adcl", 0x58010000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* adcl<.f> 0,RB,RC 01011bbb00000001FBBBcccccc111110. */
+{ "adcl", 0x5801003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* adcl<.f><.cc> RB,RB,RC 01011bbb11000001FBBBcccccc0QQQQQ. */
+{ "adcl", 0x58C10000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* adcl<.f> RA,RB,u6 01011bbb01000001FBBBuuuuuuaaaaaa. */
+{ "adcl", 0x58410000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* adcl<.f> 0,RB,u6 01011bbb01000001FBBBuuuuuu111110. */
+{ "adcl", 0x5841003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* adcl<.f><.cc> RB,RB,u6 01011bbb11000001FBBBuuuuuu1QQQQQ. */
+{ "adcl", 0x58C10020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* adcl<.f> RB,RB,s12 01011bbb10000001FBBBssssssSSSSSS. */
+{ "adcl", 0x58810000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* adcl<.f> RA,ximm,RC 0101110000000001F111ccccccaaaaaa. */
+{ "adcl", 0x5C017000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* adcl<.f> RA,RB,ximm 01011bbb00000001FBBB111100aaaaaa. */
+{ "adcl", 0x58010F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* adcl<.f> 0,ximm,RC 0101110000000001F111cccccc111110. */
+{ "adcl", 0x5C01703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* adcl<.f> 0,RB,ximm 01011bbb00000001FBBB111100111110. */
+{ "adcl", 0x58010F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* adcl<.f><.cc> 0,ximm,RC 0101110011000001F111cccccc0QQQQQ. */
+{ "adcl", 0x5CC17000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* adcl<.f><.cc> RB,RB,ximm 01011bbb11000001FBBB1111000QQQQQ. */
+{ "adcl", 0x58C10F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* adcl<.f> RA,ximm,u6 0101110001000001F111uuuuuuaaaaaa. */
+{ "adcl", 0x5C417000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* adcl<.f> 0,ximm,u6 0101110001000001F111uuuuuu111110. */
+{ "adcl", 0x5C41703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* adcl<.f><.cc> 0,ximm,u6 0101110011000001F111uuuuuu1QQQQQ. */
+{ "adcl", 0x5CC17020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* adcl<.f> RA,limm,RC 0101111000000001F111ccccccaaaaaa. */
+{ "adcl", 0x5E017000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* adcl<.f> RA,RB,limm 01011bbb00000001FBBB111110aaaaaa. */
+{ "adcl", 0x58010F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* adcl<.f> 0,limm,RC 0101111000000001F111cccccc111110. */
+{ "adcl", 0x5E01703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* adcl<.f> 0,RB,limm 01011bbb00000001FBBB111110111110. */
+{ "adcl", 0x58010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* adcl<.f><.cc> 0,limm,RC 0101111011000001F111cccccc0QQQQQ. */
+{ "adcl", 0x5EC17000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* adcl<.f><.cc> RB,RB,limm 01011bbb11000001FBBB1111100QQQQQ. */
+{ "adcl", 0x58C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* adcl<.f> RA,limm,u6 0101111001000001F111uuuuuuaaaaaa. */
+{ "adcl", 0x5E417000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adcl<.f> 0,limm,u6 0101111001000001F111uuuuuu111110. */
+{ "adcl", 0x5E41703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adcl<.f><.cc> 0,limm,u6 0101111011000001F111uuuuuu1QQQQQ. */
+{ "adcl", 0x5EC17020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* adcl<.f> 0,ximm,s12 0101110010000001F111ssssssSSSSSS. */
+{ "adcl", 0x5C817000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* adcl<.f> 0,limm,s12 0101111010000001F111ssssssSSSSSS. */
+{ "adcl", 0x5E817000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* adcl<.f> RA,ximm,ximm 0101110000000001F111111100aaaaaa. */
+{ "adcl", 0x5C017F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* adcl<.f> 0,ximm,ximm 0101110000000001F111111100111110. */
+{ "adcl", 0x5C017F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* adcl<.f><.cc> 0,ximm,ximm 0101110011000001F1111111000QQQQQ. */
+{ "adcl", 0x5CC17F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* adcl<.f> RA,limm,limm 0101111000000001F111111110aaaaaa. */
+{ "adcl", 0x5E017F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* adcl<.f> 0,limm,limm 0101111000000001F111111110111110. */
+{ "adcl", 0x5E017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* adcl<.f><.cc> 0,limm,limm 0101111011000001F1111111100QQQQQ. */
+{ "adcl", 0x5EC17F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add<.f> a,b,c 00100bbb00000000FBBBCCCCCCAAAAAA. */
+{ "add", 0x20000000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add<.f> 0,b,c 00100bbb00000000FBBBCCCCCC111110. */
+{ "add", 0x2000003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add<.f><.cc> b,b,c 00100bbb11000000FBBBCCCCCC0QQQQQ. */
+{ "add", 0x20C00000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
+{ "add", 0x20400000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add<.f> 0,b,u6 00100bbb01000000FBBBuuuuuu111110. */
+{ "add", 0x2040003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
+{ "add", 0x20C00020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add<.f> b,b,s12 00100bbb10000000FBBBssssssSSSSSS. */
+{ "add", 0x20800000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add<.f> a,limm,c 0010011000000000F111CCCCCCAAAAAA. */
+{ "add", 0x26007000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
+{ "add", 0x20000F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add<.f> 0,limm,c 0010011000000000F111CCCCCC111110. */
+{ "add", 0x2600703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add<.f> 0,b,limm 00100bbb00000000FBBB111110111110. */
+{ "add", 0x20000FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
+{ "add", 0x20C00F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add<.f><.cc> 0,limm,c 0010011011000000F111CCCCCC0QQQQQ. */
+{ "add", 0x26C07000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add<.f> a,limm,u6 0010011001000000F111uuuuuuAAAAAA. */
+{ "add", 0x26407000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add<.f> 0,limm,u6 0010011001000000F111uuuuuu111110. */
+{ "add", 0x2640703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add<.f><.cc> 0,limm,u6 0010011011000000F111uuuuuu1QQQQQ. */
+{ "add", 0x26C07020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add<.f> 0,limm,s12 0010011010000000F111ssssssSSSSSS. */
+{ "add", 0x26807000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add<.f> a,limm,limm 0010011000000000F111111110AAAAAA. */
+{ "add", 0x26007F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add<.f> 0,limm,limm 0010011000000000F111111110111110. */
+{ "add", 0x26007FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add<.f><.cc> 0,limm,limm 0010011011000000F1111111100QQQQQ. */
+{ "add", 0x26C07F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add1<.f> a,b,c 00100bbb00010100FBBBCCCCCCAAAAAA. */
+{ "add1", 0x20140000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add1<.f> 0,b,c 00100bbb00010100FBBBCCCCCC111110. */
+{ "add1", 0x2014003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add1<.f><.cc> b,b,c 00100bbb11010100FBBBCCCCCC0QQQQQ. */
+{ "add1", 0x20D40000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add1<.f> a,b,u6 00100bbb01010100FBBBuuuuuuAAAAAA. */
+{ "add1", 0x20540000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add1<.f> 0,b,u6 00100bbb01010100FBBBuuuuuu111110. */
+{ "add1", 0x2054003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add1<.f><.cc> b,b,u6 00100bbb11010100FBBBuuuuuu1QQQQQ. */
+{ "add1", 0x20D40020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1<.f> b,b,s12 00100bbb10010100FBBBssssssSSSSSS. */
+{ "add1", 0x20940000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add1<.f> a,limm,c 0010011000010100F111CCCCCCAAAAAA. */
+{ "add1", 0x26147000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add1<.f> a,b,limm 00100bbb00010100FBBB111110AAAAAA. */
+{ "add1", 0x20140F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add1<.f> 0,limm,c 0010011000010100F111CCCCCC111110. */
+{ "add1", 0x2614703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add1<.f> 0,b,limm 00100bbb00010100FBBB111110111110. */
+{ "add1", 0x20140FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add1<.f><.cc> b,b,limm 00100bbb11010100FBBB1111100QQQQQ. */
+{ "add1", 0x20D40F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add1<.f><.cc> 0,limm,c 0010011011010100F111CCCCCC0QQQQQ. */
+{ "add1", 0x26D47000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add1<.f> a,limm,u6 0010011001010100F111uuuuuuAAAAAA. */
+{ "add1", 0x26547000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add1<.f> 0,limm,u6 0010011001010100F111uuuuuu111110. */
+{ "add1", 0x2654703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add1<.f><.cc> 0,limm,u6 0010011011010100F111uuuuuu1QQQQQ. */
+{ "add1", 0x26D47020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1<.f> 0,limm,s12 0010011010010100F111ssssssSSSSSS. */
+{ "add1", 0x26947000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add1<.f> a,limm,limm 0010011000010100F111111110AAAAAA. */
+{ "add1", 0x26147F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add1<.f> 0,limm,limm 0010011000010100F111111110111110. */
+{ "add1", 0x26147FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add1<.f><.cc> 0,limm,limm 0010011011010100F1111111100QQQQQ. */
+{ "add1", 0x26D47F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add1l<.f> RA,RB,RC 01011bbb00010100FBBBccccccaaaaaa. */
+{ "add1l", 0x58140000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add1l<.f> 0,RB,RC 01011bbb00010100FBBBcccccc111110. */
+{ "add1l", 0x5814003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add1l<.f><.cc> RB,RB,RC 01011bbb11010100FBBBcccccc0QQQQQ. */
+{ "add1l", 0x58D40000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add1l<.f> RA,RB,u6 01011bbb01010100FBBBuuuuuuaaaaaa. */
+{ "add1l", 0x58540000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add1l<.f> 0,RB,u6 01011bbb01010100FBBBuuuuuu111110. */
+{ "add1l", 0x5854003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add1l<.f><.cc> RB,RB,u6 01011bbb11010100FBBBuuuuuu1QQQQQ. */
+{ "add1l", 0x58D40020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1l<.f> RB,RB,s12 01011bbb10010100FBBBssssssSSSSSS. */
+{ "add1l", 0x58940000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add1l<.f> RA,ximm,RC 0101110000010100F111ccccccaaaaaa. */
+{ "add1l", 0x5C147000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* add1l<.f> RA,RB,ximm 01011bbb00010100FBBB111100aaaaaa. */
+{ "add1l", 0x58140F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* add1l<.f> 0,ximm,RC 0101110000010100F111cccccc111110. */
+{ "add1l", 0x5C14703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* add1l<.f> 0,RB,ximm 01011bbb00010100FBBB111100111110. */
+{ "add1l", 0x58140F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* add1l<.f><.cc> 0,ximm,RC 0101110011010100F111cccccc0QQQQQ. */
+{ "add1l", 0x5CD47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* add1l<.f><.cc> RB,RB,ximm 01011bbb11010100FBBB1111000QQQQQ. */
+{ "add1l", 0x58D40F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* add1l<.f> RA,ximm,u6 0101110001010100F111uuuuuuaaaaaa. */
+{ "add1l", 0x5C547000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add1l<.f> 0,ximm,u6 0101110001010100F111uuuuuu111110. */
+{ "add1l", 0x5C54703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add1l<.f><.cc> 0,ximm,u6 0101110011010100F111uuuuuu1QQQQQ. */
+{ "add1l", 0x5CD47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1l<.f> RA,limm,RC 0101111000010100F111ccccccaaaaaa. */
+{ "add1l", 0x5E147000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add1l<.f> RA,RB,limm 01011bbb00010100FBBB111110aaaaaa. */
+{ "add1l", 0x58140F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add1l<.f> 0,limm,RC 0101111000010100F111cccccc111110. */
+{ "add1l", 0x5E14703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add1l<.f> 0,RB,limm 01011bbb00010100FBBB111110111110. */
+{ "add1l", 0x58140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add1l<.f><.cc> 0,limm,RC 0101111011010100F111cccccc0QQQQQ. */
+{ "add1l", 0x5ED47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add1l<.f><.cc> RB,RB,limm 01011bbb11010100FBBB1111100QQQQQ. */
+{ "add1l", 0x58D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add1l<.f> RA,limm,u6 0101111001010100F111uuuuuuaaaaaa. */
+{ "add1l", 0x5E547000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add1l<.f> 0,limm,u6 0101111001010100F111uuuuuu111110. */
+{ "add1l", 0x5E54703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add1l<.f><.cc> 0,limm,u6 0101111011010100F111uuuuuu1QQQQQ. */
+{ "add1l", 0x5ED47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1l<.f> 0,ximm,s12 0101110010010100F111ssssssSSSSSS. */
+{ "add1l", 0x5C947000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* add1l<.f> 0,limm,s12 0101111010010100F111ssssssSSSSSS. */
+{ "add1l", 0x5E947000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add1l<.f> RA,ximm,ximm 0101110000010100F111111100aaaaaa. */
+{ "add1l", 0x5C147F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* add1l<.f> 0,ximm,ximm 0101110000010100F111111100111110. */
+{ "add1l", 0x5C147F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* add1l<.f><.cc> 0,ximm,ximm 0101110011010100F1111111000QQQQQ. */
+{ "add1l", 0x5CD47F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* add1l<.f> RA,limm,limm 0101111000010100F111111110aaaaaa. */
+{ "add1l", 0x5E147F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add1l<.f> 0,limm,limm 0101111000010100F111111110111110. */
+{ "add1l", 0x5E147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add1l<.f><.cc> 0,limm,limm 0101111011010100F1111111100QQQQQ. */
+{ "add1l", 0x5ED47F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add1_s b,b,c 01111bbbccc10100. */
+{ "add1_s", 0x00007814, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* add2<.f> a,b,c 00100bbb00010101FBBBCCCCCCAAAAAA. */
+{ "add2", 0x20150000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add2<.f> 0,b,c 00100bbb00010101FBBBCCCCCC111110. */
+{ "add2", 0x2015003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add2<.f><.cc> b,b,c 00100bbb11010101FBBBCCCCCC0QQQQQ. */
+{ "add2", 0x20D50000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add2<.f> a,b,u6 00100bbb01010101FBBBuuuuuuAAAAAA. */
+{ "add2", 0x20550000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add2<.f> 0,b,u6 00100bbb01010101FBBBuuuuuu111110. */
+{ "add2", 0x2055003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add2<.f><.cc> b,b,u6 00100bbb11010101FBBBuuuuuu1QQQQQ. */
+{ "add2", 0x20D50020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2<.f> b,b,s12 00100bbb10010101FBBBssssssSSSSSS. */
+{ "add2", 0x20950000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add2<.f> a,limm,c 0010011000010101F111CCCCCCAAAAAA. */
+{ "add2", 0x26157000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add2<.f> a,b,limm 00100bbb00010101FBBB111110AAAAAA. */
+{ "add2", 0x20150F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add2<.f> 0,limm,c 0010011000010101F111CCCCCC111110. */
+{ "add2", 0x2615703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add2<.f> 0,b,limm 00100bbb00010101FBBB111110111110. */
+{ "add2", 0x20150FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add2<.f><.cc> b,b,limm 00100bbb11010101FBBB1111100QQQQQ. */
+{ "add2", 0x20D50F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add2<.f><.cc> 0,limm,c 0010011011010101F111CCCCCC0QQQQQ. */
+{ "add2", 0x26D57000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add2<.f> a,limm,u6 0010011001010101F111uuuuuuAAAAAA. */
+{ "add2", 0x26557000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add2<.f> 0,limm,u6 0010011001010101F111uuuuuu111110. */
+{ "add2", 0x2655703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add2<.f><.cc> 0,limm,u6 0010011011010101F111uuuuuu1QQQQQ. */
+{ "add2", 0x26D57020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2<.f> 0,limm,s12 0010011010010101F111ssssssSSSSSS. */
+{ "add2", 0x26957000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add2<.f> a,limm,limm 0010011000010101F111111110AAAAAA. */
+{ "add2", 0x26157F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add2<.f> 0,limm,limm 0010011000010101F111111110111110. */
+{ "add2", 0x26157FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add2<.f><.cc> 0,limm,limm 0010011011010101F1111111100QQQQQ. */
+{ "add2", 0x26D57F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add2l<.f> RA,RB,RC 01011bbb00010101FBBBccccccaaaaaa. */
+{ "add2l", 0x58150000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add2l<.f> 0,RB,RC 01011bbb00010101FBBBcccccc111110. */
+{ "add2l", 0x5815003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add2l<.f><.cc> RB,RB,RC 01011bbb11010101FBBBcccccc0QQQQQ. */
+{ "add2l", 0x58D50000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add2l<.f> RA,RB,u6 01011bbb01010101FBBBuuuuuuaaaaaa. */
+{ "add2l", 0x58550000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add2l<.f> 0,RB,u6 01011bbb01010101FBBBuuuuuu111110. */
+{ "add2l", 0x5855003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add2l<.f><.cc> RB,RB,u6 01011bbb11010101FBBBuuuuuu1QQQQQ. */
+{ "add2l", 0x58D50020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2l<.f> RB,RB,s12 01011bbb10010101FBBBssssssSSSSSS. */
+{ "add2l", 0x58950000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add2l<.f> RA,ximm,RC 0101110000010101F111ccccccaaaaaa. */
+{ "add2l", 0x5C157000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* add2l<.f> RA,RB,ximm 01011bbb00010101FBBB111100aaaaaa. */
+{ "add2l", 0x58150F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* add2l<.f> 0,ximm,RC 0101110000010101F111cccccc111110. */
+{ "add2l", 0x5C15703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* add2l<.f> 0,RB,ximm 01011bbb00010101FBBB111100111110. */
+{ "add2l", 0x58150F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* add2l<.f><.cc> 0,ximm,RC 0101110011010101F111cccccc0QQQQQ. */
+{ "add2l", 0x5CD57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* add2l<.f><.cc> RB,RB,ximm 01011bbb11010101FBBB1111000QQQQQ. */
+{ "add2l", 0x58D50F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* add2l<.f> RA,ximm,u6 0101110001010101F111uuuuuuaaaaaa. */
+{ "add2l", 0x5C557000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add2l<.f> 0,ximm,u6 0101110001010101F111uuuuuu111110. */
+{ "add2l", 0x5C55703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add2l<.f><.cc> 0,ximm,u6 0101110011010101F111uuuuuu1QQQQQ. */
+{ "add2l", 0x5CD57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2l<.f> RA,limm,RC 0101111000010101F111ccccccaaaaaa. */
+{ "add2l", 0x5E157000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add2l<.f> RA,RB,limm 01011bbb00010101FBBB111110aaaaaa. */
+{ "add2l", 0x58150F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add2l<.f> 0,limm,RC 0101111000010101F111cccccc111110. */
+{ "add2l", 0x5E15703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add2l<.f> 0,RB,limm 01011bbb00010101FBBB111110111110. */
+{ "add2l", 0x58150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add2l<.f><.cc> 0,limm,RC 0101111011010101F111cccccc0QQQQQ. */
+{ "add2l", 0x5ED57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add2l<.f><.cc> RB,RB,limm 01011bbb11010101FBBB1111100QQQQQ. */
+{ "add2l", 0x58D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add2l<.f> RA,limm,u6 0101111001010101F111uuuuuuaaaaaa. */
+{ "add2l", 0x5E557000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add2l<.f> 0,limm,u6 0101111001010101F111uuuuuu111110. */
+{ "add2l", 0x5E55703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add2l<.f><.cc> 0,limm,u6 0101111011010101F111uuuuuu1QQQQQ. */
+{ "add2l", 0x5ED57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2l<.f> 0,ximm,s12 0101110010010101F111ssssssSSSSSS. */
+{ "add2l", 0x5C957000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* add2l<.f> 0,limm,s12 0101111010010101F111ssssssSSSSSS. */
+{ "add2l", 0x5E957000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add2l<.f> RA,ximm,ximm 0101110000010101F111111100aaaaaa. */
+{ "add2l", 0x5C157F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* add2l<.f> 0,ximm,ximm 0101110000010101F111111100111110. */
+{ "add2l", 0x5C157F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* add2l<.f><.cc> 0,ximm,ximm 0101110011010101F1111111000QQQQQ. */
+{ "add2l", 0x5CD57F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* add2l<.f> RA,limm,limm 0101111000010101F111111110aaaaaa. */
+{ "add2l", 0x5E157F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add2l<.f> 0,limm,limm 0101111000010101F111111110111110. */
+{ "add2l", 0x5E157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add2l<.f><.cc> 0,limm,limm 0101111011010101F1111111100QQQQQ. */
+{ "add2l", 0x5ED57F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add2_s b,b,c 01111bbbccc10101. */
+{ "add2_s", 0x00007815, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* add3<.f> a,b,c 00100bbb00010110FBBBCCCCCCAAAAAA. */
+{ "add3", 0x20160000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add3<.f> 0,b,c 00100bbb00010110FBBBCCCCCC111110. */
+{ "add3", 0x2016003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add3<.f><.cc> b,b,c 00100bbb11010110FBBBCCCCCC0QQQQQ. */
+{ "add3", 0x20D60000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add3<.f> a,b,u6 00100bbb01010110FBBBuuuuuuAAAAAA. */
+{ "add3", 0x20560000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add3<.f> 0,b,u6 00100bbb01010110FBBBuuuuuu111110. */
+{ "add3", 0x2056003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add3<.f><.cc> b,b,u6 00100bbb11010110FBBBuuuuuu1QQQQQ. */
+{ "add3", 0x20D60020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3<.f> b,b,s12 00100bbb10010110FBBBssssssSSSSSS. */
+{ "add3", 0x20960000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add3<.f> a,limm,c 0010011000010110F111CCCCCCAAAAAA. */
+{ "add3", 0x26167000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add3<.f> a,b,limm 00100bbb00010110FBBB111110AAAAAA. */
+{ "add3", 0x20160F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add3<.f> 0,limm,c 0010011000010110F111CCCCCC111110. */
+{ "add3", 0x2616703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add3<.f> 0,b,limm 00100bbb00010110FBBB111110111110. */
+{ "add3", 0x20160FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add3<.f><.cc> b,b,limm 00100bbb11010110FBBB1111100QQQQQ. */
+{ "add3", 0x20D60F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add3<.f><.cc> 0,limm,c 0010011011010110F111CCCCCC0QQQQQ. */
+{ "add3", 0x26D67000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add3<.f> a,limm,u6 0010011001010110F111uuuuuuAAAAAA. */
+{ "add3", 0x26567000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add3<.f> 0,limm,u6 0010011001010110F111uuuuuu111110. */
+{ "add3", 0x2656703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add3<.f><.cc> 0,limm,u6 0010011011010110F111uuuuuu1QQQQQ. */
+{ "add3", 0x26D67020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3<.f> 0,limm,s12 0010011010010110F111ssssssSSSSSS. */
+{ "add3", 0x26967000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add3<.f> a,limm,limm 0010011000010110F111111110AAAAAA. */
+{ "add3", 0x26167F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add3<.f> 0,limm,limm 0010011000010110F111111110111110. */
+{ "add3", 0x26167FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add3<.f><.cc> 0,limm,limm 0010011011010110F1111111100QQQQQ. */
+{ "add3", 0x26D67F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add3l<.f> RA,RB,RC 01011bbb00010110FBBBccccccaaaaaa. */
+{ "add3l", 0x58160000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add3l<.f> 0,RB,RC 01011bbb00010110FBBBcccccc111110. */
+{ "add3l", 0x5816003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add3l<.f><.cc> RB,RB,RC 01011bbb11010110FBBBcccccc0QQQQQ. */
+{ "add3l", 0x58D60000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add3l<.f> RA,RB,u6 01011bbb01010110FBBBuuuuuuaaaaaa. */
+{ "add3l", 0x58560000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add3l<.f> 0,RB,u6 01011bbb01010110FBBBuuuuuu111110. */
+{ "add3l", 0x5856003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add3l<.f><.cc> RB,RB,u6 01011bbb11010110FBBBuuuuuu1QQQQQ. */
+{ "add3l", 0x58D60020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3l<.f> RB,RB,s12 01011bbb10010110FBBBssssssSSSSSS. */
+{ "add3l", 0x58960000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add3l<.f> RA,ximm,RC 0101110000010110F111ccccccaaaaaa. */
+{ "add3l", 0x5C167000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* add3l<.f> RA,RB,ximm 01011bbb00010110FBBB111100aaaaaa. */
+{ "add3l", 0x58160F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* add3l<.f> 0,ximm,RC 0101110000010110F111cccccc111110. */
+{ "add3l", 0x5C16703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* add3l<.f> 0,RB,ximm 01011bbb00010110FBBB111100111110. */
+{ "add3l", 0x58160F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* add3l<.f><.cc> 0,ximm,RC 0101110011010110F111cccccc0QQQQQ. */
+{ "add3l", 0x5CD67000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* add3l<.f><.cc> RB,RB,ximm 01011bbb11010110FBBB1111000QQQQQ. */
+{ "add3l", 0x58D60F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* add3l<.f> RA,ximm,u6 0101110001010110F111uuuuuuaaaaaa. */
+{ "add3l", 0x5C567000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add3l<.f> 0,ximm,u6 0101110001010110F111uuuuuu111110. */
+{ "add3l", 0x5C56703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add3l<.f><.cc> 0,ximm,u6 0101110011010110F111uuuuuu1QQQQQ. */
+{ "add3l", 0x5CD67020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3l<.f> RA,limm,RC 0101111000010110F111ccccccaaaaaa. */
+{ "add3l", 0x5E167000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add3l<.f> RA,RB,limm 01011bbb00010110FBBB111110aaaaaa. */
+{ "add3l", 0x58160F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add3l<.f> 0,limm,RC 0101111000010110F111cccccc111110. */
+{ "add3l", 0x5E16703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add3l<.f> 0,RB,limm 01011bbb00010110FBBB111110111110. */
+{ "add3l", 0x58160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add3l<.f><.cc> 0,limm,RC 0101111011010110F111cccccc0QQQQQ. */
+{ "add3l", 0x5ED67000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add3l<.f><.cc> RB,RB,limm 01011bbb11010110FBBB1111100QQQQQ. */
+{ "add3l", 0x58D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add3l<.f> RA,limm,u6 0101111001010110F111uuuuuuaaaaaa. */
+{ "add3l", 0x5E567000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add3l<.f> 0,limm,u6 0101111001010110F111uuuuuu111110. */
+{ "add3l", 0x5E56703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add3l<.f><.cc> 0,limm,u6 0101111011010110F111uuuuuu1QQQQQ. */
+{ "add3l", 0x5ED67020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3l<.f> 0,ximm,s12 0101110010010110F111ssssssSSSSSS. */
+{ "add3l", 0x5C967000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* add3l<.f> 0,limm,s12 0101111010010110F111ssssssSSSSSS. */
+{ "add3l", 0x5E967000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add3l<.f> RA,ximm,ximm 0101110000010110F111111100aaaaaa. */
+{ "add3l", 0x5C167F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* add3l<.f> 0,ximm,ximm 0101110000010110F111111100111110. */
+{ "add3l", 0x5C167F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* add3l<.f><.cc> 0,ximm,ximm 0101110011010110F1111111000QQQQQ. */
+{ "add3l", 0x5CD67F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* add3l<.f> RA,limm,limm 0101111000010110F111111110aaaaaa. */
+{ "add3l", 0x5E167F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add3l<.f> 0,limm,limm 0101111000010110F111111110111110. */
+{ "add3l", 0x5E167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add3l<.f><.cc> 0,limm,limm 0101111011010110F1111111100QQQQQ. */
+{ "add3l", 0x5ED67F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add3_s b,b,c 01111bbbccc10110. */
+{ "add3_s", 0x00007816, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* addhl RA,RB,RC 01011bbb001011100BBBccccccaaaaaa. */
+{ "addhl", 0x582E0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { 0 }},
+
+/* addhl 0,RB,RC 01011bbb001011100BBBcccccc111110. */
+{ "addhl", 0x582E003E, 0xF8FF803F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+
+/* addhl<.cc> RB,RB,RC 01011bbb111011100BBBcccccc0QQQQQ. */
+{ "addhl", 0x58EE0000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* addhl RA,RB,u6 01011bbb011011100BBBuuuuuuaaaaaa. */
+{ "addhl", 0x586E0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* addhl 0,RB,u6 01011bbb011011100BBBuuuuuu111110. */
+{ "addhl", 0x586E003E, 0xF8FF803F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* addhl<.cc> RB,RB,u6 01011bbb111011100BBBuuuuuu1QQQQQ. */
+{ "addhl", 0x58EE0020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* addhl RB,RB,s12 01011bbb101011100BBBssssssSSSSSS. */
+{ "addhl", 0x58AE0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* addhl RA,limm,RC 01011110001011100111ccccccaaaaaa. */
+{ "addhl", 0x5E2E7000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, HI32, RC }, { 0 }},
+
+/* addhl RA,RB,limm 01011bbb001011100BBB111110aaaaaa. */
+{ "addhl", 0x582E0F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, HI32 }, { 0 }},
+
+/* addhl<.cc> RB,RB,limm 01011bbb111011100BBB1111100QQQQQ. */
+{ "addhl", 0x58EE0F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, HI32 }, { C_CC }},
+
+/* addhl_s h,PCL,ximm 01110011hhh010HH. */
+{ "addhl_s", 0x00007308, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, PCL_S, XIMM_S }, { 0 }},
+
+/* addhl_s h,h,limm 01110001hhh010HH. */
+{ "addhl_s", 0x00007108, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, RH_Sdup, HI32 }, { 0 }},
+
+/* addl<.f> RA,RB,RC 01011bbb00000000FBBBccccccaaaaaa. */
+{ "addl", 0x58000000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* addl<.f> 0,RB,RC 01011bbb00000000FBBBcccccc111110. */
+{ "addl", 0x5800003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* addl<.f><.cc> RB,RB,RC 01011bbb11000000FBBBcccccc0QQQQQ. */
+{ "addl", 0x58C00000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* addl<.f> RA,RB,u6 01011bbb01000000FBBBuuuuuuaaaaaa. */
+{ "addl", 0x58400000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* addl<.f> 0,RB,u6 01011bbb01000000FBBBuuuuuu111110. */
+{ "addl", 0x5840003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* addl<.f><.cc> RB,RB,u6 01011bbb11000000FBBBuuuuuu1QQQQQ. */
+{ "addl", 0x58C00020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* addl<.f> RB,RB,s12 01011bbb10000000FBBBssssssSSSSSS. */
+{ "addl", 0x58800000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* addl<.f> RA,ximm,RC 0101110000000000F111ccccccaaaaaa. */
+{ "addl", 0x5C007000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* addl<.f> RA,RB,ximm 01011bbb00000000FBBB111100aaaaaa. */
+{ "addl", 0x58000F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* addl<.f> 0,ximm,RC 0101110000000000F111cccccc111110. */
+{ "addl", 0x5C00703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* addl<.f> 0,RB,ximm 01011bbb00000000FBBB111100111110. */
+{ "addl", 0x58000F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* addl<.f><.cc> 0,ximm,RC 0101110011000000F111cccccc0QQQQQ. */
+{ "addl", 0x5CC07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* addl<.f><.cc> RB,RB,ximm 01011bbb11000000FBBB1111000QQQQQ. */
+{ "addl", 0x58C00F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* addl<.f> RA,ximm,u6 0101110001000000F111uuuuuuaaaaaa. */
+{ "addl", 0x5C407000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* addl<.f> 0,ximm,u6 0101110001000000F111uuuuuu111110. */
+{ "addl", 0x5C40703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* addl<.f><.cc> 0,ximm,u6 0101110011000000F111uuuuuu1QQQQQ. */
+{ "addl", 0x5CC07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* addl<.f> RA,limm,RC 0101111000000000F111ccccccaaaaaa. */
+{ "addl", 0x5E007000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* addl<.f> RA,RB,limm 01011bbb00000000FBBB111110aaaaaa. */
+{ "addl", 0x58000F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* addl<.f> 0,limm,RC 0101111000000000F111cccccc111110. */
+{ "addl", 0x5E00703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* addl<.f> 0,RB,limm 01011bbb00000000FBBB111110111110. */
+{ "addl", 0x58000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* addl<.f><.cc> 0,limm,RC 0101111011000000F111cccccc0QQQQQ. */
+{ "addl", 0x5EC07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* addl<.f><.cc> RB,RB,limm 01011bbb11000000FBBB1111100QQQQQ. */
+{ "addl", 0x58C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* addl<.f> RA,limm,u6 0101111001000000F111uuuuuuaaaaaa. */
+{ "addl", 0x5E407000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* addl<.f> 0,limm,u6 0101111001000000F111uuuuuu111110. */
+{ "addl", 0x5E40703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* addl<.f><.cc> 0,limm,u6 0101111011000000F111uuuuuu1QQQQQ. */
+{ "addl", 0x5EC07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* addl<.f> 0,ximm,s12 0101110010000000F111ssssssSSSSSS. */
+{ "addl", 0x5C807000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* addl<.f> 0,limm,s12 0101111010000000F111ssssssSSSSSS. */
+{ "addl", 0x5E807000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* addl<.f> RA,ximm,ximm 0101110000000000F111111100aaaaaa. */
+{ "addl", 0x5C007F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* addl<.f> 0,ximm,ximm 0101110000000000F111111100111110. */
+{ "addl", 0x5C007F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* addl<.f><.cc> 0,ximm,ximm 0101110011000000F1111111000QQQQQ. */
+{ "addl", 0x5CC07F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* addl<.f> RA,limm,limm 0101111000000000F111111110aaaaaa. */
+{ "addl", 0x5E007F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* addl<.f> 0,limm,limm 0101111000000000F111111110111110. */
+{ "addl", 0x5E007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* addl<.f><.cc> 0,limm,limm 0101111011000000F1111111100QQQQQ. */
+{ "addl", 0x5EC07F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* addl_s SP,SP,u9 11000UU0101uuuuu. */
+{ "addl_s", 0x0000C0A0, 0x0000F9E0, ARC_OPCODE_ARC64, ARITH, NONE, { SP_S, SP_Sdup, UIMM9_A32_11_S }, { 0 }},
+
+/* addl_s b,b,c 01111bbbccc00001. */
+{ "addl_s", 0x00007801, 0x0000F81F, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* addl_s b,SP,u7 11000bbb100uuuuu. */
+{ "addl_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, SP_S, UIMM7_A32_11_S }, { 0 }},
+
+/* addl_s R0,GP,s11 1100111sssssssss. */
+{ "addl_s", 0x0000CE00, 0x0000FE00, ARC_OPCODE_ARC64, ARITH, NONE, { R0_S, GP_S, SIMM11_A32_7_S }, { 0 }},
+
+/* addl_s h,h,LO32 01110001hhh110HH. */
+{ "addl_s", 0x00007118, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, RH_Sdup, LO32 }, { 0 }},
+
+/* addl_s h,PCL,LO32 01110011hhh110HH. */
+{ "addl_s", 0x00007318, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, PCL_S, LO32 }, { 0 }},
+
+/* add_s a,b,c 01100bbbccc11aaa. */
+{ "add_s", 0x00006018, 0x0000F818,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA_S, RB_S, RC_S }, { 0 }},
+
+/* add_s b,b,h 01110bbbhhh000HH. */
+{ "add_s", 0x00007000, 0x0000F81C,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RH_S }, { 0 }},
+
+/* add_s h,h,s3 01110ssshhh001HH. */
+{ "add_s", 0x00007004, 0x0000F81C,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, RH_Sdup, SIMM3_5_S }, { 0 }},
+
+/* add_s R0,b,u6 01001bbb0UUU1uuu. */
+{ "add_s", 0x00004808, 0x0000F888,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, CD2, { R0_S, RB_S, UIMM6_13_S }, { 0 }},
+
+/* add_s R1,b,u6 01001bbb1UUU1uuu. */
+{ "add_s", 0x00004888, 0x0000F888,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, CD2, { R1_S, RB_S, UIMM6_13_S }, { 0 }},
+
+/* add_s b,b,limm 01110bbb11000011. */
+{ "add_s", 0x000070C3, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, LIMM_S }, { 0 }},
+
+/* add_s 0,limm,s3 01110sss11000111. */
+{ "add_s", 0x000070C7, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA_S, LIMM_S, SIMM3_5_S }, { 0 }},
+
+/* add_s b,sp,u7 11000bbb100uuuuu. */
+{ "add_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, SP_S, UIMM7_A32_11_S }, { 0 }},
+
+/* add_s SP,SP,u7 11000000101uuuuu. */
+{ "add_s", 0x0000C0A0, 0x0000FFE0, ARC_OPCODE_ARC32, ARITH, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
+
+/* aex b,c 00100bbb00100111RBBBCCCCCCRRRRRR. */
+{ "aex", 0x20270000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* aex<.cc> b,c 00100bbb11100111RBBBCCCCCC0QQQQQ. */
+{ "aex", 0x20E70000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* aex b,u6 00100bbb01100111RBBBuuuuuuRRRRRR. */
+{ "aex", 0x20670000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* aex<.cc> b,u6 00100bbb11100111RBBBuuuuuu1QQQQQ. */
+{ "aex", 0x20E70020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
+
+/* aex b,s12 00100bbb10100111RBBBssssssSSSSSS. */
+{ "aex", 0x20A70000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* aex limm,c 0010011000100111R111CCCCCCRRRRRR. */
+{ "aex", 0x26277000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* aex b,limm 00100bbb00100111RBBB111110RRRRRR. */
+{ "aex", 0x20270F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* aex<.cc> limm,c 0010011011100111R111CCCCCC0QQQQQ. */
+{ "aex", 0x26E77000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* aex<.cc> b,limm 00100bbb11100111RBBB1111100QQQQQ. */
+{ "aex", 0x20E70F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { C_CC }},
+
+/* aex limm,u6 0010011001100111R111uuuuuuRRRRRR. */
+{ "aex", 0x26677000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* aex<.cc> limm,u6 0010011011100111R111uuuuuu1QQQQQ. */
+{ "aex", 0x26E77020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
+
+/* aex limm,s12 0010011010100111R111ssssssSSSSSS. */
+{ "aex", 0x26A77000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* aex limm,limm 0010011000100111R111111110RRRRRR. */
+{ "aex", 0x26277F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 }},
+
+/* aex<.cc> limm,limm 0010011011100111R1111111100QQQQQ. */
+{ "aex", 0x26E77F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_CC }},
+
+/* aexl RB,RC 01011bbb001001110BBBccccccRRRRRR. */
+{ "aexl", 0x58270000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* aexl<.cc> RB,RC 01011bbb111001110BBBcccccc0QQQQQ. */
+{ "aexl", 0x58E70000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* aexl RB,u6 01011bbb011001110BBBuuuuuuRRRRRR. */
+{ "aexl", 0x58670000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* aexl<.cc> RB,u6 01011bbb111001110BBBuuuuuu1QQQQQ. */
+{ "aexl", 0x58E70020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
+
+/* aexl RB,s12 01011bbb101001110BBBssssssSSSSSS. */
+{ "aexl", 0x58A70000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* aexl RB,ximm 01011bbb001001110BBB111100RRRRRR. */
+{ "aexl", 0x58270F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, XIMM, BRAKETdup }, { 0 }},
+
+/* aexl<.cc> RB,ximm 01011bbb111001110BBB1111000QQQQQ. */
+{ "aexl", 0x58E70F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, XIMM, BRAKETdup }, { C_CC }},
+
+/* aexl RB,limm 01011bbb001001110BBB111110RRRRRR. */
+{ "aexl", 0x58270F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* aexl<.cc> RB,limm 01011bbb111001110BBB1111100QQQQQ. */
+{ "aexl", 0x58E70F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_CC }},
+
+/* and<.f> a,b,c 00100bbb00000100FBBBCCCCCCAAAAAA. */
+{ "and", 0x20040000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* and<.f> 0,b,c 00100bbb00000100FBBBCCCCCC111110. */
+{ "and", 0x2004003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* and<.f><.cc> b,b,c 00100bbb11000100FBBBCCCCCC0QQQQQ. */
+{ "and", 0x20C40000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* and<.f> a,b,u6 00100bbb01000100FBBBuuuuuuAAAAAA. */
+{ "and", 0x20440000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* and<.f> 0,b,u6 00100bbb01000100FBBBuuuuuu111110. */
+{ "and", 0x2044003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* and<.f><.cc> b,b,u6 00100bbb11000100FBBBuuuuuu1QQQQQ. */
+{ "and", 0x20C40020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* and<.f> b,b,s12 00100bbb10000100FBBBssssssSSSSSS. */
+{ "and", 0x20840000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* and<.f> a,limm,c 0010011000000100F111CCCCCCAAAAAA. */
+{ "and", 0x26047000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* and<.f> a,b,limm 00100bbb00000100FBBB111110AAAAAA. */
+{ "and", 0x20040F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* and<.f> 0,limm,c 0010011000000100F111CCCCCC111110. */
+{ "and", 0x2604703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* and<.f> 0,b,limm 00100bbb00000100FBBB111110111110. */
+{ "and", 0x20040FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* and<.f><.cc> b,b,limm 00100bbb11000100FBBB1111100QQQQQ. */
+{ "and", 0x20C40F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* and<.f><.cc> 0,limm,c 0010011011000100F111CCCCCC0QQQQQ. */
+{ "and", 0x26C47000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* and<.f> a,limm,u6 0010011001000100F111uuuuuuAAAAAA. */
+{ "and", 0x26447000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* and<.f> 0,limm,u6 0010011001000100F111uuuuuu111110. */
+{ "and", 0x2644703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* and<.f><.cc> 0,limm,u6 0010011011000100F111uuuuuu1QQQQQ. */
+{ "and", 0x26C47020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* and<.f> 0,limm,s12 0010011010000100F111ssssssSSSSSS. */
+{ "and", 0x26847000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* and<.f> a,limm,limm 0010011000000100F111111110AAAAAA. */
+{ "and", 0x26047F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* and<.f> 0,limm,limm 0010011000000100F111111110111110. */
+{ "and", 0x26047FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* and<.f><.cc> 0,limm,limm 0010011011000100F1111111100QQQQQ. */
+{ "and", 0x26C47F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* andl<.f> RA,RB,RC 01011bbb00000100FBBBccccccaaaaaa. */
+{ "andl", 0x58040000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* andl<.f> 0,RB,RC 01011bbb00000100FBBBcccccc111110. */
+{ "andl", 0x5804003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* andl<.f><.cc> RB,RB,RC 01011bbb11000100FBBBcccccc0QQQQQ. */
+{ "andl", 0x58C40000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* andl<.f> RA,RB,u6 01011bbb01000100FBBBuuuuuuaaaaaa. */
+{ "andl", 0x58440000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* andl<.f> 0,RB,u6 01011bbb01000100FBBBuuuuuu111110. */
+{ "andl", 0x5844003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* andl<.f><.cc> RB,RB,u6 01011bbb11000100FBBBuuuuuu1QQQQQ. */
+{ "andl", 0x58C40020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* andl<.f> RB,RB,s12 01011bbb10000100FBBBssssssSSSSSS. */
+{ "andl", 0x58840000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* andl<.f> RA,ximm,RC 0101110000000100F111ccccccaaaaaa. */
+{ "andl", 0x5C047000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* andl<.f> RA,RB,ximm 01011bbb00000100FBBB111100aaaaaa. */
+{ "andl", 0x58040F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* andl<.f> 0,ximm,RC 0101110000000100F111cccccc111110. */
+{ "andl", 0x5C04703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* andl<.f> 0,RB,ximm 01011bbb00000100FBBB111100111110. */
+{ "andl", 0x58040F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* andl<.f><.cc> 0,ximm,RC 0101110011000100F111cccccc0QQQQQ. */
+{ "andl", 0x5CC47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* andl<.f><.cc> RB,RB,ximm 01011bbb11000100FBBB1111000QQQQQ. */
+{ "andl", 0x58C40F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* andl<.f> RA,ximm,u6 0101110001000100F111uuuuuuaaaaaa. */
+{ "andl", 0x5C447000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* andl<.f> 0,ximm,u6 0101110001000100F111uuuuuu111110. */
+{ "andl", 0x5C44703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* andl<.f><.cc> 0,ximm,u6 0101110011000100F111uuuuuu1QQQQQ. */
+{ "andl", 0x5CC47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* andl<.f> RA,limm,RC 0101111000000100F111ccccccaaaaaa. */
+{ "andl", 0x5E047000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* andl<.f> RA,RB,limm 01011bbb00000100FBBB111110aaaaaa. */
+{ "andl", 0x58040F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* andl<.f> 0,limm,RC 0101111000000100F111cccccc111110. */
+{ "andl", 0x5E04703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* andl<.f> 0,RB,limm 01011bbb00000100FBBB111110111110. */
+{ "andl", 0x58040FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* andl<.f><.cc> 0,limm,RC 0101111011000100F111cccccc0QQQQQ. */
+{ "andl", 0x5EC47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* andl<.f><.cc> RB,RB,limm 01011bbb11000100FBBB1111100QQQQQ. */
+{ "andl", 0x58C40F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* andl<.f> RA,limm,u6 0101111001000100F111uuuuuuaaaaaa. */
+{ "andl", 0x5E447000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* andl<.f> 0,limm,u6 0101111001000100F111uuuuuu111110. */
+{ "andl", 0x5E44703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* andl<.f><.cc> 0,limm,u6 0101111011000100F111uuuuuu1QQQQQ. */
+{ "andl", 0x5EC47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* andl<.f> 0,ximm,s12 0101110010000100F111ssssssSSSSSS. */
+{ "andl", 0x5C847000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* andl<.f> 0,limm,s12 0101111010000100F111ssssssSSSSSS. */
+{ "andl", 0x5E847000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* andl<.f> RA,ximm,ximm 0101110000000100F111111100aaaaaa. */
+{ "andl", 0x5C047F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* andl<.f> 0,ximm,ximm 0101110000000100F111111100111110. */
+{ "andl", 0x5C047F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* andl<.f><.cc> 0,ximm,ximm 0101110011000100F1111111000QQQQQ. */
+{ "andl", 0x5CC47F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* andl<.f> RA,limm,limm 0101111000000100F111111110aaaaaa. */
+{ "andl", 0x5E047F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* andl<.f> 0,limm,limm 0101111000000100F111111110111110. */
+{ "andl", 0x5E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* andl<.f><.cc> 0,limm,limm 0101111011000100F1111111100QQQQQ. */
+{ "andl", 0x5EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* andl_s b,b,c 01111bbbccc01000. */
+{ "andl_s", 0x00007808, 0x0000F81F, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* and_s b,b,c 01111bbbccc00100. */
+{ "and_s", 0x00007804, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* asl<.f> b,c 00100bbb00101111FBBBCCCCCC000000. */
+{ "asl", 0x202F0000, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* asl<.f> 0,c 0010011000101111F111CCCCCC000000. */
+{ "asl", 0x262F7000, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* asl<.f> a,b,c 00101bbb00000000FBBBCCCCCCAAAAAA. */
+{ "asl", 0x28000000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* asl<.f> 0,b,c 00101bbb00000000FBBBCCCCCC111110. */
+{ "asl", 0x2800003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* asl<.f><.cc> b,b,c 00101bbb11000000FBBBCCCCCC0QQQQQ. */
+{ "asl", 0x28C00000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asl<.f> b,u6 00100bbb01101111FBBBuuuuuu000000. */
+{ "asl", 0x206F0000, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* asl<.f> 0,u6 0010011001101111F111uuuuuu000000. */
+{ "asl", 0x266F7000, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* asl<.f> a,b,u6 00101bbb01000000FBBBuuuuuuAAAAAA. */
+{ "asl", 0x28400000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asl<.f> 0,b,u6 00101bbb01000000FBBBuuuuuu111110. */
+{ "asl", 0x2840003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asl<.f><.cc> b,b,u6 00101bbb11000000FBBBuuuuuu1QQQQQ. */
+{ "asl", 0x28C00020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asl<.f> b,b,s12 00101bbb10000000FBBBssssssSSSSSS. */
+{ "asl", 0x28800000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asl<.f> b,limm 00100bbb00101111FBBB111110000000. */
+{ "asl", 0x202F0F80, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* asl<.f> 0,limm 0010011000101111F111111110000000. */
+{ "asl", 0x262F7F80, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* asl<.f> a,limm,c 0010111000000000F111CCCCCCAAAAAA. */
+{ "asl", 0x2E007000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* asl<.f> a,b,limm 00101bbb00000000FBBB111110AAAAAA. */
+{ "asl", 0x28000F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* asl<.f> 0,limm,c 0010111000000000F111CCCCCC111110. */
+{ "asl", 0x2E00703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* asl<.f> 0,b,limm 00101bbb00000000FBBB111110111110. */
+{ "asl", 0x28000FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* asl<.f><.cc> b,b,limm 00101bbb11000000FBBB1111100QQQQQ. */
+{ "asl", 0x28C00F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asl<.f><.cc> 0,limm,c 0010111011000000F111CCCCCC0QQQQQ. */
+{ "asl", 0x2EC07000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asl<.f> a,limm,u6 0010111001000000F111uuuuuuAAAAAA. */
+{ "asl", 0x2E407000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asl<.f> 0,limm,u6 0010111001000000F111uuuuuu111110. */
+{ "asl", 0x2E40703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asl<.f><.cc> 0,limm,u6 0010111011000000F111uuuuuu1QQQQQ. */
+{ "asl", 0x2EC07020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asl<.f> 0,limm,s12 0010111010000000F111ssssssSSSSSS. */
+{ "asl", 0x2E807000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asl<.f> a,limm,limm 0010111000000000F111111110AAAAAA. */
+{ "asl", 0x2E007F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asl<.f> 0,limm,limm 0010111000000000F111111110111110. */
+{ "asl", 0x2E007FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asl<.f><.cc> 0,limm,limm 0010111011000000F1111111100QQQQQ. */
+{ "asl", 0x2EC07F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asll<.f> RA,RB,RC 01011bbb00100000FBBBccccccaaaaaa. */
+{ "asll", 0x58200000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* asll<.f> 0,RB,RC 01011bbb00100000FBBBcccccc111110. */
+{ "asll", 0x5820003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asll<.f><.cc> RB,RB,RC 01011bbb11100000FBBBcccccc0QQQQQ. */
+{ "asll", 0x58E00000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asll<.f> RB,RC 01011bbb00101111FBBBcccccc000000. */
+{ "asll", 0x582F0000, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* asll<.f> 0,RC 0101111000101111F111cccccc000000. */
+{ "asll", 0x5E2F7000, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* asll<.f> RA,RB,u6 01011bbb01100000FBBBuuuuuuaaaaaa. */
+{ "asll", 0x58600000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asll<.f> 0,RB,u6 01011bbb01100000FBBBuuuuuu111110. */
+{ "asll", 0x5860003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asll<.f><.cc> RB,RB,u6 01011bbb11100000FBBBuuuuuu1QQQQQ. */
+{ "asll", 0x58E00020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asll<.f> RB,u6 01011bbb01101111FBBBuuuuuu000000. */
+{ "asll", 0x586F0000, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* asll<.f> 0,u6 0101111001101111F111uuuuuu000000. */
+{ "asll", 0x5E6F7000, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* asll<.f> RB,RB,s12 01011bbb10100000FBBBssssssSSSSSS. */
+{ "asll", 0x58A00000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asll<.f> RA,ximm,RC 0101110000100000F111ccccccaaaaaa. */
+{ "asll", 0x5C207000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* asll<.f> RA,RB,ximm 01011bbb00100000FBBB111100aaaaaa. */
+{ "asll", 0x58200F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* asll<.f> 0,ximm,RC 0101110000100000F111cccccc111110. */
+{ "asll", 0x5C20703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* asll<.f> 0,RB,ximm 01011bbb00100000FBBB111100111110. */
+{ "asll", 0x58200F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* asll<.f><.cc> 0,ximm,RC 0101110011100000F111cccccc0QQQQQ. */
+{ "asll", 0x5CE07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* asll<.f><.cc> RB,RB,ximm 01011bbb11100000FBBB1111000QQQQQ. */
+{ "asll", 0x58E00F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* asll<.f> RB,ximm 01011bbb00101111FBBB111100000000. */
+{ "asll", 0x582F0F00, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* asll<.f> 0,ximm 0101111000101111F111111100000000. */
+{ "asll", 0x5E2F7F00, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* asll<.f> RA,ximm,u6 0101110001100000F111uuuuuuaaaaaa. */
+{ "asll", 0x5C607000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* asll<.f> 0,ximm,u6 0101110001100000F111uuuuuu111110. */
+{ "asll", 0x5C60703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* asll<.f><.cc> 0,ximm,u6 0101110011100000F111uuuuuu1QQQQQ. */
+{ "asll", 0x5CE07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asll<.f> RA,limm,RC 0101111000100000F111ccccccaaaaaa. */
+{ "asll", 0x5E207000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asll<.f> RA,RB,limm 01011bbb00100000FBBB111110aaaaaa. */
+{ "asll", 0x58200F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asll<.f> 0,limm,RC 0101111000100000F111cccccc111110. */
+{ "asll", 0x5E20703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asll<.f> 0,RB,limm 01011bbb00100000FBBB111110111110. */
+{ "asll", 0x58200FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asll<.f><.cc> 0,limm,RC 0101111011100000F111cccccc0QQQQQ. */
+{ "asll", 0x5EE07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asll<.f><.cc> RB,RB,limm 01011bbb11100000FBBB1111100QQQQQ. */
+{ "asll", 0x58E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asll<.f> RB,limm 01011bbb00101111FBBB111110000000. */
+{ "asll", 0x582F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* asll<.f> 0,limm 0101111000101111F111111110000000. */
+{ "asll", 0x5E2F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* asll<.f> RA,limm,u6 0101111001100000F111uuuuuuaaaaaa. */
+{ "asll", 0x5E607000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asll<.f> 0,limm,u6 0101111001100000F111uuuuuu111110. */
+{ "asll", 0x5E60703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asll<.f><.cc> 0,limm,u6 0101111011100000F111uuuuuu1QQQQQ. */
+{ "asll", 0x5EE07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asll<.f> 0,ximm,s12 0101110010100000F111ssssssSSSSSS. */
+{ "asll", 0x5CA07000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* asll<.f> 0,limm,s12 0101111010100000F111ssssssSSSSSS. */
+{ "asll", 0x5EA07000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asll<.f> RA,ximm,ximm 0101110000100000F111111100aaaaaa. */
+{ "asll", 0x5C207F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* asll<.f> 0,ximm,ximm 0101110000100000F111111100111110. */
+{ "asll", 0x5C207F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* asll<.f><.cc> 0,ximm,ximm 0101110011100000F1111111000QQQQQ. */
+{ "asll", 0x5CE07F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* asll<.f> RA,limm,limm 0101111000100000F111111110aaaaaa. */
+{ "asll", 0x5E207F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asll<.f> 0,limm,limm 0101111000100000F111111110111110. */
+{ "asll", 0x5E207FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asll<.f><.cc> 0,limm,limm 0101111011100000F1111111100QQQQQ. */
+{ "asll", 0x5EE07F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asl_s b,c 01111bbbccc11011. */
+{ "asl_s", 0x0000781B, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* asl_s b,b,c 01111bbbccc11000. */
+{ "asl_s", 0x00007818, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* asl_s b,b,u5 10111bbb000uuuuu. */
+{ "asl_s", 0x0000B800, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* asr<.f> b,c 00100bbb00101111FBBBCCCCCC000001. */
+{ "asr", 0x202F0001, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* asr<.f> 0,c 0010011000101111F111CCCCCC000001. */
+{ "asr", 0x262F7001, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* asr<.f> a,b,c 00101bbb00000010FBBBCCCCCCAAAAAA. */
+{ "asr", 0x28020000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* asr<.f> 0,b,c 00101bbb00000010FBBBCCCCCC111110. */
+{ "asr", 0x2802003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* asr<.f><.cc> b,b,c 00101bbb11000010FBBBCCCCCC0QQQQQ. */
+{ "asr", 0x28C20000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asr<.f> b,u6 00100bbb01101111FBBBuuuuuu000001. */
+{ "asr", 0x206F0001, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* asr<.f> 0,u6 0010011001101111F111uuuuuu000001. */
+{ "asr", 0x266F7001, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* asr<.f> a,b,u6 00101bbb01000010FBBBuuuuuuAAAAAA. */
+{ "asr", 0x28420000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asr<.f> 0,b,u6 00101bbb01000010FBBBuuuuuu111110. */
+{ "asr", 0x2842003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asr<.f><.cc> b,b,u6 00101bbb11000010FBBBuuuuuu1QQQQQ. */
+{ "asr", 0x28C20020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asr<.f> b,b,s12 00101bbb10000010FBBBssssssSSSSSS. */
+{ "asr", 0x28820000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asr<.f> b,limm 00100bbb00101111FBBB111110000001. */
+{ "asr", 0x202F0F81, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* asr<.f> 0,limm 0010011000101111F111111110000001. */
+{ "asr", 0x262F7F81, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* asr<.f> a,limm,c 0010111000000010F111CCCCCCAAAAAA. */
+{ "asr", 0x2E027000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* asr<.f> a,b,limm 00101bbb00000010FBBB111110AAAAAA. */
+{ "asr", 0x28020F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* asr<.f> 0,limm,c 0010111000000010F111CCCCCC111110. */
+{ "asr", 0x2E02703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* asr<.f> 0,b,limm 00101bbb00000010FBBB111110111110. */
+{ "asr", 0x28020FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* asr<.f><.cc> b,b,limm 00101bbb11000010FBBB1111100QQQQQ. */
+{ "asr", 0x28C20F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asr<.f><.cc> 0,limm,c 0010111011000010F111CCCCCC0QQQQQ. */
+{ "asr", 0x2EC27000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asr<.f> a,limm,u6 0010111001000010F111uuuuuuAAAAAA. */
+{ "asr", 0x2E427000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asr<.f> 0,limm,u6 0010111001000010F111uuuuuu111110. */
+{ "asr", 0x2E42703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asr<.f><.cc> 0,limm,u6 0010111011000010F111uuuuuu1QQQQQ. */
+{ "asr", 0x2EC27020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asr<.f> 0,limm,s12 0010111010000010F111ssssssSSSSSS. */
+{ "asr", 0x2E827000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asr<.f> a,limm,limm 0010111000000010F111111110AAAAAA. */
+{ "asr", 0x2E027F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asr<.f> 0,limm,limm 0010111000000010F111111110111110. */
+{ "asr", 0x2E027FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asr<.f><.cc> 0,limm,limm 0010111011000010F1111111100QQQQQ. */
+{ "asr", 0x2EC27F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asr16<.f> b,c 00101bbb00101111FBBBCCCCCC001100. */
+{ "asr16", 0x282F000C, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* asr16<.f> 0,c 0010111000101111F111CCCCCC001100. */
+{ "asr16", 0x2E2F700C, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* asr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001100. */
+{ "asr16", 0x286F000C, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* asr16<.f> 0,u6 0010111001101111F111uuuuuu001100. */
+{ "asr16", 0x2E6F700C, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* asr16<.f> b,limm 00101bbb00101111FBBB111110001100. */
+{ "asr16", 0x282F0F8C, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* asr16<.f> 0,limm 0010111000101111F111111110001100. */
+{ "asr16", 0x2E2F7F8C, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* asr8<.f> b,c 00101bbb00101111FBBBCCCCCC001101. */
+{ "asr8", 0x282F000D, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* asr8<.f> 0,c 0010111000101111F111CCCCCC001101. */
+{ "asr8", 0x2E2F700D, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* asr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001101. */
+{ "asr8", 0x286F000D, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* asr8<.f> 0,u6 0010111001101111F111uuuuuu001101. */
+{ "asr8", 0x2E6F700D, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* asr8<.f> b,limm 00101bbb00101111FBBB111110001101. */
+{ "asr8", 0x282F0F8D, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* asr8<.f> 0,limm 0010111000101111F111111110001101. */
+{ "asr8", 0x2E2F7F8D, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* asrl<.f> RA,RB,RC 01011bbb00100010FBBBccccccaaaaaa. */
+{ "asrl", 0x58220000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* asrl<.f> 0,RB,RC 01011bbb00100010FBBBcccccc111110. */
+{ "asrl", 0x5822003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asrl<.f><.cc> RB,RB,RC 01011bbb11100010FBBBcccccc0QQQQQ. */
+{ "asrl", 0x58E20000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asrl<.f> RB,RC 01011bbb00101111FBBBcccccc000001. */
+{ "asrl", 0x582F0001, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* asrl<.f> 0,RC 0101111000101111F111cccccc000001. */
+{ "asrl", 0x5E2F7001, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* asrl<.f> RA,RB,u6 01011bbb01100010FBBBuuuuuuaaaaaa. */
+{ "asrl", 0x58620000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asrl<.f> 0,RB,u6 01011bbb01100010FBBBuuuuuu111110. */
+{ "asrl", 0x5862003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asrl<.f><.cc> RB,RB,u6 01011bbb11100010FBBBuuuuuu1QQQQQ. */
+{ "asrl", 0x58E20020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrl<.f> RB,u6 01011bbb01101111FBBBuuuuuu000001. */
+{ "asrl", 0x586F0001, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* asrl<.f> 0,u6 0101111001101111F111uuuuuu000001. */
+{ "asrl", 0x5E6F7001, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* asrl<.f> RB,RB,s12 01011bbb10100010FBBBssssssSSSSSS. */
+{ "asrl", 0x58A20000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asrl<.f> RA,ximm,RC 0101110000100010F111ccccccaaaaaa. */
+{ "asrl", 0x5C227000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* asrl<.f> RA,RB,ximm 01011bbb00100010FBBB111100aaaaaa. */
+{ "asrl", 0x58220F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* asrl<.f> 0,ximm,RC 0101110000100010F111cccccc111110. */
+{ "asrl", 0x5C22703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* asrl<.f> 0,RB,ximm 01011bbb00100010FBBB111100111110. */
+{ "asrl", 0x58220F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* asrl<.f><.cc> 0,ximm,RC 0101110011100010F111cccccc0QQQQQ. */
+{ "asrl", 0x5CE27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* asrl<.f><.cc> RB,RB,ximm 01011bbb11100010FBBB1111000QQQQQ. */
+{ "asrl", 0x58E20F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* asrl<.f> RB,ximm 01011bbb00101111FBBB111100000001. */
+{ "asrl", 0x582F0F01, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* asrl<.f> 0,ximm 0101111000101111F111111100000001. */
+{ "asrl", 0x5E2F7F01, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* asrl<.f> RA,ximm,u6 0101110001100010F111uuuuuuaaaaaa. */
+{ "asrl", 0x5C627000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* asrl<.f> 0,ximm,u6 0101110001100010F111uuuuuu111110. */
+{ "asrl", 0x5C62703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* asrl<.f><.cc> 0,ximm,u6 0101110011100010F111uuuuuu1QQQQQ. */
+{ "asrl", 0x5CE27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrl<.f> RA,limm,RC 0101111000100010F111ccccccaaaaaa. */
+{ "asrl", 0x5E227000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asrl<.f> RA,RB,limm 01011bbb00100010FBBB111110aaaaaa. */
+{ "asrl", 0x58220F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asrl<.f> 0,limm,RC 0101111000100010F111cccccc111110. */
+{ "asrl", 0x5E22703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asrl<.f> 0,RB,limm 01011bbb00100010FBBB111110111110. */
+{ "asrl", 0x58220FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asrl<.f><.cc> 0,limm,RC 0101111011100010F111cccccc0QQQQQ. */
+{ "asrl", 0x5EE27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asrl<.f><.cc> RB,RB,limm 01011bbb11100010FBBB1111100QQQQQ. */
+{ "asrl", 0x58E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asrl<.f> RB,limm 01011bbb00101111FBBB111110000001. */
+{ "asrl", 0x582F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* asrl<.f> 0,limm 0101111000101111F111111110000001. */
+{ "asrl", 0x5E2F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* asrl<.f> RA,limm,u6 0101111001100010F111uuuuuuaaaaaa. */
+{ "asrl", 0x5E627000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrl<.f> 0,limm,u6 0101111001100010F111uuuuuu111110. */
+{ "asrl", 0x5E62703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrl<.f><.cc> 0,limm,u6 0101111011100010F111uuuuuu1QQQQQ. */
+{ "asrl", 0x5EE27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrl<.f> 0,ximm,s12 0101110010100010F111ssssssSSSSSS. */
+{ "asrl", 0x5CA27000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* asrl<.f> 0,limm,s12 0101111010100010F111ssssssSSSSSS. */
+{ "asrl", 0x5EA27000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asrl<.f> RA,ximm,ximm 0101110000100010F111111100aaaaaa. */
+{ "asrl", 0x5C227F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* asrl<.f> 0,ximm,ximm 0101110000100010F111111100111110. */
+{ "asrl", 0x5C227F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* asrl<.f><.cc> 0,ximm,ximm 0101110011100010F1111111000QQQQQ. */
+{ "asrl", 0x5CE27F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* asrl<.f> RA,limm,limm 0101111000100010F111111110aaaaaa. */
+{ "asrl", 0x5E227F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asrl<.f> 0,limm,limm 0101111000100010F111111110111110. */
+{ "asrl", 0x5E227FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asrl<.f><.cc> 0,limm,limm 0101111011100010F1111111100QQQQQ. */
+{ "asrl", 0x5EE27F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asr_s b,c 01111bbbccc11100. */
+{ "asr_s", 0x0000781C, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* asr_s b,b,c 01111bbbccc11010. */
+{ "asr_s", 0x0000781A, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* asr_s b,b,u5 10111bbb010uuuuu. */
+{ "asr_s", 0x0000B840, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* atld<.op><.aq> RB,RC 00100bbb00101111FBBBcccccc110OOO. */
+{ "atld", 0x202F0030, 0xF8FF0038, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_ATOP, C_AQ, C_RL }},
+
+/* atldl_add<.aq> RB,RC 01011bbb00101111FBBBcccccc110000. */
+{ "atldl", 0x582F0030, 0xF8FF0038, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_ATOP, C_AQ, C_RL }},
+
+/* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
+{ "b", 0x00010000, 0xF8010000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM25_A16_5 }, { C_D }},
+
+/* b<.d><cc> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ. */
+{ "b", 0x00000000, 0xF8010000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM21_A16_5 }, { C_CC, C_D }},
+
+/* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00110. */
+{ "bbit0", 0x08010006, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT0, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* bbit0<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10110. */
+{ "bbit0", 0x08010016, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT0, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* bbit0 b,limm,s9 00001bbbsssssss1SBBB111110000110. */
+{ "bbit0", 0x08010F86, 0xF8010FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT0, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0 limm,c,s9 00001110sssssss1S111CCCCCC000110. */
+{ "bbit0", 0x0E017006, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0 limm,u6,s9 00001110sssssss1S111uuuuuu010110. */
+{ "bbit0", 0x0E017016, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0 limm,limm,s9 00001110sssssss1S111111110000110. */
+{ "bbit0", 0x0E017F86, 0xFF017FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0l<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110. */
+{ "bbit0l", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* bbit0l<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11110. */
+{ "bbit0l", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* bbit0l b,limm,s9 00001bbbsssssss1SBBB111110001110. */
+{ "bbit0l", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0l limm,c,s9 00001110sssssss1S111CCCCCC001110. */
+{ "bbit0l", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0l limm,u6,s9 00001110sssssss1S111uuuuuu011110. */
+{ "bbit0l", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0l limm,limm,s9 00001110sssssss1S111111110001110. */
+{ "bbit0l", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00111. */
+{ "bbit1", 0x08010007, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT1, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* bbit1<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10111. */
+{ "bbit1", 0x08010017, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT1, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* bbit1 b,limm,s9 00001bbbsssssss1SBBB111110000111. */
+{ "bbit1", 0x08010F87, 0xF8010FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT1, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1 limm,c,s9 00001110sssssss1S111CCCCCC000111. */
+{ "bbit1", 0x0E017007, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1 limm,u6,s9 00001110sssssss1S111uuuuuu010111. */
+{ "bbit1", 0x0E017017, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1 limm,limm,s9 00001110sssssss1S111111110000111. */
+{ "bbit1", 0x0E017F87, 0xFF017FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1l<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01111. */
+{ "bbit1l", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* bbit1l<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11111. */
+{ "bbit1l", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* bbit1l b,limm,s9 00001bbbsssssss1SBBB111110001111. */
+{ "bbit1l", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1l limm,c,s9 00001110sssssss1S111CCCCCC001111. */
+{ "bbit1l", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1l limm,u6,s9 00001110sssssss1S111uuuuuu011111. */
+{ "bbit1l", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1l limm,limm,s9 00001110sssssss1S111111110001111. */
+{ "bbit1l", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+
+/* bclr<.f> a,b,c 00100bbb00010000FBBBCCCCCCAAAAAA. */
+{ "bclr", 0x20100000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bclr<.f> 0,b,c 00100bbb00010000FBBBCCCCCC111110. */
+{ "bclr", 0x2010003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bclr<.f><.cc> b,b,c 00100bbb11010000FBBBCCCCCC0QQQQQ. */
+{ "bclr", 0x20D00000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bclr<.f> a,b,u6 00100bbb01010000FBBBuuuuuuAAAAAA. */
+{ "bclr", 0x20500000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bclr<.f> 0,b,u6 00100bbb01010000FBBBuuuuuu111110. */
+{ "bclr", 0x2050003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bclr<.f><.cc> b,b,u6 00100bbb11010000FBBBuuuuuu1QQQQQ. */
+{ "bclr", 0x20D00020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclr<.f> b,b,s12 00100bbb10010000FBBBssssssSSSSSS. */
+{ "bclr", 0x20900000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bclr<.f> a,limm,c 0010011000010000F111CCCCCCAAAAAA. */
+{ "bclr", 0x26107000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bclr<.f> a,b,limm 00100bbb00010000FBBB111110AAAAAA. */
+{ "bclr", 0x20100F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bclr<.f> 0,limm,c 0010011000010000F111CCCCCC111110. */
+{ "bclr", 0x2610703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bclr<.f> 0,b,limm 00100bbb00010000FBBB111110111110. */
+{ "bclr", 0x20100FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bclr<.f><.cc> b,b,limm 00100bbb11010000FBBB1111100QQQQQ. */
+{ "bclr", 0x20D00F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bclr<.f><.cc> 0,limm,c 0010011011010000F111CCCCCC0QQQQQ. */
+{ "bclr", 0x26D07000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bclr<.f> a,limm,u6 0010011001010000F111uuuuuuAAAAAA. */
+{ "bclr", 0x26507000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bclr<.f> 0,limm,u6 0010011001010000F111uuuuuu111110. */
+{ "bclr", 0x2650703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bclr<.f><.cc> 0,limm,u6 0010011011010000F111uuuuuu1QQQQQ. */
+{ "bclr", 0x26D07020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclr<.f> 0,limm,s12 0010011010010000F111ssssssSSSSSS. */
+{ "bclr", 0x26907000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bclr<.f> a,limm,limm 0010011000010000F111111110AAAAAA. */
+{ "bclr", 0x26107F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bclr<.f> 0,limm,limm 0010011000010000F111111110111110. */
+{ "bclr", 0x26107FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bclr<.f><.cc> 0,limm,limm 0010011011010000F1111111100QQQQQ. */
+{ "bclr", 0x26D07F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,RB,RC 01011bbb00010000FBBBccccccaaaaaa. */
+{ "bclrl", 0x58100000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bclrl<.f> 0,RB,RC 01011bbb00010000FBBBcccccc111110. */
+{ "bclrl", 0x5810003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bclrl<.f><.cc> RB,RB,RC 01011bbb11010000FBBBcccccc0QQQQQ. */
+{ "bclrl", 0x58D00000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,RB,u6 01011bbb01010000FBBBuuuuuuaaaaaa. */
+{ "bclrl", 0x58500000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f> 0,RB,u6 01011bbb01010000FBBBuuuuuu111110. */
+{ "bclrl", 0x5850003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f><.cc> RB,RB,u6 01011bbb11010000FBBBuuuuuu1QQQQQ. */
+{ "bclrl", 0x58D00020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclrl<.f> RB,RB,s12 01011bbb10010000FBBBssssssSSSSSS. */
+{ "bclrl", 0x58900000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bclrl<.f> RA,ximm,RC 0101110000010000F111ccccccaaaaaa. */
+{ "bclrl", 0x5C107000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bclrl<.f> RA,RB,ximm 01011bbb00010000FBBB111100aaaaaa. */
+{ "bclrl", 0x58100F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bclrl<.f> 0,ximm,RC 0101110000010000F111cccccc111110. */
+{ "bclrl", 0x5C10703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bclrl<.f> 0,RB,ximm 01011bbb00010000FBBB111100111110. */
+{ "bclrl", 0x58100F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bclrl<.f><.cc> 0,ximm,RC 0101110011010000F111cccccc0QQQQQ. */
+{ "bclrl", 0x5CD07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bclrl<.f><.cc> RB,RB,ximm 01011bbb11010000FBBB1111000QQQQQ. */
+{ "bclrl", 0x58D00F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,ximm,u6 0101110001010000F111uuuuuuaaaaaa. */
+{ "bclrl", 0x5C507000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f> 0,ximm,u6 0101110001010000F111uuuuuu111110. */
+{ "bclrl", 0x5C50703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f><.cc> 0,ximm,u6 0101110011010000F111uuuuuu1QQQQQ. */
+{ "bclrl", 0x5CD07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,limm,RC 0101111000010000F111ccccccaaaaaa. */
+{ "bclrl", 0x5E107000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bclrl<.f> RA,RB,limm 01011bbb00010000FBBB111110aaaaaa. */
+{ "bclrl", 0x58100F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bclrl<.f> 0,limm,RC 0101111000010000F111cccccc111110. */
+{ "bclrl", 0x5E10703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bclrl<.f> 0,RB,limm 01011bbb00010000FBBB111110111110. */
+{ "bclrl", 0x58100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bclrl<.f><.cc> 0,limm,RC 0101111011010000F111cccccc0QQQQQ. */
+{ "bclrl", 0x5ED07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bclrl<.f><.cc> RB,RB,limm 01011bbb11010000FBBB1111100QQQQQ. */
+{ "bclrl", 0x58D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,limm,u6 0101111001010000F111uuuuuuaaaaaa. */
+{ "bclrl", 0x5E507000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f> 0,limm,u6 0101111001010000F111uuuuuu111110. */
+{ "bclrl", 0x5E50703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f><.cc> 0,limm,u6 0101111011010000F111uuuuuu1QQQQQ. */
+{ "bclrl", 0x5ED07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclrl<.f> 0,ximm,s12 0101110010010000F111ssssssSSSSSS. */
+{ "bclrl", 0x5C907000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bclrl<.f> 0,limm,s12 0101111010010000F111ssssssSSSSSS. */
+{ "bclrl", 0x5E907000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bclrl<.f> RA,ximm,ximm 0101110000010000F111111100aaaaaa. */
+{ "bclrl", 0x5C107F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bclrl<.f> 0,ximm,ximm 0101110000010000F111111100111110. */
+{ "bclrl", 0x5C107F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bclrl<.f><.cc> 0,ximm,ximm 0101110011010000F1111111000QQQQQ. */
+{ "bclrl", 0x5CD07F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,limm,limm 0101111000010000F111111110aaaaaa. */
+{ "bclrl", 0x5E107F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bclrl<.f> 0,limm,limm 0101111000010000F111111110111110. */
+{ "bclrl", 0x5E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bclrl<.f><.cc> 0,limm,limm 0101111011010000F1111111100QQQQQ. */
+{ "bclrl", 0x5ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bclr_s b,b,u5 10111bbb101uuuuu. */
+{ "bclr_s", 0x0000B8A0, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* beq_sCC_EQ s10 1111001sssssssss. */
+{ "beq_s", 0x0000F200, 0x0000FE00,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM10_A16_7_S }, { C_CC_EQ }},
+
+/* bge_sCC_GE s7 1111011001ssssss. */
+{ "bge_s", 0x0000F640, 0x0000FFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_GE }},
+
+/* bgt_sCC_GT s7 1111011000ssssss. */
+{ "bgt_s", 0x0000F600, 0x0000FFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_GT }},
+
+/* bhi_sCC_HI s7 1111011100ssssss. */
+{ "bhi_s", 0x0000F700, 0x0000FFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_HI }},
+
+/* bhs_sCC_HS s7 1111011101ssssss. */
+{ "bhs_s", 0x0000F740, 0x0000FFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_HS }},
+
+/* bi c 00100RRR001001000RRRCCCCCCRRRRRR. */
+{ "bi", 0x20240000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BI, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* bi limm 00100RRR001001000RRR111110RRRRRR. */
+{ "bi", 0x20240F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BI, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* bic<.f> a,b,c 00100bbb00000110FBBBCCCCCCAAAAAA. */
+{ "bic", 0x20060000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bic<.f> 0,b,c 00100bbb00000110FBBBCCCCCC111110. */
+{ "bic", 0x2006003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bic<.f><.cc> b,b,c 00100bbb11000110FBBBCCCCCC0QQQQQ. */
+{ "bic", 0x20C60000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bic<.f> a,b,u6 00100bbb01000110FBBBuuuuuuAAAAAA. */
+{ "bic", 0x20460000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bic<.f> 0,b,u6 00100bbb01000110FBBBuuuuuu111110. */
+{ "bic", 0x2046003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bic<.f><.cc> b,b,u6 00100bbb11000110FBBBuuuuuu1QQQQQ. */
+{ "bic", 0x20C60020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bic<.f> b,b,s12 00100bbb10000110FBBBssssssSSSSSS. */
+{ "bic", 0x20860000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bic<.f> a,limm,c 0010011000000110F111CCCCCCAAAAAA. */
+{ "bic", 0x26067000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bic<.f> a,b,limm 00100bbb00000110FBBB111110AAAAAA. */
+{ "bic", 0x20060F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bic<.f> 0,limm,c 0010011000000110F111CCCCCC111110. */
+{ "bic", 0x2606703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bic<.f> 0,b,limm 00100bbb00000110FBBB111110111110. */
+{ "bic", 0x20060FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bic<.f><.cc> b,b,limm 00100bbb11000110FBBB1111100QQQQQ. */
+{ "bic", 0x20C60F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bic<.f><.cc> 0,limm,c 0010011011000110F111CCCCCC0QQQQQ. */
+{ "bic", 0x26C67000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bic<.f> a,limm,u6 0010011001000110F111uuuuuuAAAAAA. */
+{ "bic", 0x26467000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bic<.f> 0,limm,u6 0010011001000110F111uuuuuu111110. */
+{ "bic", 0x2646703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bic<.f><.cc> 0,limm,u6 0010011011000110F111uuuuuu1QQQQQ. */
+{ "bic", 0x26C67020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bic<.f> 0,limm,s12 0010011010000110F111ssssssSSSSSS. */
+{ "bic", 0x26867000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bic<.f> a,limm,limm 0010011000000110F111111110AAAAAA. */
+{ "bic", 0x26067F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bic<.f> 0,limm,limm 0010011000000110F111111110111110. */
+{ "bic", 0x26067FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bic<.f><.cc> 0,limm,limm 0010011011000110F1111111100QQQQQ. */
+{ "bic", 0x26C67F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bicl<.f> RA,RB,RC 01011bbb00000110FBBBccccccaaaaaa. */
+{ "bicl", 0x58060000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bicl<.f> 0,RB,RC 01011bbb00000110FBBBcccccc111110. */
+{ "bicl", 0x5806003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bicl<.f><.cc> RB,RB,RC 01011bbb11000110FBBBcccccc0QQQQQ. */
+{ "bicl", 0x58C60000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bicl<.f> RA,RB,u6 01011bbb01000110FBBBuuuuuuaaaaaa. */
+{ "bicl", 0x58460000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bicl<.f> 0,RB,u6 01011bbb01000110FBBBuuuuuu111110. */
+{ "bicl", 0x5846003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bicl<.f><.cc> RB,RB,u6 01011bbb11000110FBBBuuuuuu1QQQQQ. */
+{ "bicl", 0x58C60020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bicl<.f> RB,RB,s12 01011bbb10000110FBBBssssssSSSSSS. */
+{ "bicl", 0x58860000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bicl<.f> RA,ximm,RC 0101110000000110F111ccccccaaaaaa. */
+{ "bicl", 0x5C067000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bicl<.f> RA,RB,ximm 01011bbb00000110FBBB111100aaaaaa. */
+{ "bicl", 0x58060F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bicl<.f> 0,ximm,RC 0101110000000110F111cccccc111110. */
+{ "bicl", 0x5C06703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bicl<.f> 0,RB,ximm 01011bbb00000110FBBB111100111110. */
+{ "bicl", 0x58060F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bicl<.f><.cc> 0,ximm,RC 0101110011000110F111cccccc0QQQQQ. */
+{ "bicl", 0x5CC67000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bicl<.f><.cc> RB,RB,ximm 01011bbb11000110FBBB1111000QQQQQ. */
+{ "bicl", 0x58C60F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bicl<.f> RA,ximm,u6 0101110001000110F111uuuuuuaaaaaa. */
+{ "bicl", 0x5C467000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bicl<.f> 0,ximm,u6 0101110001000110F111uuuuuu111110. */
+{ "bicl", 0x5C46703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bicl<.f><.cc> 0,ximm,u6 0101110011000110F111uuuuuu1QQQQQ. */
+{ "bicl", 0x5CC67020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bicl<.f> RA,limm,RC 0101111000000110F111ccccccaaaaaa. */
+{ "bicl", 0x5E067000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bicl<.f> RA,RB,limm 01011bbb00000110FBBB111110aaaaaa. */
+{ "bicl", 0x58060F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bicl<.f> 0,limm,RC 0101111000000110F111cccccc111110. */
+{ "bicl", 0x5E06703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bicl<.f> 0,RB,limm 01011bbb00000110FBBB111110111110. */
+{ "bicl", 0x58060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bicl<.f><.cc> 0,limm,RC 0101111011000110F111cccccc0QQQQQ. */
+{ "bicl", 0x5EC67000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bicl<.f><.cc> RB,RB,limm 01011bbb11000110FBBB1111100QQQQQ. */
+{ "bicl", 0x58C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bicl<.f> RA,limm,u6 0101111001000110F111uuuuuuaaaaaa. */
+{ "bicl", 0x5E467000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bicl<.f> 0,limm,u6 0101111001000110F111uuuuuu111110. */
+{ "bicl", 0x5E46703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bicl<.f><.cc> 0,limm,u6 0101111011000110F111uuuuuu1QQQQQ. */
+{ "bicl", 0x5EC67020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bicl<.f> 0,ximm,s12 0101110010000110F111ssssssSSSSSS. */
+{ "bicl", 0x5C867000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bicl<.f> 0,limm,s12 0101111010000110F111ssssssSSSSSS. */
+{ "bicl", 0x5E867000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bicl<.f> RA,ximm,ximm 0101110000000110F111111100aaaaaa. */
+{ "bicl", 0x5C067F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bicl<.f> 0,ximm,ximm 0101110000000110F111111100111110. */
+{ "bicl", 0x5C067F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bicl<.f><.cc> 0,ximm,ximm 0101110011000110F1111111000QQQQQ. */
+{ "bicl", 0x5CC67F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bicl<.f> RA,limm,limm 0101111000000110F111111110aaaaaa. */
+{ "bicl", 0x5E067F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bicl<.f> 0,limm,limm 0101111000000110F111111110111110. */
+{ "bicl", 0x5E067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bicl<.f><.cc> 0,limm,limm 0101111011000110F1111111100QQQQQ. */
+{ "bicl", 0x5EC67F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bic_s b,b,c 01111bbbccc00110. */
+{ "bic_s", 0x00007806, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* bih c 00100RRR001001010RRRCCCCCCRRRRRR. */
+{ "bih", 0x20250000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BIH, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* bih limm 00100RRR001001010RRR111110RRRRRR. */
+{ "bih", 0x20250F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BIH, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
+{ "bl", 0x08020000, 0xF8030000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM25_A32_5 }, { C_D }},
+
+/* bl<.d><.cc> s21 00001sssssssss00SSSSSSSSSSNQQQQQ. */
+{ "bl", 0x08000000, 0xF8030000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM21_A32_5 }, { C_CC, C_D }},
+
+/* ble_sCC_LE s7 1111011011ssssss. */
+{ "ble_s", 0x0000F6C0, 0x0000FFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LE }},
+
+/* blo_sCC_LO s7 1111011110ssssss. */
+{ "blo_s", 0x0000F780, 0x0000FFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LO }},
+
+/* bls_sCC_LS s7 1111011111ssssss. */
+{ "bls_s", 0x0000F7C0, 0x0000FFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LS }},
+
+/* blt_sCC_LT s7 1111011010ssssss. */
+{ "blt_s", 0x0000F680, 0x0000FFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LT }},
+
+/* bl_s s13 11111sssssssssss. */
+{ "bl_s", 0x0000F800, 0x0000F800,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM13_A32_5_S }, { 0 }},
+
+/* bl_s LIMM 01111 011 111 00000. */
+{ "bl_s", 0x7BE0, 0xFFFF, ARC_OPCODE_ARC64, BRANCH, NONE, { LIMM34 }, { 0 }},
+
+/* bmsk<.f> a,b,c 00100bbb00010011FBBBCCCCCCAAAAAA. */
+{ "bmsk", 0x20130000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bmsk<.f> 0,b,c 00100bbb00010011FBBBCCCCCC111110. */
+{ "bmsk", 0x2013003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bmsk<.f><.cc> b,b,c 00100bbb11010011FBBBCCCCCC0QQQQQ. */
+{ "bmsk", 0x20D30000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bmsk<.f> a,b,u6 00100bbb01010011FBBBuuuuuuAAAAAA. */
+{ "bmsk", 0x20530000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f> 0,b,u6 00100bbb01010011FBBBuuuuuu111110. */
+{ "bmsk", 0x2053003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f><.cc> b,b,u6 00100bbb11010011FBBBuuuuuu1QQQQQ. */
+{ "bmsk", 0x20D30020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsk<.f> b,b,s12 00100bbb10010011FBBBssssssSSSSSS. */
+{ "bmsk", 0x20930000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bmsk<.f> a,limm,c 0010011000010011F111CCCCCCAAAAAA. */
+{ "bmsk", 0x26137000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bmsk<.f> a,b,limm 00100bbb00010011FBBB111110AAAAAA. */
+{ "bmsk", 0x20130F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bmsk<.f> 0,limm,c 0010011000010011F111CCCCCC111110. */
+{ "bmsk", 0x2613703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bmsk<.f> 0,b,limm 00100bbb00010011FBBB111110111110. */
+{ "bmsk", 0x20130FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bmsk<.f><.cc> b,b,limm 00100bbb11010011FBBB1111100QQQQQ. */
+{ "bmsk", 0x20D30F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bmsk<.f><.cc> 0,limm,c 0010011011010011F111CCCCCC0QQQQQ. */
+{ "bmsk", 0x26D37000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bmsk<.f> a,limm,u6 0010011001010011F111uuuuuuAAAAAA. */
+{ "bmsk", 0x26537000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f> 0,limm,u6 0010011001010011F111uuuuuu111110. */
+{ "bmsk", 0x2653703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f><.cc> 0,limm,u6 0010011011010011F111uuuuuu1QQQQQ. */
+{ "bmsk", 0x26D37020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsk<.f> 0,limm,s12 0010011010010011F111ssssssSSSSSS. */
+{ "bmsk", 0x26937000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bmsk<.f> a,limm,limm 0010011000010011F111111110AAAAAA. */
+{ "bmsk", 0x26137F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bmsk<.f> 0,limm,limm 0010011000010011F111111110111110. */
+{ "bmsk", 0x26137FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bmsk<.f><.cc> 0,limm,limm 0010011011010011F1111111100QQQQQ. */
+{ "bmsk", 0x26D37F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,RB,RC 01011bbb00010011FBBBccccccaaaaaa. */
+{ "bmskl", 0x58130000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bmskl<.f> 0,RB,RC 01011bbb00010011FBBBcccccc111110. */
+{ "bmskl", 0x5813003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bmskl<.f><.cc> RB,RB,RC 01011bbb11010011FBBBcccccc0QQQQQ. */
+{ "bmskl", 0x58D30000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,RB,u6 01011bbb01010011FBBBuuuuuuaaaaaa. */
+{ "bmskl", 0x58530000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f> 0,RB,u6 01011bbb01010011FBBBuuuuuu111110. */
+{ "bmskl", 0x5853003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f><.cc> RB,RB,u6 01011bbb11010011FBBBuuuuuu1QQQQQ. */
+{ "bmskl", 0x58D30020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskl<.f> RB,RB,s12 01011bbb10010011FBBBssssssSSSSSS. */
+{ "bmskl", 0x58930000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bmskl<.f> RA,ximm,RC 0101110000010011F111ccccccaaaaaa. */
+{ "bmskl", 0x5C137000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bmskl<.f> RA,RB,ximm 01011bbb00010011FBBB111100aaaaaa. */
+{ "bmskl", 0x58130F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bmskl<.f> 0,ximm,RC 0101110000010011F111cccccc111110. */
+{ "bmskl", 0x5C13703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bmskl<.f> 0,RB,ximm 01011bbb00010011FBBB111100111110. */
+{ "bmskl", 0x58130F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bmskl<.f><.cc> 0,ximm,RC 0101110011010011F111cccccc0QQQQQ. */
+{ "bmskl", 0x5CD37000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bmskl<.f><.cc> RB,RB,ximm 01011bbb11010011FBBB1111000QQQQQ. */
+{ "bmskl", 0x58D30F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,ximm,u6 0101110001010011F111uuuuuuaaaaaa. */
+{ "bmskl", 0x5C537000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f> 0,ximm,u6 0101110001010011F111uuuuuu111110. */
+{ "bmskl", 0x5C53703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f><.cc> 0,ximm,u6 0101110011010011F111uuuuuu1QQQQQ. */
+{ "bmskl", 0x5CD37020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,limm,RC 0101111000010011F111ccccccaaaaaa. */
+{ "bmskl", 0x5E137000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bmskl<.f> RA,RB,limm 01011bbb00010011FBBB111110aaaaaa. */
+{ "bmskl", 0x58130F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bmskl<.f> 0,limm,RC 0101111000010011F111cccccc111110. */
+{ "bmskl", 0x5E13703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bmskl<.f> 0,RB,limm 01011bbb00010011FBBB111110111110. */
+{ "bmskl", 0x58130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bmskl<.f><.cc> 0,limm,RC 0101111011010011F111cccccc0QQQQQ. */
+{ "bmskl", 0x5ED37000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bmskl<.f><.cc> RB,RB,limm 01011bbb11010011FBBB1111100QQQQQ. */
+{ "bmskl", 0x58D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,limm,u6 0101111001010011F111uuuuuuaaaaaa. */
+{ "bmskl", 0x5E537000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f> 0,limm,u6 0101111001010011F111uuuuuu111110. */
+{ "bmskl", 0x5E53703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f><.cc> 0,limm,u6 0101111011010011F111uuuuuu1QQQQQ. */
+{ "bmskl", 0x5ED37020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskl<.f> 0,ximm,s12 0101110010010011F111ssssssSSSSSS. */
+{ "bmskl", 0x5C937000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bmskl<.f> 0,limm,s12 0101111010010011F111ssssssSSSSSS. */
+{ "bmskl", 0x5E937000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bmskl<.f> RA,ximm,ximm 0101110000010011F111111100aaaaaa. */
+{ "bmskl", 0x5C137F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bmskl<.f> 0,ximm,ximm 0101110000010011F111111100111110. */
+{ "bmskl", 0x5C137F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bmskl<.f><.cc> 0,ximm,ximm 0101110011010011F1111111000QQQQQ. */
+{ "bmskl", 0x5CD37F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,limm,limm 0101111000010011F111111110aaaaaa. */
+{ "bmskl", 0x5E137F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bmskl<.f> 0,limm,limm 0101111000010011F111111110111110. */
+{ "bmskl", 0x5E137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bmskl<.f><.cc> 0,limm,limm 0101111011010011F1111111100QQQQQ. */
+{ "bmskl", 0x5ED37F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bmskn<.f> a,b,c 00100bbb00101100FBBBCCCCCCAAAAAA. */
+{ "bmskn", 0x202C0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bmskn<.f> 0,b,c 00100bbb00101100FBBBCCCCCC111110. */
+{ "bmskn", 0x202C003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bmskn<.f><.cc> b,b,c 00100bbb11101100FBBBCCCCCC0QQQQQ. */
+{ "bmskn", 0x20EC0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bmskn<.f> a,b,u6 00100bbb01101100FBBBuuuuuuAAAAAA. */
+{ "bmskn", 0x206C0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f> 0,b,u6 00100bbb01101100FBBBuuuuuu111110. */
+{ "bmskn", 0x206C003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f><.cc> b,b,u6 00100bbb11101100FBBBuuuuuu1QQQQQ. */
+{ "bmskn", 0x20EC0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskn<.f> b,b,s12 00100bbb10101100FBBBssssssSSSSSS. */
+{ "bmskn", 0x20AC0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bmskn<.f> a,limm,c 0010011000101100F111CCCCCCAAAAAA. */
+{ "bmskn", 0x262C7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bmskn<.f> a,b,limm 00100bbb00101100FBBB111110AAAAAA. */
+{ "bmskn", 0x202C0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bmskn<.f> 0,limm,c 0010011000101100F111CCCCCC111110. */
+{ "bmskn", 0x262C703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bmskn<.f> 0,b,limm 00100bbb00101100FBBB111110111110. */
+{ "bmskn", 0x202C0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bmskn<.f><.cc> b,b,limm 00100bbb11101100FBBB1111100QQQQQ. */
+{ "bmskn", 0x20EC0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bmskn<.f><.cc> 0,limm,c 0010011011101100F111CCCCCC0QQQQQ. */
+{ "bmskn", 0x26EC7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bmskn<.f> a,limm,u6 0010011001101100F111uuuuuuAAAAAA. */
+{ "bmskn", 0x266C7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f> 0,limm,u6 0010011001101100F111uuuuuu111110. */
+{ "bmskn", 0x266C703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f><.cc> 0,limm,u6 0010011011101100F111uuuuuu1QQQQQ. */
+{ "bmskn", 0x26EC7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskn<.f> 0,limm,s12 0010011010101100F111ssssssSSSSSS. */
+{ "bmskn", 0x26AC7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bmskn<.f> a,limm,limm 0010011000101100F111111110AAAAAA. */
+{ "bmskn", 0x262C7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bmskn<.f> 0,limm,limm 0010011000101100F111111110111110. */
+{ "bmskn", 0x262C7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bmskn<.f><.cc> 0,limm,limm 0010011011101100F1111111100QQQQQ. */
+{ "bmskn", 0x26EC7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,RB,RC 01011bbb00101100FBBBccccccaaaaaa. */
+{ "bmsknl", 0x582C0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bmsknl<.f> 0,RB,RC 01011bbb00101100FBBBcccccc111110. */
+{ "bmsknl", 0x582C003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bmsknl<.f><.cc> RB,RB,RC 01011bbb11101100FBBBcccccc0QQQQQ. */
+{ "bmsknl", 0x58EC0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,RB,u6 01011bbb01101100FBBBuuuuuuaaaaaa. */
+{ "bmsknl", 0x586C0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f> 0,RB,u6 01011bbb01101100FBBBuuuuuu111110. */
+{ "bmsknl", 0x586C003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f><.cc> RB,RB,u6 01011bbb11101100FBBBuuuuuu1QQQQQ. */
+{ "bmsknl", 0x58EC0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsknl<.f> RB,RB,s12 01011bbb10101100FBBBssssssSSSSSS. */
+{ "bmsknl", 0x58AC0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bmsknl<.f> RA,ximm,RC 0101110000101100F111ccccccaaaaaa. */
+{ "bmsknl", 0x5C2C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bmsknl<.f> RA,RB,ximm 01011bbb00101100FBBB111100aaaaaa. */
+{ "bmsknl", 0x582C0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bmsknl<.f> 0,ximm,RC 0101110000101100F111cccccc111110. */
+{ "bmsknl", 0x5C2C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bmsknl<.f> 0,RB,ximm 01011bbb00101100FBBB111100111110. */
+{ "bmsknl", 0x582C0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,ximm,RC 0101110011101100F111cccccc0QQQQQ. */
+{ "bmsknl", 0x5CEC7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bmsknl<.f><.cc> RB,RB,ximm 01011bbb11101100FBBB1111000QQQQQ. */
+{ "bmsknl", 0x58EC0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,ximm,u6 0101110001101100F111uuuuuuaaaaaa. */
+{ "bmsknl", 0x5C6C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f> 0,ximm,u6 0101110001101100F111uuuuuu111110. */
+{ "bmsknl", 0x5C6C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,ximm,u6 0101110011101100F111uuuuuu1QQQQQ. */
+{ "bmsknl", 0x5CEC7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,limm,RC 0101111000101100F111ccccccaaaaaa. */
+{ "bmsknl", 0x5E2C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bmsknl<.f> RA,RB,limm 01011bbb00101100FBBB111110aaaaaa. */
+{ "bmsknl", 0x582C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bmsknl<.f> 0,limm,RC 0101111000101100F111cccccc111110. */
+{ "bmsknl", 0x5E2C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bmsknl<.f> 0,RB,limm 01011bbb00101100FBBB111110111110. */
+{ "bmsknl", 0x582C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,limm,RC 0101111011101100F111cccccc0QQQQQ. */
+{ "bmsknl", 0x5EEC7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bmsknl<.f><.cc> RB,RB,limm 01011bbb11101100FBBB1111100QQQQQ. */
+{ "bmsknl", 0x58EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,limm,u6 0101111001101100F111uuuuuuaaaaaa. */
+{ "bmsknl", 0x5E6C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f> 0,limm,u6 0101111001101100F111uuuuuu111110. */
+{ "bmsknl", 0x5E6C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,limm,u6 0101111011101100F111uuuuuu1QQQQQ. */
+{ "bmsknl", 0x5EEC7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsknl<.f> 0,ximm,s12 0101110010101100F111ssssssSSSSSS. */
+{ "bmsknl", 0x5CAC7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bmsknl<.f> 0,limm,s12 0101111010101100F111ssssssSSSSSS. */
+{ "bmsknl", 0x5EAC7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bmsknl<.f> RA,ximm,ximm 0101110000101100F111111100aaaaaa. */
+{ "bmsknl", 0x5C2C7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bmsknl<.f> 0,ximm,ximm 0101110000101100F111111100111110. */
+{ "bmsknl", 0x5C2C7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,ximm,ximm 0101110011101100F1111111000QQQQQ. */
+{ "bmsknl", 0x5CEC7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,limm,limm 0101111000101100F111111110aaaaaa. */
+{ "bmsknl", 0x5E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bmsknl<.f> 0,limm,limm 0101111000101100F111111110111110. */
+{ "bmsknl", 0x5E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,limm,limm 0101111011101100F1111111100QQQQQ. */
+{ "bmsknl", 0x5EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bmsk_s b,b,u5 10111bbb110uuuuu. */
+{ "bmsk_s", 0x0000B8C0, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* bne_sCC_NE s10 1111010sssssssss. */
+{ "bne_s", 0x0000F400, 0x0000FE00,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM10_A16_7_S }, { C_CC_NE }},
+
+/* breq<.d>CC_EQ b,c,s9 00001bbbsssssss1SBBBCCCCCCN00000. */
+{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_EQ }},
+
+/* breq<.d>CC_EQ b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10000. */
+{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_EQ }},
+
+/* breqCC_EQ b,limm,s9 00001bbbsssssss1SBBB111110000000. */
+{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_EQ }},
+
+/* breqCC_EQ limm,c,s9 00001110sssssss1S111CCCCCC000000. */
+{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_EQ }},
+
+/* breqCC_EQ limm,u6,s9 00001110sssssss1S111uuuuuu010000. */
+{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_EQ }},
+
+/* breqCC_EQ limm,limm,s9 00001110sssssss1S111111110000000. */
+{ "breq", 0x0E017F80, 0xFF017FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_EQ }},
+
+/* breql<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01000. */
+{ "breql", 0x08010008, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* breql<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11000. */
+{ "breql", 0x08010018, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* breql b,ximm,s9 00001bbbsssssss1SBBB111100001000. */
+{ "breql", 0x08010F08, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 }},
+
+/* breql ximm,c,s9 00001100sssssss1S111CCCCCC001000. */
+{ "breql", 0x0C017008, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* breql ximm,u6,s9 00001100sssssss1S111uuuuuu011000. */
+{ "breql", 0x0C017018, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* breql b,limm,s9 00001bbbsssssss1SBBB111110001000. */
+{ "breql", 0x08010F88, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* breql limm,c,s9 00001110sssssss1S111CCCCCC001000. */
+{ "breql", 0x0E017008, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* breql limm,u6,s9 00001110sssssss1S111uuuuuu011000. */
+{ "breql", 0x0E017018, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* breql_s b,0,s8 11101bbb0sssssss. */
+{ "breql_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC64, BRCC, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
+
+/* breq_s b,0,s8 11101bbb0sssssss. */
+{ "breq_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC32, BRCC, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
+
+/* brge<.d>CC_GE b,c,s9 00001bbbsssssss1SBBBCCCCCCN00011. */
+{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_GE }},
+
+/* brge<.d>CC_GE b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10011. */
+{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_GE }},
+
+/* brgeCC_GE b,limm,s9 00001bbbsssssss1SBBB111110000011. */
+{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_GE }},
+
+/* brgeCC_GE limm,c,s9 00001110sssssss1S111CCCCCC000011. */
+{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_GE }},
+
+/* brgeCC_GE limm,u6,s9 00001110sssssss1S111uuuuuu010011. */
+{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_GE }},
+
+/* brgeCC_GE limm,limm,s9 00001110sssssss1S111111110000011. */
+{ "brge", 0x0E017F83, 0xFF017FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_GE }},
+
+/* brgel<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01011. */
+{ "brgel", 0x0801000B, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brgel<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11011. */
+{ "brgel", 0x0801001B, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brgel b,ximm,s9 00001bbbsssssss1SBBB111100001011. */
+{ "brgel", 0x08010F0B, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brgel ximm,c,s9 00001100sssssss1S111CCCCCC001011. */
+{ "brgel", 0x0C01700B, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brgel ximm,u6,s9 00001100sssssss1S111uuuuuu011011. */
+{ "brgel", 0x0C01701B, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brgel b,limm,s9 00001bbbsssssss1SBBB111110001011. */
+{ "brgel", 0x08010F8B, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brgel limm,c,s9 00001110sssssss1S111CCCCCC001011. */
+{ "brgel", 0x0E01700B, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brgel limm,u6,s9 00001110sssssss1S111uuuuuu011011. */
+{ "brgel", 0x0E01701B, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brhs<.d>CC_HS b,c,s9 00001bbbsssssss1SBBBCCCCCCN00101. */
+{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_HS }},
+
+/* brhs<.d>CC_HS b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10101. */
+{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_HS }},
+
+/* brhsCC_HS b,limm,s9 00001bbbsssssss1SBBB111110000101. */
+{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_HS }},
+
+/* brhsCC_HS limm,c,s9 00001110sssssss1S111CCCCCC000101. */
+{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_HS }},
+
+/* brhsCC_HS limm,u6,s9 00001110sssssss1S111uuuuuu010101. */
+{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_HS }},
+
+/* brhsCC_HS limm,limm,s9 00001110sssssss1S111111110000101. */
+{ "brhs", 0x0E017F85, 0xFF017FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_HS }},
+
+/* brhsl<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01101. */
+{ "brhsl", 0x0801000D, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brhsl<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11101. */
+{ "brhsl", 0x0801001D, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brhsl b,ximm,s9 00001bbbsssssss1SBBB111100001101. */
+{ "brhsl", 0x08010F0D, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brhsl ximm,c,s9 00001100sssssss1S111CCCCCC001101. */
+{ "brhsl", 0x0C01700D, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brhsl ximm,u6,s9 00001100sssssss1S111uuuuuu011101. */
+{ "brhsl", 0x0C01701D, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brhsl b,limm,s9 00001bbbsssssss1SBBB111110001101. */
+{ "brhsl", 0x08010F8D, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brhsl limm,c,s9 00001110sssssss1S111CCCCCC001101. */
+{ "brhsl", 0x0E01700D, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brhsl limm,u6,s9 00001110sssssss1S111uuuuuu011101. */
+{ "brhsl", 0x0E01701D, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brk 00100101011011110000000000111111. */
+{ "brk", 0x256F003F, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* brk_s 0111111111111111. */
+{ "brk_s", 0x00007FFF, 0x0000FFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* brlo<.d>CC_LO b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100. */
+{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LO }},
+
+/* brlo<.d>CC_LO b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10100. */
+{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LO }},
+
+/* brloCC_LO b,limm,s9 00001bbbsssssss1SBBB111110000100. */
+{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LO }},
+
+/* brloCC_LO limm,c,s9 00001110sssssss1S111CCCCCC000100. */
+{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LO }},
+
+/* brloCC_LO limm,u6,s9 00001110sssssss1S111uuuuuu010100. */
+{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LO }},
+
+/* brloCC_LO limm,limm,s9 00001110sssssss1S111111110000100. */
+{ "brlo", 0x0E017F84, 0xFF017FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_LO }},
+
+/* brlol<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01100. */
+{ "brlol", 0x0801000C, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brlol<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11100. */
+{ "brlol", 0x0801001C, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brlol b,ximm,s9 00001bbbsssssss1SBBB111100001100. */
+{ "brlol", 0x08010F0C, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brlol ximm,c,s9 00001100sssssss1S111CCCCCC001100. */
+{ "brlol", 0x0C01700C, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brlol ximm,u6,s9 00001100sssssss1S111uuuuuu011100. */
+{ "brlol", 0x0C01701C, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brlol b,limm,s9 00001bbbsssssss1SBBB111110001100. */
+{ "brlol", 0x08010F8C, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brlol limm,c,s9 00001110sssssss1S111CCCCCC001100. */
+{ "brlol", 0x0E01700C, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brlol limm,u6,s9 00001110sssssss1S111uuuuuu011100. */
+{ "brlol", 0x0E01701C, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brlt<.d>CC_LT b,c,s9 00001bbbsssssss1SBBBCCCCCCN00010. */
+{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LT }},
+
+/* brlt<.d>CC_LT b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10010. */
+{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LT }},
+
+/* brltCC_LT b,limm,s9 00001bbbsssssss1SBBB111110000010. */
+{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LT }},
+
+/* brltCC_LT limm,c,s9 00001110sssssss1S111CCCCCC000010. */
+{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LT }},
+
+/* brltCC_LT limm,u6,s9 00001110sssssss1S111uuuuuu010010. */
+{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LT }},
+
+/* brltCC_LT limm,limm,s9 00001110sssssss1S111111110000010. */
+{ "brlt", 0x0E017F82, 0xFF017FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_LT }},
+
+/* brltl<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01010. */
+{ "brltl", 0x0801000A, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brltl<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11010. */
+{ "brltl", 0x0801001A, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brltl b,ximm,s9 00001bbbsssssss1SBBB111100001010. */
+{ "brltl", 0x08010F0A, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brltl ximm,c,s9 00001100sssssss1S111CCCCCC001010. */
+{ "brltl", 0x0C01700A, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brltl ximm,u6,s9 00001100sssssss1S111uuuuuu011010. */
+{ "brltl", 0x0C01701A, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brltl b,limm,s9 00001bbbsssssss1SBBB111110001010. */
+{ "brltl", 0x08010F8A, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brltl limm,c,s9 00001110sssssss1S111CCCCCC001010. */
+{ "brltl", 0x0E01700A, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brltl limm,u6,s9 00001110sssssss1S111uuuuuu011010. */
+{ "brltl", 0x0E01701A, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brne<.d>CC_NE b,c,s9 00001bbbsssssss1SBBBCCCCCCN00001. */
+{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_NE }},
+
+/* brne<.d>CC_NE b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10001. */
+{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_NE }},
+
+/* brneCC_NE b,limm,s9 00001bbbsssssss1SBBB111110000001. */
+{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_NE }},
+
+/* brneCC_NE limm,c,s9 00001110sssssss1S111CCCCCC000001. */
+{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_NE }},
+
+/* brneCC_NE limm,u6,s9 00001110sssssss1S111uuuuuu010001. */
+{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_NE }},
+
+/* brneCC_NE limm,limm,s9 00001110sssssss1S111111110000001. */
+{ "brne", 0x0E017F81, 0xFF017FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_NE }},
+
+/* brnel<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01001. */
+{ "brnel", 0x08010009, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brnel<.d> b,u6,s9 00001bbbsssssss1SBBBUUUUUUN11001. */
+{ "brnel", 0x08010019, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brnel b,ximm,s9 00001bbbsssssss1SBBB111100001001. */
+{ "brnel", 0x08010F09, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, XIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brnel ximm,c,s9 00001100sssssss1S111CCCCCC001001. */
+{ "brnel", 0x0C017009, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brnel ximm,u6,s9 00001100sssssss1S111uuuuuu011001. */
+{ "brnel", 0x0C017019, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { XIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brnel b,limm,s9 00001bbbsssssss1SBBB111110001001. */
+{ "brnel", 0x08010F89, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brnel limm,c,s9 00001110sssssss1S111CCCCCC001001. */
+{ "brnel", 0x0E017009, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brnel limm,u6,s9 00001110sssssss1S111uuuuuu011001. */
+{ "brnel", 0x0E017019, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brnel_s b,0,s8 11101bbb1sssssss. */
+{ "brnel_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC64, BRCC, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
+
+/* brne_s b,0,s8 11101bbb1sssssss. */
+{ "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC32, BRCC, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
+
+/* bset<.f> a,b,c 00100bbb00001111FBBBCCCCCCAAAAAA. */
+{ "bset", 0x200F0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bset<.f> 0,b,c 00100bbb00001111FBBBCCCCCC111110. */
+{ "bset", 0x200F003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bset<.f><.cc> b,b,c 00100bbb11001111FBBBCCCCCC0QQQQQ. */
+{ "bset", 0x20CF0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bset<.f> a,b,u6 00100bbb01001111FBBBuuuuuuAAAAAA. */
+{ "bset", 0x204F0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bset<.f> 0,b,u6 00100bbb01001111FBBBuuuuuu111110. */
+{ "bset", 0x204F003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bset<.f><.cc> b,b,u6 00100bbb11001111FBBBuuuuuu1QQQQQ. */
+{ "bset", 0x20CF0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bset<.f> b,b,s12 00100bbb10001111FBBBssssssSSSSSS. */
+{ "bset", 0x208F0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bset<.f> a,limm,c 0010011000001111F111CCCCCCAAAAAA. */
+{ "bset", 0x260F7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bset<.f> a,b,limm 00100bbb00001111FBBB111110AAAAAA. */
+{ "bset", 0x200F0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bset<.f> 0,limm,c 0010011000001111F111CCCCCC111110. */
+{ "bset", 0x260F703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bset<.f> 0,b,limm 00100bbb00001111FBBB111110111110. */
+{ "bset", 0x200F0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bset<.f><.cc> b,b,limm 00100bbb11001111FBBB1111100QQQQQ. */
+{ "bset", 0x20CF0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bset<.f><.cc> 0,limm,c 0010011011001111F111CCCCCC0QQQQQ. */
+{ "bset", 0x26CF7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bset<.f> a,limm,u6 0010011001001111F111uuuuuuAAAAAA. */
+{ "bset", 0x264F7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bset<.f> 0,limm,u6 0010011001001111F111uuuuuu111110. */
+{ "bset", 0x264F703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bset<.f><.cc> 0,limm,u6 0010011011001111F111uuuuuu1QQQQQ. */
+{ "bset", 0x26CF7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bset<.f> 0,limm,s12 0010011010001111F111ssssssSSSSSS. */
+{ "bset", 0x268F7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bset<.f> a,limm,limm 0010011000001111F111111110AAAAAA. */
+{ "bset", 0x260F7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bset<.f> 0,limm,limm 0010011000001111F111111110111110. */
+{ "bset", 0x260F7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bset<.f><.cc> 0,limm,limm 0010011011001111F1111111100QQQQQ. */
+{ "bset", 0x26CF7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,RB,RC 01011bbb00001111FBBBccccccaaaaaa. */
+{ "bsetl", 0x580F0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bsetl<.f> 0,RB,RC 01011bbb00001111FBBBcccccc111110. */
+{ "bsetl", 0x580F003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bsetl<.f><.cc> RB,RB,RC 01011bbb11001111FBBBcccccc0QQQQQ. */
+{ "bsetl", 0x58CF0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,RB,u6 01011bbb01001111FBBBuuuuuuaaaaaa. */
+{ "bsetl", 0x584F0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f> 0,RB,u6 01011bbb01001111FBBBuuuuuu111110. */
+{ "bsetl", 0x584F003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f><.cc> RB,RB,u6 01011bbb11001111FBBBuuuuuu1QQQQQ. */
+{ "bsetl", 0x58CF0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bsetl<.f> RB,RB,s12 01011bbb10001111FBBBssssssSSSSSS. */
+{ "bsetl", 0x588F0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bsetl<.f> RA,ximm,RC 0101110000001111F111ccccccaaaaaa. */
+{ "bsetl", 0x5C0F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bsetl<.f> RA,RB,ximm 01011bbb00001111FBBB111100aaaaaa. */
+{ "bsetl", 0x580F0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bsetl<.f> 0,ximm,RC 0101110000001111F111cccccc111110. */
+{ "bsetl", 0x5C0F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bsetl<.f> 0,RB,ximm 01011bbb00001111FBBB111100111110. */
+{ "bsetl", 0x580F0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bsetl<.f><.cc> 0,ximm,RC 0101110011001111F111cccccc0QQQQQ. */
+{ "bsetl", 0x5CCF7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bsetl<.f><.cc> RB,RB,ximm 01011bbb11001111FBBB1111000QQQQQ. */
+{ "bsetl", 0x58CF0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,ximm,u6 0101110001001111F111uuuuuuaaaaaa. */
+{ "bsetl", 0x5C4F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f> 0,ximm,u6 0101110001001111F111uuuuuu111110. */
+{ "bsetl", 0x5C4F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f><.cc> 0,ximm,u6 0101110011001111F111uuuuuu1QQQQQ. */
+{ "bsetl", 0x5CCF7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,limm,RC 0101111000001111F111ccccccaaaaaa. */
+{ "bsetl", 0x5E0F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bsetl<.f> RA,RB,limm 01011bbb00001111FBBB111110aaaaaa. */
+{ "bsetl", 0x580F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bsetl<.f> 0,limm,RC 0101111000001111F111cccccc111110. */
+{ "bsetl", 0x5E0F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bsetl<.f> 0,RB,limm 01011bbb00001111FBBB111110111110. */
+{ "bsetl", 0x580F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bsetl<.f><.cc> 0,limm,RC 0101111011001111F111cccccc0QQQQQ. */
+{ "bsetl", 0x5ECF7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bsetl<.f><.cc> RB,RB,limm 01011bbb11001111FBBB1111100QQQQQ. */
+{ "bsetl", 0x58CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,limm,u6 0101111001001111F111uuuuuuaaaaaa. */
+{ "bsetl", 0x5E4F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f> 0,limm,u6 0101111001001111F111uuuuuu111110. */
+{ "bsetl", 0x5E4F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f><.cc> 0,limm,u6 0101111011001111F111uuuuuu1QQQQQ. */
+{ "bsetl", 0x5ECF7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bsetl<.f> 0,ximm,s12 0101110010001111F111ssssssSSSSSS. */
+{ "bsetl", 0x5C8F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bsetl<.f> 0,limm,s12 0101111010001111F111ssssssSSSSSS. */
+{ "bsetl", 0x5E8F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bsetl<.f> RA,ximm,ximm 0101110000001111F111111100aaaaaa. */
+{ "bsetl", 0x5C0F7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bsetl<.f> 0,ximm,ximm 0101110000001111F111111100111110. */
+{ "bsetl", 0x5C0F7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bsetl<.f><.cc> 0,ximm,ximm 0101110011001111F1111111000QQQQQ. */
+{ "bsetl", 0x5CCF7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,limm,limm 0101111000001111F111111110aaaaaa. */
+{ "bsetl", 0x5E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bsetl<.f> 0,limm,limm 0101111000001111F111111110111110. */
+{ "bsetl", 0x5E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bsetl<.f><.cc> 0,limm,limm 0101111011001111F1111111100QQQQQ. */
+{ "bsetl", 0x5ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bset_s b,b,u5 10111bbb100uuuuu. */
+{ "bset_s", 0x0000B880, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* btst b,c 00100bbb000100011BBBCCCCCCRRRRRR. */
+{ "btst", 0x20118000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { 0 }},
+
+/* btst<.cc> b,c 00100bbb110100011BBBCCCCCC0QQQQQ. */
+{ "btst", 0x20D18000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_CC }},
+
+/* btst b,u6 00100bbb010100011BBBuuuuuuRRRRRR. */
+{ "btst", 0x20518000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* btst<.cc> b,u6 00100bbb110100011BBBuuuuuu1QQQQQ. */
+{ "btst", 0x20D18020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* btst b,s12 00100bbb100100011BBBssssssSSSSSS. */
+{ "btst", 0x20918000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* btst limm,c 00100110000100011111CCCCCCRRRRRR. */
+{ "btst", 0x2611F000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, RC }, { 0 }},
+
+/* btst b,limm 00100bbb000100011BBB111110RRRRRR. */
+{ "btst", 0x20118F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { 0 }},
+
+/* btst<.cc> b,limm 00100bbb110100011BBB1111100QQQQQ. */
+{ "btst", 0x20D18F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_CC }},
+
+/* btst<.cc> limm,c 00100110110100011111CCCCCC0QQQQQ. */
+{ "btst", 0x26D1F000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, RC }, { C_CC }},
+
+/* btst limm,u6 00100110010100011111uuuuuuRRRRRR. */
+{ "btst", 0x2651F000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* btst<.cc> limm,u6 00100110110100011111uuuuuu1QQQQQ. */
+{ "btst", 0x26D1F020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* btst limm,s12 00100110100100011111ssssssSSSSSS. */
+{ "btst", 0x2691F000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* btst limm,limm 00100110000100011111111110RRRRRR. */
+{ "btst", 0x2611FF80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* btst<.cc> limm,limm 001001101101000111111111100QQQQQ. */
+{ "btst", 0x26D1FF80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* btstl RB,RC 01011bbb000100011BBBccccccRRRRRR. */
+{ "btstl", 0x58118000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* btstl<.cc> RB,RC 01011bbb110100011BBBcccccc0QQQQQ. */
+{ "btstl", 0x58D18000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* btstl RB,u6 01011bbb010100011BBBuuuuuuRRRRRR. */
+{ "btstl", 0x58518000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* btstl<.cc> RB,u6 01011bbb110100011BBBuuuuuu1QQQQQ. */
+{ "btstl", 0x58D18020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* btstl RB,s12 01011bbb100100011BBBssssssSSSSSS. */
+{ "btstl", 0x58918000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* btstl ximm,RC 01011100000100011111ccccccRRRRRR. */
+{ "btstl", 0x5C11F000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { XIMM, RC }, { 0 }},
+
+/* btstl RB,ximm 01011bbb000100011BBB111100RRRRRR. */
+{ "btstl", 0x58118F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 }},
+
+/* btstl<.cc> RB,ximm 01011bbb110100011BBB1111000QQQQQ. */
+{ "btstl", 0x58D18F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC }},
+
+/* btstl limm,RC 01011110000100011111ccccccRRRRRR. */
+{ "btstl", 0x5E11F000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* btstl RB,limm 01011bbb000100011BBB111110RRRRRR. */
+{ "btstl", 0x58118F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* btstl<.cc> RB,limm 01011bbb110100011BBB1111100QQQQQ. */
+{ "btstl", 0x58D18F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* btst_s b,u5 10111bbb111uuuuu. */
+{ "btst_s", 0x0000B8E0, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, UIMM5_11_S }, { 0 }},
+
+/* bxor<.f> a,b,c 00100bbb00010010FBBBCCCCCCAAAAAA. */
+{ "bxor", 0x20120000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bxor<.f> 0,b,c 00100bbb00010010FBBBCCCCCC111110. */
+{ "bxor", 0x2012003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bxor<.f><.cc> b,b,c 00100bbb11010010FBBBCCCCCC0QQQQQ. */
+{ "bxor", 0x20D20000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bxor<.f> a,b,u6 00100bbb01010010FBBBuuuuuuAAAAAA. */
+{ "bxor", 0x20520000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bxor<.f> 0,b,u6 00100bbb01010010FBBBuuuuuu111110. */
+{ "bxor", 0x2052003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bxor<.f><.cc> b,b,u6 00100bbb11010010FBBBuuuuuu1QQQQQ. */
+{ "bxor", 0x20D20020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxor<.f> b,b,s12 00100bbb10010010FBBBssssssSSSSSS. */
+{ "bxor", 0x20920000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bxor<.f> a,limm,c 0010011000010010F111CCCCCCAAAAAA. */
+{ "bxor", 0x26127000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bxor<.f> a,b,limm 00100bbb00010010FBBB111110AAAAAA. */
+{ "bxor", 0x20120F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bxor<.f> 0,limm,c 0010011000010010F111CCCCCC111110. */
+{ "bxor", 0x2612703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bxor<.f> 0,b,limm 00100bbb00010010FBBB111110111110. */
+{ "bxor", 0x20120FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bxor<.f><.cc> b,b,limm 00100bbb11010010FBBB1111100QQQQQ. */
+{ "bxor", 0x20D20F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bxor<.f><.cc> 0,limm,c 0010011011010010F111CCCCCC0QQQQQ. */
+{ "bxor", 0x26D27000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bxor<.f> a,limm,u6 0010011001010010F111uuuuuuAAAAAA. */
+{ "bxor", 0x26527000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bxor<.f> 0,limm,u6 0010011001010010F111uuuuuu111110. */
+{ "bxor", 0x2652703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bxor<.f><.cc> 0,limm,u6 0010011011010010F111uuuuuu1QQQQQ. */
+{ "bxor", 0x26D27020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxor<.f> 0,limm,s12 0010011010010010F111ssssssSSSSSS. */
+{ "bxor", 0x26927000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bxor<.f> a,limm,limm 0010011000010010F111111110AAAAAA. */
+{ "bxor", 0x26127F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bxor<.f> 0,limm,limm 0010011000010010F111111110111110. */
+{ "bxor", 0x26127FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bxor<.f><.cc> 0,limm,limm 0010011011010010F1111111100QQQQQ. */
+{ "bxor", 0x26D27F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,RB,RC 01011bbb00010010FBBBccccccaaaaaa. */
+{ "bxorl", 0x58120000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bxorl<.f> 0,RB,RC 01011bbb00010010FBBBcccccc111110. */
+{ "bxorl", 0x5812003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bxorl<.f><.cc> RB,RB,RC 01011bbb11010010FBBBcccccc0QQQQQ. */
+{ "bxorl", 0x58D20000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,RB,u6 01011bbb01010010FBBBuuuuuuaaaaaa. */
+{ "bxorl", 0x58520000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f> 0,RB,u6 01011bbb01010010FBBBuuuuuu111110. */
+{ "bxorl", 0x5852003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f><.cc> RB,RB,u6 01011bbb11010010FBBBuuuuuu1QQQQQ. */
+{ "bxorl", 0x58D20020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxorl<.f> RB,RB,s12 01011bbb10010010FBBBssssssSSSSSS. */
+{ "bxorl", 0x58920000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bxorl<.f> RA,ximm,RC 0101110000010010F111ccccccaaaaaa. */
+{ "bxorl", 0x5C127000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bxorl<.f> RA,RB,ximm 01011bbb00010010FBBB111100aaaaaa. */
+{ "bxorl", 0x58120F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bxorl<.f> 0,ximm,RC 0101110000010010F111cccccc111110. */
+{ "bxorl", 0x5C12703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bxorl<.f> 0,RB,ximm 01011bbb00010010FBBB111100111110. */
+{ "bxorl", 0x58120F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bxorl<.f><.cc> 0,ximm,RC 0101110011010010F111cccccc0QQQQQ. */
+{ "bxorl", 0x5CD27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bxorl<.f><.cc> RB,RB,ximm 01011bbb11010010FBBB1111000QQQQQ. */
+{ "bxorl", 0x58D20F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,ximm,u6 0101110001010010F111uuuuuuaaaaaa. */
+{ "bxorl", 0x5C527000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f> 0,ximm,u6 0101110001010010F111uuuuuu111110. */
+{ "bxorl", 0x5C52703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f><.cc> 0,ximm,u6 0101110011010010F111uuuuuu1QQQQQ. */
+{ "bxorl", 0x5CD27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,limm,RC 0101111000010010F111ccccccaaaaaa. */
+{ "bxorl", 0x5E127000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bxorl<.f> RA,RB,limm 01011bbb00010010FBBB111110aaaaaa. */
+{ "bxorl", 0x58120F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bxorl<.f> 0,limm,RC 0101111000010010F111cccccc111110. */
+{ "bxorl", 0x5E12703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bxorl<.f> 0,RB,limm 01011bbb00010010FBBB111110111110. */
+{ "bxorl", 0x58120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bxorl<.f><.cc> 0,limm,RC 0101111011010010F111cccccc0QQQQQ. */
+{ "bxorl", 0x5ED27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bxorl<.f><.cc> RB,RB,limm 01011bbb11010010FBBB1111100QQQQQ. */
+{ "bxorl", 0x58D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,limm,u6 0101111001010010F111uuuuuuaaaaaa. */
+{ "bxorl", 0x5E527000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f> 0,limm,u6 0101111001010010F111uuuuuu111110. */
+{ "bxorl", 0x5E52703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f><.cc> 0,limm,u6 0101111011010010F111uuuuuu1QQQQQ. */
+{ "bxorl", 0x5ED27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxorl<.f> 0,ximm,s12 0101110010010010F111ssssssSSSSSS. */
+{ "bxorl", 0x5C927000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bxorl<.f> 0,limm,s12 0101111010010010F111ssssssSSSSSS. */
+{ "bxorl", 0x5E927000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bxorl<.f> RA,ximm,ximm 0101110000010010F111111100aaaaaa. */
+{ "bxorl", 0x5C127F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bxorl<.f> 0,ximm,ximm 0101110000010010F111111100111110. */
+{ "bxorl", 0x5C127F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bxorl<.f><.cc> 0,ximm,ximm 0101110011010010F1111111000QQQQQ. */
+{ "bxorl", 0x5CD27F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,limm,limm 0101111000010010F111111110aaaaaa. */
+{ "bxorl", 0x5E127F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bxorl<.f> 0,limm,limm 0101111000010010F111111110111110. */
+{ "bxorl", 0x5E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bxorl<.f><.cc> 0,limm,limm 0101111011010010F1111111100QQQQQ. */
+{ "bxorl", 0x5ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* b_s s10 1111000sssssssss. */
+{ "b_s", 0x0000F000, 0x0000FE00,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 }},
+
+/* clri c 00100111001011110000CCCCCC111111. */
+{ "clri", 0x272F003F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { 0 }},
+
+/* clri u6 00100111011011110000uuuuuu111111. */
+{ "clri", 0x276F003F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* clri 00100111001011110000000000111111. */
+{ "clri", 0x276F003F, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* cmp b,c 00100bbb000011001BBBCCCCCCRRRRRR. */
+{ "cmp", 0x200C8000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* cmp<.cc> b,c 00100bbb110011001BBBCCCCCC0QQQQQ. */
+{ "cmp", 0x20CC8000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* cmp b,u6 00100bbb010011001BBBuuuuuuRRRRRR. */
+{ "cmp", 0x204C8000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* cmp<.cc> b,u6 00100bbb110011001BBBuuuuuu1QQQQQ. */
+{ "cmp", 0x20CC8020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* cmp b,s12 00100bbb100011001BBBssssssSSSSSS. */
+{ "cmp", 0x208C8000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* cmp limm,c 00100110000011001111CCCCCCRRRRRR. */
+{ "cmp", 0x260CF000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* cmp b,limm 00100bbb000011001BBB111110RRRRRR. */
+{ "cmp", 0x200C8F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* cmp<.cc> b,limm 00100bbb110011001BBB1111100QQQQQ. */
+{ "cmp", 0x20CC8F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* cmp<.cc> limm,c 00100110110011001111CCCCCC0QQQQQ. */
+{ "cmp", 0x26CCF000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { C_CC }},
+
+/* cmp limm,u6 00100110010011001111uuuuuuRRRRRR. */
+{ "cmp", 0x264CF000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* cmp<.cc> limm,u6 00100110110011001111uuuuuu1QQQQQ. */
+{ "cmp", 0x26CCF020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmp limm,s12 00100110100011001111ssssssSSSSSS. */
+{ "cmp", 0x268CF000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* cmp limm,limm 00100110000011001111111110RRRRRR. */
+{ "cmp", 0x260CFF80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* cmp<.cc> limm,limm 001001101100110011111111100QQQQQ. */
+{ "cmp", 0x26CCFF80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* cmpl RB,RC 01011bbb000011001BBBccccccRRRRRR. */
+{ "cmpl", 0x580C8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* cmpl<.cc> RB,RC 01011bbb110011001BBBcccccc0QQQQQ. */
+{ "cmpl", 0x58CC8000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* cmpl RB,u6 01011bbb010011001BBBuuuuuuRRRRRR. */
+{ "cmpl", 0x584C8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* cmpl<.cc> RB,u6 01011bbb110011001BBBuuuuuu1QQQQQ. */
+{ "cmpl", 0x58CC8020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* cmpl RB,s12 01011bbb100011001BBBssssssSSSSSS. */
+{ "cmpl", 0x588C8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* cmpl ximm,RC 01011100000011001111ccccccRRRRRR. */
+{ "cmpl", 0x5C0CF000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { XIMM, RC }, { 0 }},
+
+/* cmpl RB,ximm 01011bbb000011001BBB111100RRRRRR. */
+{ "cmpl", 0x580C8F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 }},
+
+/* cmpl<.cc> RB,ximm 01011bbb110011001BBB1111000QQQQQ. */
+{ "cmpl", 0x58CC8F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC }},
+
+/* cmpl limm,RC 01011110000011001111ccccccRRRRRR. */
+{ "cmpl", 0x5E0CF000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* cmpl RB,limm 01011bbb000011001BBB111110RRRRRR. */
+{ "cmpl", 0x580C8F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* cmpl<.cc> RB,limm 01011bbb110011001BBB1111100QQQQQ. */
+{ "cmpl", 0x58CC8F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* cmp_s b,h 01110bbbhhh100HH. */
+{ "cmp_s", 0x00007010, 0x0000F81C,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RH_S }, { 0 }},
+
+/* cmp_s h,s3 01110ssshhh101HH. */
+{ "cmp_s", 0x00007014, 0x0000F81C,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, SIMM3_5_S }, { 0 }},
+
+/* cmp_s b,limm 01110bbb11010011. */
+{ "cmp_s", 0x000070D3, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, LIMM_S }, { 0 }},
+
+/* cmp_s limm,s3 01110sss11010111. */
+{ "cmp_s", 0x000070D7, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM_S, SIMM3_5_S }, { 0 }},
+
+/* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS. */
+{ "dbnz", 0x208C0000, 0xF8FE8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, BRANCH, NONE, { RB, SIMM13_A16_20 }, { C_DNZ_D }},
+
+/* div<.f> a,b,c 00101bbb00000100FBBBCCCCCCAAAAAA. */
+{ "div", 0x28040000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
+
+/* div<.f> 0,b,c 00101bbb00000100FBBBCCCCCC111110. */
+{ "div", 0x2804003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
+
+/* div<.f><.cc> b,b,c 00101bbb11000100FBBBCCCCCC0QQQQQ. */
+{ "div", 0x28C40000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* div<.f> a,b,u6 00101bbb01000100FBBBuuuuuuAAAAAA. */
+{ "div", 0x28440000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* div<.f> 0,b,u6 00101bbb01000100FBBBuuuuuu111110. */
+{ "div", 0x2844003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* div<.f><.cc> b,b,u6 00101bbb11000100FBBBuuuuuu1QQQQQ. */
+{ "div", 0x28C40020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* div<.f> b,b,s12 00101bbb10000100FBBBssssssSSSSSS. */
+{ "div", 0x28840000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* div<.f> a,limm,c 0010111000000100F111CCCCCCAAAAAA. */
+{ "div", 0x2E047000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* div<.f> a,b,limm 00101bbb00000100FBBB111110AAAAAA. */
+{ "div", 0x28040F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* div<.f> 0,limm,c 0010111000000100F111CCCCCC111110. */
+{ "div", 0x2E04703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* div<.f> 0,b,limm 00101bbb00000100FBBB111110111110. */
+{ "div", 0x28040FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* div<.f><.cc> b,b,limm 00101bbb11000100FBBB1111100QQQQQ. */
+{ "div", 0x28C40F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* div<.f><.cc> 0,limm,c 0010111011000100F111CCCCCC0QQQQQ. */
+{ "div", 0x2EC47000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* div<.f> a,limm,u6 0010111001000100F111uuuuuuAAAAAA. */
+{ "div", 0x2E447000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* div<.f> 0,limm,u6 0010111001000100F111uuuuuu111110. */
+{ "div", 0x2E44703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* div<.f><.cc> 0,limm,u6 0010111011000100F111uuuuuu1QQQQQ. */
+{ "div", 0x2EC47020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* div<.f> 0,limm,s12 0010111010000100F111ssssssSSSSSS. */
+{ "div", 0x2E847000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* div<.f> a,limm,limm 0010111000000100F111111110AAAAAA. */
+{ "div", 0x2E047F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* div<.f> 0,limm,limm 0010111000000100F111111110111110. */
+{ "div", 0x2E047FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* div<.f><.cc> 0,limm,limm 0010111011000100F1111111100QQQQQ. */
+{ "div", 0x2EC47F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* divl<.f> RA,RB,RC 01011bbb00100100FBBBccccccaaaaaa. */
+{ "divl", 0x58240000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* divl<.f> 0,RB,RC 01011bbb00100100FBBBcccccc111110. */
+{ "divl", 0x5824003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* divl<.f><.cc> RB,RB,RC 01011bbb11100100FBBBcccccc0QQQQQ. */
+{ "divl", 0x58E40000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* divl<.f> RA,RB,u6 01011bbb01100100FBBBuuuuuuaaaaaa. */
+{ "divl", 0x58640000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* divl<.f> 0,RB,u6 01011bbb01100100FBBBuuuuuu111110. */
+{ "divl", 0x5864003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* divl<.f><.cc> RB,RB,u6 01011bbb11100100FBBBuuuuuu1QQQQQ. */
+{ "divl", 0x58E40020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* divl<.f> RB,RB,s12 01011bbb10100100FBBBssssssSSSSSS. */
+{ "divl", 0x58A40000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* divl<.f> RA,ximm,RC 0101110000100100F111ccccccaaaaaa. */
+{ "divl", 0x5C247000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* divl<.f> RA,RB,ximm 01011bbb00100100FBBB111100aaaaaa. */
+{ "divl", 0x58240F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* divl<.f> 0,ximm,RC 0101110000100100F111cccccc111110. */
+{ "divl", 0x5C24703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* divl<.f> 0,RB,ximm 01011bbb00100100FBBB111100111110. */
+{ "divl", 0x58240F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* divl<.f><.cc> 0,ximm,RC 0101110011100100F111cccccc0QQQQQ. */
+{ "divl", 0x5CE47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* divl<.f><.cc> RB,RB,ximm 01011bbb11100100FBBB1111000QQQQQ. */
+{ "divl", 0x58E40F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* divl<.f> RA,ximm,u6 0101110001100100F111uuuuuuaaaaaa. */
+{ "divl", 0x5C647000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* divl<.f> 0,ximm,u6 0101110001100100F111uuuuuu111110. */
+{ "divl", 0x5C64703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* divl<.f><.cc> 0,ximm,u6 0101110011100100F111uuuuuu1QQQQQ. */
+{ "divl", 0x5CE47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divl<.f> RA,limm,RC 0101111000100100F111ccccccaaaaaa. */
+{ "divl", 0x5E247000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* divl<.f> RA,RB,limm 01011bbb00100100FBBB111110aaaaaa. */
+{ "divl", 0x58240F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* divl<.f> 0,limm,RC 0101111000100100F111cccccc111110. */
+{ "divl", 0x5E24703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* divl<.f> 0,RB,limm 01011bbb00100100FBBB111110111110. */
+{ "divl", 0x58240FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* divl<.f><.cc> 0,limm,RC 0101111011100100F111cccccc0QQQQQ. */
+{ "divl", 0x5EE47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* divl<.f><.cc> RB,RB,limm 01011bbb11100100FBBB1111100QQQQQ. */
+{ "divl", 0x58E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* divl<.f> RA,limm,u6 0101111001100100F111uuuuuuaaaaaa. */
+{ "divl", 0x5E647000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divl<.f> 0,limm,u6 0101111001100100F111uuuuuu111110. */
+{ "divl", 0x5E64703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divl<.f><.cc> 0,limm,u6 0101111011100100F111uuuuuu1QQQQQ. */
+{ "divl", 0x5EE47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divl<.f> 0,ximm,s12 0101110010100100F111ssssssSSSSSS. */
+{ "divl", 0x5CA47000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* divl<.f> 0,limm,s12 0101111010100100F111ssssssSSSSSS. */
+{ "divl", 0x5EA47000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* divl<.f> RA,ximm,ximm 0101110000100100F111111100aaaaaa. */
+{ "divl", 0x5C247F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* divl<.f> 0,ximm,ximm 0101110000100100F111111100111110. */
+{ "divl", 0x5C247F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* divl<.f><.cc> 0,ximm,ximm 0101110011100100F1111111000QQQQQ. */
+{ "divl", 0x5CE47F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* divl<.f> RA,limm,limm 0101111000100100F111111110aaaaaa. */
+{ "divl", 0x5E247F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* divl<.f> 0,limm,limm 0101111000100100F111111110111110. */
+{ "divl", 0x5E247FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* divl<.f><.cc> 0,limm,limm 0101111011100100F1111111100QQQQQ. */
+{ "divl", 0x5EE47F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* divu<.f> a,b,c 00101bbb00000101FBBBCCCCCCAAAAAA. */
+{ "divu", 0x28050000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
+
+/* divu<.f> 0,b,c 00101bbb00000101FBBBCCCCCC111110. */
+{ "divu", 0x2805003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
+
+/* divu<.f><.cc> b,b,c 00101bbb11000101FBBBCCCCCC0QQQQQ. */
+{ "divu", 0x28C50000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* divu<.f> a,b,u6 00101bbb01000101FBBBuuuuuuAAAAAA. */
+{ "divu", 0x28450000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* divu<.f> 0,b,u6 00101bbb01000101FBBBuuuuuu111110. */
+{ "divu", 0x2845003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* divu<.f><.cc> b,b,u6 00101bbb11000101FBBBuuuuuu1QQQQQ. */
+{ "divu", 0x28C50020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* divu<.f> b,b,s12 00101bbb10000101FBBBssssssSSSSSS. */
+{ "divu", 0x28850000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* divu<.f> a,limm,c 0010111000000101F111CCCCCCAAAAAA. */
+{ "divu", 0x2E057000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* divu<.f> a,b,limm 00101bbb00000101FBBB111110AAAAAA. */
+{ "divu", 0x28050F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* divu<.f> 0,limm,c 0010111000000101F111CCCCCC111110. */
+{ "divu", 0x2E05703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* divu<.f> 0,b,limm 00101bbb00000101FBBB111110111110. */
+{ "divu", 0x28050FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* divu<.f><.cc> b,b,limm 00101bbb11000101FBBB1111100QQQQQ. */
+{ "divu", 0x28C50F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* divu<.f><.cc> 0,limm,c 0010111011000101F111CCCCCC0QQQQQ. */
+{ "divu", 0x2EC57000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* divu<.f> a,limm,u6 0010111001000101F111uuuuuuAAAAAA. */
+{ "divu", 0x2E457000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* divu<.f> 0,limm,u6 0010111001000101F111uuuuuu111110. */
+{ "divu", 0x2E45703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divu<.f><.cc> 0,limm,u6 0010111011000101F111uuuuuu1QQQQQ. */
+{ "divu", 0x2EC57020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divu<.f> 0,limm,s12 0010111010000101F111ssssssSSSSSS. */
+{ "divu", 0x2E857000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* divu<.f> a,limm,limm 0010111000000101F111111110AAAAAA. */
+{ "divu", 0x2E057F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* divu<.f> 0,limm,limm 0010111000000101F111111110111110. */
+{ "divu", 0x2E057FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* divu<.f><.cc> 0,limm,limm 0010111011000101F1111111100QQQQQ. */
+{ "divu", 0x2EC57F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* divul<.f> RA,RB,RC 01011bbb00100101FBBBccccccaaaaaa. */
+{ "divul", 0x58250000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* divul<.f> 0,RB,RC 01011bbb00100101FBBBcccccc111110. */
+{ "divul", 0x5825003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* divul<.f><.cc> RB,RB,RC 01011bbb11100101FBBBcccccc0QQQQQ. */
+{ "divul", 0x58E50000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* divul<.f> RA,RB,u6 01011bbb01100101FBBBuuuuuuaaaaaa. */
+{ "divul", 0x58650000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* divul<.f> 0,RB,u6 01011bbb01100101FBBBuuuuuu111110. */
+{ "divul", 0x5865003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* divul<.f><.cc> RB,RB,u6 01011bbb11100101FBBBuuuuuu1QQQQQ. */
+{ "divul", 0x58E50020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* divul<.f> RB,RB,s12 01011bbb10100101FBBBssssssSSSSSS. */
+{ "divul", 0x58A50000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* divul<.f> RA,ximm,RC 0101110000100101F111ccccccaaaaaa. */
+{ "divul", 0x5C257000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* divul<.f> RA,RB,ximm 01011bbb00100101FBBB111100aaaaaa. */
+{ "divul", 0x58250F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* divul<.f> 0,ximm,RC 0101110000100101F111cccccc111110. */
+{ "divul", 0x5C25703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* divul<.f> 0,RB,ximm 01011bbb00100101FBBB111100111110. */
+{ "divul", 0x58250F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* divul<.f><.cc> 0,ximm,RC 0101110011100101F111cccccc0QQQQQ. */
+{ "divul", 0x5CE57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* divul<.f><.cc> RB,RB,ximm 01011bbb11100101FBBB1111000QQQQQ. */
+{ "divul", 0x58E50F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* divul<.f> RA,ximm,u6 0101110001100101F111uuuuuuaaaaaa. */
+{ "divul", 0x5C657000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* divul<.f> 0,ximm,u6 0101110001100101F111uuuuuu111110. */
+{ "divul", 0x5C65703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* divul<.f><.cc> 0,ximm,u6 0101110011100101F111uuuuuu1QQQQQ. */
+{ "divul", 0x5CE57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divul<.f> RA,limm,RC 0101111000100101F111ccccccaaaaaa. */
+{ "divul", 0x5E257000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* divul<.f> RA,RB,limm 01011bbb00100101FBBB111110aaaaaa. */
+{ "divul", 0x58250F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* divul<.f> 0,limm,RC 0101111000100101F111cccccc111110. */
+{ "divul", 0x5E25703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* divul<.f> 0,RB,limm 01011bbb00100101FBBB111110111110. */
+{ "divul", 0x58250FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* divul<.f><.cc> 0,limm,RC 0101111011100101F111cccccc0QQQQQ. */
+{ "divul", 0x5EE57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* divul<.f><.cc> RB,RB,limm 01011bbb11100101FBBB1111100QQQQQ. */
+{ "divul", 0x58E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* divul<.f> RA,limm,u6 0101111001100101F111uuuuuuaaaaaa. */
+{ "divul", 0x5E657000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divul<.f> 0,limm,u6 0101111001100101F111uuuuuu111110. */
+{ "divul", 0x5E65703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divul<.f><.cc> 0,limm,u6 0101111011100101F111uuuuuu1QQQQQ. */
+{ "divul", 0x5EE57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divul<.f> 0,ximm,s12 0101110010100101F111ssssssSSSSSS. */
+{ "divul", 0x5CA57000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* divul<.f> 0,limm,s12 0101111010100101F111ssssssSSSSSS. */
+{ "divul", 0x5EA57000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* divul<.f> RA,ximm,ximm 0101110000100101F111111100aaaaaa. */
+{ "divul", 0x5C257F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* divul<.f> 0,ximm,ximm 0101110000100101F111111100111110. */
+{ "divul", 0x5C257F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* divul<.f><.cc> 0,ximm,ximm 0101110011100101F1111111000QQQQQ. */
+{ "divul", 0x5CE57F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* divul<.f> RA,limm,limm 0101111000100101F111111110aaaaaa. */
+{ "divul", 0x5E257F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* divul<.f> 0,limm,limm 0101111000100101F111111110111110. */
+{ "divul", 0x5E257FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* divul<.f><.cc> 0,limm,limm 0101111011100101F1111111100QQQQQ. */
+{ "divul", 0x5EE57F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmach<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA. */
+{ "dmach", 0x28120000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmach<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110. */
+{ "dmach", 0x2812003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmach<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ. */
+{ "dmach", 0x28D20000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmach<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA. */
+{ "dmach", 0x28520000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmach<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110. */
+{ "dmach", 0x2852003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmach<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ. */
+{ "dmach", 0x28D20020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmach<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS. */
+{ "dmach", 0x28920000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmach<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA. */
+{ "dmach", 0x2E127000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmach<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA. */
+{ "dmach", 0x28120F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmach<.f> 0,limm,c 0010111000010010F111CCCCCC111110. */
+{ "dmach", 0x2E12703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmach<.f> 0,b,limm 00101bbb00010010FBBB111110111110. */
+{ "dmach", 0x28120FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmach<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ. */
+{ "dmach", 0x28D20F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmach<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ. */
+{ "dmach", 0x2ED27000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmach<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA. */
+{ "dmach", 0x2E527000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmach<.f> 0,limm,u6 0010111001010010F111uuuuuu111110. */
+{ "dmach", 0x2E52703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmach<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ. */
+{ "dmach", 0x2ED27020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmach<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS. */
+{ "dmach", 0x2E927000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmach<.f> a,limm,limm 0010111000010010F111111110AAAAAA. */
+{ "dmach", 0x2E127F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmach<.f> 0,limm,limm 0010111000010010F111111110111110. */
+{ "dmach", 0x2E127FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmach<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ. */
+{ "dmach", 0x2ED27F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmachu<.f> a,b,c 00101bbb00010011FBBBCCCCCCAAAAAA. */
+{ "dmachu", 0x28130000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmachu<.f> 0,b,c 00101bbb00010011FBBBCCCCCC111110. */
+{ "dmachu", 0x2813003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmachu<.f><.cc> b,b,c 00101bbb11010011FBBBCCCCCC0QQQQQ. */
+{ "dmachu", 0x28D30000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmachu<.f> a,b,u6 00101bbb01010011FBBBuuuuuuAAAAAA. */
+{ "dmachu", 0x28530000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f> 0,b,u6 00101bbb01010011FBBBuuuuuu111110. */
+{ "dmachu", 0x2853003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f><.cc> b,b,u6 00101bbb11010011FBBBuuuuuu1QQQQQ. */
+{ "dmachu", 0x28D30020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachu<.f> b,b,s12 00101bbb10010011FBBBssssssSSSSSS. */
+{ "dmachu", 0x28930000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmachu<.f> a,limm,c 0010111000010011F111CCCCCCAAAAAA. */
+{ "dmachu", 0x2E137000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmachu<.f> a,b,limm 00101bbb00010011FBBB111110AAAAAA. */
+{ "dmachu", 0x28130F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmachu<.f> 0,limm,c 0010111000010011F111CCCCCC111110. */
+{ "dmachu", 0x2E13703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmachu<.f> 0,b,limm 00101bbb00010011FBBB111110111110. */
+{ "dmachu", 0x28130FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmachu<.f><.cc> b,b,limm 00101bbb11010011FBBB1111100QQQQQ. */
+{ "dmachu", 0x28D30F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmachu<.f><.cc> 0,limm,c 0010111011010011F111CCCCCC0QQQQQ. */
+{ "dmachu", 0x2ED37000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmachu<.f> a,limm,u6 0010111001010011F111uuuuuuAAAAAA. */
+{ "dmachu", 0x2E537000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f> 0,limm,u6 0010111001010011F111uuuuuu111110. */
+{ "dmachu", 0x2E53703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f><.cc> 0,limm,u6 0010111011010011F111uuuuuu1QQQQQ. */
+{ "dmachu", 0x2ED37020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachu<.f> 0,limm,s12 0010111010010011F111ssssssSSSSSS. */
+{ "dmachu", 0x2E937000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmachu<.f> a,limm,limm 0010111000010011F111111110AAAAAA. */
+{ "dmachu", 0x2E137F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmachu<.f> 0,limm,limm 0010111000010011F111111110111110. */
+{ "dmachu", 0x2E137FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachu<.f><.cc> 0,limm,limm 0010111011010011F1111111100QQQQQ. */
+{ "dmachu", 0x2ED37F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmacwh<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA. */
+{ "dmacwh", 0x28360000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmacwh<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110. */
+{ "dmacwh", 0x2836003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmacwh<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ. */
+{ "dmacwh", 0x28F60000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmacwh<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA. */
+{ "dmacwh", 0x28760000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110. */
+{ "dmacwh", 0x2876003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ. */
+{ "dmacwh", 0x28F60020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwh<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS. */
+{ "dmacwh", 0x28B60000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmacwh<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA. */
+{ "dmacwh", 0x2E367000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmacwh<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA. */
+{ "dmacwh", 0x28360F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmacwh<.f> 0,limm,c 0010111000110110F111CCCCCC111110. */
+{ "dmacwh", 0x2E36703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmacwh<.f> 0,b,limm 00101bbb00110110FBBB111110111110. */
+{ "dmacwh", 0x28360FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmacwh<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ. */
+{ "dmacwh", 0x28F60F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmacwh<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ. */
+{ "dmacwh", 0x2EF67000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmacwh<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA. */
+{ "dmacwh", 0x2E767000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f> 0,limm,u6 0010111001110110F111uuuuuu111110. */
+{ "dmacwh", 0x2E76703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ. */
+{ "dmacwh", 0x2EF67020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwh<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS. */
+{ "dmacwh", 0x2EB67000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmacwh<.f> a,limm,limm 0010111000110110F111111110AAAAAA. */
+{ "dmacwh", 0x2E367F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwh<.f> 0,limm,limm 0010111000110110F111111110111110. */
+{ "dmacwh", 0x2E367FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwh<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ. */
+{ "dmacwh", 0x2EF67F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmacwhu<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA. */
+{ "dmacwhu", 0x28370000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmacwhu<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110. */
+{ "dmacwhu", 0x2837003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmacwhu<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ. */
+{ "dmacwhu", 0x28F70000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmacwhu<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA. */
+{ "dmacwhu", 0x28770000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110. */
+{ "dmacwhu", 0x2877003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ. */
+{ "dmacwhu", 0x28F70020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwhu<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS. */
+{ "dmacwhu", 0x28B70000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmacwhu<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA. */
+{ "dmacwhu", 0x2E377000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmacwhu<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA. */
+{ "dmacwhu", 0x28370F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmacwhu<.f> 0,limm,c 0010111000110111F111CCCCCC111110. */
+{ "dmacwhu", 0x2E37703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmacwhu<.f> 0,b,limm 00101bbb00110111FBBB111110111110. */
+{ "dmacwhu", 0x28370FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmacwhu<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ. */
+{ "dmacwhu", 0x28F70F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmacwhu<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ. */
+{ "dmacwhu", 0x2EF77000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmacwhu<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA. */
+{ "dmacwhu", 0x2E777000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f> 0,limm,u6 0010111001110111F111uuuuuu111110. */
+{ "dmacwhu", 0x2E77703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ. */
+{ "dmacwhu", 0x2EF77020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwhu<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS. */
+{ "dmacwhu", 0x2EB77000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmacwhu<.f> a,limm,limm 0010111000110111F111111110AAAAAA. */
+{ "dmacwhu", 0x2E377F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwhu<.f> 0,limm,limm 0010111000110111F111111110111110. */
+{ "dmacwhu", 0x2E377FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwhu<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ. */
+{ "dmacwhu", 0x2EF77F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmb 00100011011011110001RRR000111111. */
+{ "dmb", 0x236F103F, 0xFFFFF1FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* dmb u3 00100011011011110001RRRuuu111111. */
+{ "dmb", 0x236F103F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM3_23 }, { 0 }},
+
+/* dmpyh<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA. */
+{ "dmpyh", 0x28100000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpyh<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110. */
+{ "dmpyh", 0x2810003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmpyh<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ. */
+{ "dmpyh", 0x28D00000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyh<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA. */
+{ "dmpyh", 0x28500000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110. */
+{ "dmpyh", 0x2850003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ. */
+{ "dmpyh", 0x28D00020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyh<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS. */
+{ "dmpyh", 0x28900000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyh<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA. */
+{ "dmpyh", 0x2E107000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpyh<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA. */
+{ "dmpyh", 0x28100F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpyh<.f> 0,limm,c 0010111000010000F111CCCCCC111110. */
+{ "dmpyh", 0x2E10703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyh<.f> 0,b,limm 00101bbb00010000FBBB111110111110. */
+{ "dmpyh", 0x28100FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyh<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ. */
+{ "dmpyh", 0x28D00F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyh<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ. */
+{ "dmpyh", 0x2ED07000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyh<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA. */
+{ "dmpyh", 0x2E507000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f> 0,limm,u6 0010111001010000F111uuuuuu111110. */
+{ "dmpyh", 0x2E50703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ. */
+{ "dmpyh", 0x2ED07020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyh<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS. */
+{ "dmpyh", 0x2E907000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyh<.f> a,limm,limm 0010111000010000F111111110AAAAAA. */
+{ "dmpyh", 0x2E107F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyh<.f> 0,limm,limm 0010111000010000F111111110111110. */
+{ "dmpyh", 0x2E107FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyh<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ. */
+{ "dmpyh", 0x2ED07F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhu<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA. */
+{ "dmpyhu", 0x28110000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpyhu<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110. */
+{ "dmpyhu", 0x2811003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhu<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ. */
+{ "dmpyhu", 0x28D10000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhu<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA. */
+{ "dmpyhu", 0x28510000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110. */
+{ "dmpyhu", 0x2851003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ. */
+{ "dmpyhu", 0x28D10020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhu<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS. */
+{ "dmpyhu", 0x28910000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhu<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA. */
+{ "dmpyhu", 0x2E117000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpyhu<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA. */
+{ "dmpyhu", 0x28110F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpyhu<.f> 0,limm,c 0010111000010001F111CCCCCC111110. */
+{ "dmpyhu", 0x2E11703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhu<.f> 0,b,limm 00101bbb00010001FBBB111110111110. */
+{ "dmpyhu", 0x28110FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhu<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ. */
+{ "dmpyhu", 0x28D10F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhu<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ. */
+{ "dmpyhu", 0x2ED17000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhu<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA. */
+{ "dmpyhu", 0x2E517000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f> 0,limm,u6 0010111001010001F111uuuuuu111110. */
+{ "dmpyhu", 0x2E51703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ. */
+{ "dmpyhu", 0x2ED17020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhu<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS. */
+{ "dmpyhu", 0x2E917000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhu<.f> a,limm,limm 0010111000010001F111111110AAAAAA. */
+{ "dmpyhu", 0x2E117F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhu<.f> 0,limm,limm 0010111000010001F111111110111110. */
+{ "dmpyhu", 0x2E117FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhu<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ. */
+{ "dmpyhu", 0x2ED17F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpywh<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA. */
+{ "dmpywh", 0x28320000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpywh<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110. */
+{ "dmpywh", 0x2832003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmpywh<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ. */
+{ "dmpywh", 0x28F20000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpywh<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA. */
+{ "dmpywh", 0x28720000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110. */
+{ "dmpywh", 0x2872003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ. */
+{ "dmpywh", 0x28F20020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywh<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS. */
+{ "dmpywh", 0x28B20000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpywh<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA. */
+{ "dmpywh", 0x2E327000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpywh<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA. */
+{ "dmpywh", 0x28320F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpywh<.f> 0,limm,c 0010111000110010F111CCCCCC111110. */
+{ "dmpywh", 0x2E32703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpywh<.f> 0,b,limm 00101bbb00110010FBBB111110111110. */
+{ "dmpywh", 0x28320FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpywh<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ. */
+{ "dmpywh", 0x28F20F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpywh<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ. */
+{ "dmpywh", 0x2EF27000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpywh<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA. */
+{ "dmpywh", 0x2E727000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f> 0,limm,u6 0010111001110010F111uuuuuu111110. */
+{ "dmpywh", 0x2E72703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ. */
+{ "dmpywh", 0x2EF27020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywh<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS. */
+{ "dmpywh", 0x2EB27000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpywh<.f> a,limm,limm 0010111000110010F111111110AAAAAA. */
+{ "dmpywh", 0x2E327F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywh<.f> 0,limm,limm 0010111000110010F111111110111110. */
+{ "dmpywh", 0x2E327FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywh<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ. */
+{ "dmpywh", 0x2EF27F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpywhu<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA. */
+{ "dmpywhu", 0x28330000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpywhu<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110. */
+{ "dmpywhu", 0x2833003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmpywhu<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ. */
+{ "dmpywhu", 0x28F30000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpywhu<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA. */
+{ "dmpywhu", 0x28730000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110. */
+{ "dmpywhu", 0x2873003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ. */
+{ "dmpywhu", 0x28F30020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywhu<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS. */
+{ "dmpywhu", 0x28B30000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpywhu<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA. */
+{ "dmpywhu", 0x2E337000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpywhu<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA. */
+{ "dmpywhu", 0x28330F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpywhu<.f> 0,limm,c 0010111000110011F111CCCCCC111110. */
+{ "dmpywhu", 0x2E33703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpywhu<.f> 0,b,limm 00101bbb00110011FBBB111110111110. */
+{ "dmpywhu", 0x28330FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpywhu<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ. */
+{ "dmpywhu", 0x28F30F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpywhu<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ. */
+{ "dmpywhu", 0x2EF37000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpywhu<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA. */
+{ "dmpywhu", 0x2E737000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f> 0,limm,u6 0010111001110011F111uuuuuu111110. */
+{ "dmpywhu", 0x2E73703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ. */
+{ "dmpywhu", 0x2EF37020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywhu<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS. */
+{ "dmpywhu", 0x2EB37000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpywhu<.f> a,limm,limm 0010111000110011F111111110AAAAAA. */
+{ "dmpywhu", 0x2E337F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywhu<.f> 0,limm,limm 0010111000110011F111111110111110. */
+{ "dmpywhu", 0x2E337FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywhu<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ. */
+{ "dmpywhu", 0x2EF37F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dsync 00100010011011110001RRRRRR111111. */
+{ "dsync", 0x226F103F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* enter_s u6 110000UU111uuuu0. */
+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ENTER, NONE, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }},
+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ENTER, NONE, { BRAKET, R13_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }},
+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ENTER, NONE, { UIMM6_11_S }, { 0 }},
+
+/* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100. */
+{ "ex", 0x202F000C, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> b,u6 00100bbb01101111DBBBuuuuuu001100. */
+{ "ex", 0x206F000C, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> b,limm 00100bbb00101111DBBB111110001100. */
+{ "ex", 0x202F0F8C, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> limm,c 0010011000101111D111CCCCCC001100. */
+{ "ex", 0x262F700C, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> limm,u6 0010011001101111D111uuuuuu001100. */
+{ "ex", 0x266F700C, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> limm,limm 0010011000101111D111111110001100. */
+{ "ex", 0x262F7F8C, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 }},
+
+/* exl<.aq> RB,RC 01011bbb00101111FBBBcccccc001100. */
+{ "exl", 0x582F000C, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_AQ, C_RL }},
+
+/* extb<.f> b,c 00100bbb00101111FBBBCCCCCC000111. */
+{ "extb", 0x202F0007, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* extb<.f> 0,c 0010011000101111F111CCCCCC000111. */
+{ "extb", 0x262F7007, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* extb<.f> b,u6 00100bbb01101111FBBBuuuuuu000111. */
+{ "extb", 0x206F0007, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* extb<.f> 0,u6 0010011001101111F111uuuuuu000111. */
+{ "extb", 0x266F7007, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* extb<.f> b,limm 00100bbb00101111FBBB111110000111. */
+{ "extb", 0x202F0F87, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* extb<.f> 0,limm 0010011000101111F111111110000111. */
+{ "extb", 0x262F7F87, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* extb_s b,c 01111bbbccc01111. */
+{ "extb_s", 0x0000780F, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* exth<.f> b,c 00100bbb00101111FBBBCCCCCC001000. */
+{ "exth", 0x202F0008, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* exth<.f> 0,c 0010011000101111F111CCCCCC001000. */
+{ "exth", 0x262F7008, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* exth<.f> b,u6 00100bbb01101111FBBBuuuuuu001000. */
+{ "exth", 0x206F0008, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* exth<.f> 0,u6 0010011001101111F111uuuuuu001000. */
+{ "exth", 0x266F7008, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* exth<.f> b,limm 00100bbb00101111FBBB111110001000. */
+{ "exth", 0x202F0F88, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* exth<.f> 0,limm 0010011000101111F111111110001000. */
+{ "exth", 0x262F7F88, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* exth_s b,c 01111bbbccc10000. */
+{ "exth_s", 0x00007810, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* ffs<.f> b,c 00101bbb00101111FBBBCCCCCC010010. */
+{ "ffs", 0x282F0012, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* ffs<.f> 0,c 0010111000101111F111CCCCCC010010. */
+{ "ffs", 0x2E2F7012, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* ffs<.f> b,u6 00101bbb01101111FBBBuuuuuu010010. */
+{ "ffs", 0x286F0012, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* ffs<.f> 0,u6 0010111001101111F111uuuuuu010010. */
+{ "ffs", 0x2E6F7012, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* ffs<.f> b,limm 00101bbb00101111FBBB111110010010. */
+{ "ffs", 0x282F0F92, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* ffs<.f> 0,limm 0010111000101111F111111110010010. */
+{ "ffs", 0x2E2F7F92, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* ffsl<.f> RB,RC 01011bbb00101111FBBBcccccc010010. */
+{ "ffsl", 0x582F0012, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* ffsl<.f> 0,RC 0101111000101111F111cccccc010010. */
+{ "ffsl", 0x5E2F7012, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* ffsl<.f> RB,u6 01011bbb01101111FBBBuuuuuu010010. */
+{ "ffsl", 0x586F0012, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* ffsl<.f> 0,u6 0101111001101111F111uuuuuu010010. */
+{ "ffsl", 0x5E6F7012, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* ffsl<.f> RB,ximm 01011bbb00101111FBBB111100010010. */
+{ "ffsl", 0x582F0F12, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* ffsl<.f> 0,ximm 0101111000101111F111111100010010. */
+{ "ffsl", 0x5E2F7F12, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* ffsl<.f> RB,limm 01011bbb00101111FBBB111110010010. */
+{ "ffsl", 0x582F0F92, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* ffsl<.f> 0,limm 0101111000101111F111111110010010. */
+{ "ffsl", 0x5E2F7F92, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* flag c 00100RRR001010010RRRCCCCCCRRRRRR. */
+{ "flag", 0x20290000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { 0 }},
+
+/* flag<.cc> c 00100RRR111010010RRRCCCCCC0QQQQQ. */
+{ "flag", 0x20E90000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { C_CC }},
+
+/* flag u6 00100RRR011010010RRRuuuuuuRRRRRR. */
+{ "flag", 0x20690000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* flag<.cc> u6 00100RRR111010010RRRuuuuuu1QQQQQ. */
+{ "flag", 0x20E90020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { C_CC }},
+
+/* flag s12 00100RRR101010010RRRssssssSSSSSS. */
+{ "flag", 0x20A90000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { SIMM12_20 }, { 0 }},
+
+/* flag limm 00100RRR001010010RRR111110RRRRRR. */
+{ "flag", 0x20290F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { LIMM }, { 0 }},
+
+/* flag<.cc> limm 00100RRR111010010RRR1111100QQQQQ. */
+{ "flag", 0x20E90F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { LIMM }, { C_CC }},
+
+/* fls<.f> b,c 00101bbb00101111FBBBCCCCCC010011. */
+{ "fls", 0x282F0013, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* fls<.f> 0,c 0010111000101111F111CCCCCC010011. */
+{ "fls", 0x2E2F7013, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* fls<.f> b,u6 00101bbb01101111FBBBuuuuuu010011. */
+{ "fls", 0x286F0013, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* fls<.f> 0,u6 0010111001101111F111uuuuuu010011. */
+{ "fls", 0x2E6F7013, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* fls<.f> b,limm 00101bbb00101111FBBB111110010011. */
+{ "fls", 0x282F0F93, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* fls<.f> 0,limm 0010111000101111F111111110010011. */
+{ "fls", 0x2E2F7F93, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* flsl<.f> RB,RC 01011bbb00101111FBBBcccccc010011. */
+{ "flsl", 0x582F0013, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* flsl<.f> 0,RC 0101111000101111F111cccccc010011. */
+{ "flsl", 0x5E2F7013, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* flsl<.f> RB,u6 01011bbb01101111FBBBuuuuuu010011. */
+{ "flsl", 0x586F0013, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* flsl<.f> 0,u6 0101111001101111F111uuuuuu010011. */
+{ "flsl", 0x5E6F7013, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* flsl<.f> RB,ximm 01011bbb00101111FBBB111100010011. */
+{ "flsl", 0x582F0F13, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* flsl<.f> 0,ximm 0101111000101111F111111100010011. */
+{ "flsl", 0x5E2F7F13, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* flsl<.f> RB,limm 01011bbb00101111FBBB111110010011. */
+{ "flsl", 0x582F0F93, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* flsl<.f> 0,limm 0101111000101111F111111110010011. */
+{ "flsl", 0x5E2F7F93, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* j c 00100RRR00100000RRRRCCCCCCRRRRRR. */
+{ "j", 0x20200000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* j BLINK 00100RRR00100000RRRR011111RRRRRR. */
+{ "j", 0x202007C0, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { 0 }},
+
+/* jcc c 00100RRR11100000RRRRCCCCCC0QQQQQ. */
+{ "j", 0x20E00000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* jcc BLINK 00100RRR11100000RRRR0111110QQQQQ. */
+{ "j", 0x20E007C0, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, BLINK, BRAKETdup }, { C_CC }},
+
+/* j.D c 00100RRR00100001RRRRCCCCCCRRRRRR. */
+{ "j", 0x20210000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }},
+
+/* j.D BLINK 00100RRR00100001RRRR011111RRRRRR. */
+{ "j", 0x202107C0, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_DHARD }},
+
+/* j.Dcc c 00100RRR11100001RRRRCCCCCC0QQQQQ. */
+{ "j", 0x20E10000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* j.Dcc BLINK 00100RRR11100001RRRR0111110QQQQQ. */
+{ "j", 0x20E107C0, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, BLINK, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* j s12 00100RRR10100000RRRRssssssSSSSSS. */
+{ "j", 0x20A00000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { SIMM12_20 }, { 0 }},
+
+/* j.D s12 00100RRR10100001RRRRssssssSSSSSS. */
+{ "j", 0x20A10000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { SIMM12_20 }, { C_DHARD }},
+
+/* j u6 00100RRR01100000RRRRuuuuuuRRRRRR. */
+{ "j", 0x20600000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { 0 }},
+
+/* jcc u6 00100RRR11100000RRRRuuuuuu1QQQQQ. */
+{ "j", 0x20E00020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, COND, { UIMM6_20 }, { C_CC }},
+
+/* j.D u6 00100RRR01100001RRRRuuuuuuRRRRRR. */
+{ "j", 0x20610000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { C_DHARD }},
+
+/* j.Dcc u6 00100RRR11100001RRRRuuuuuu1QQQQQ. */
+{ "j", 0x20E10020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, COND, { UIMM6_20 }, { C_CC, C_DHARD }},
+
+/* j limm 00100RRR00100000RRRR111110RRRRRR. */
+{ "j", 0x20200F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { LIMM }, { 0 }},
+
+/* jcc limm 00100RRR11100000RRRR1111100QQQQQ. */
+{ "j", 0x20E00F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, COND, { LIMM }, { C_CC }},
+
+/* jeq_sCC_EQ BLINK 0111110011100000. */
+{ "jeq_s", 0x00007CE0, 0x0000FFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_EQ }},
+
+/* jl c 00100RRR00100010RRRRCCCCCCRRRRRR. */
+{ "jl", 0x20220000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* jlcc c 00100RRR11100010RRRRCCCCCC0QQQQQ. */
+{ "jl", 0x20E20000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* jl.D c 00100RRR00100011RRRRCCCCCCRRRRRR. */
+{ "jl", 0x20230000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }},
+
+/* jl.Dcc c 00100RRR11100011RRRRCCCCCC0QQQQQ. */
+{ "jl", 0x20E30000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* jl s12 00100RRR10100010RRRRssssssSSSSSS. */
+{ "jl", 0x20A20000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { SIMM12_20 }, { 0 }},
+
+/* jl.D s12 00100RRR10100011RRRRssssssSSSSSS. */
+{ "jl", 0x20A30000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { SIMM12_20 }, { C_DHARD }},
+
+/* jl u6 00100RRR01100010RRRRuuuuuuRRRRRR. */
+{ "jl", 0x20620000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { 0 }},
+
+/* jlcc u6 00100RRR11100010RRRRuuuuuu1QQQQQ. */
+{ "jl", 0x20E20020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { C_CC }},
+
+/* jl.D u6 00100RRR01100011RRRRuuuuuuRRRRRR. */
+{ "jl", 0x20630000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { C_DHARD }},
+
+/* jl.Dcc u6 00100RRR11100011RRRRuuuuuu1QQQQQ. */
+{ "jl", 0x20E30020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { C_CC, C_DHARD }},
+
+/* jl limm 00100RRR00100010RRRR111110RRRRRR. */
+{ "jl", 0x20220F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { LIMM }, { 0 }},
+
+/* jlcc limm 00100RRR11100010RRRR1111100QQQQQ. */
+{ "jl", 0x20E20F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { LIMM }, { C_CC }},
+
+/* jli_s u10 01010UUUUUUU1uuu. */
+{ "jli_s", 0x00005008, 0x0000F808, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JLI, NONE, { UIMM10_13_S }, { 0 }},
+
+/* jl_s b 01111bbb01000000. */
+{ "jl_s", 0x00007840, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }},
+
+/* jl_s.D b 01111bbb01100000. */
+{ "jl_s", 0x00007860, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }},
+
+/* jne_sCC_NE BLINK 0111110111100000. */
+{ "jne_s", 0x00007DE0, 0x0000FFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_NE }},
+
+/* j_s b 01111bbb00000000. */
+{ "j_s", 0x00007800, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }},
+
+/* j_s.D b 01111bbb00100000. */
+{ "j_s", 0x00007820, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }},
+
+/* j_s BLINK 0111111011100000. */
+{ "j_s", 0x00007EE0, 0x0000FFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+
+/* j_s.D BLINK 0111111111100000. */
+{ "j_s", 0x00007FE0, 0x0000FFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { C_DHARD }},
+
+/* kflag c 00100RRR001010011RRRCCCCCCRRRRRR. */
+{ "kflag", 0x20298000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { 0 }},
+
+/* kflag<.cc> c 00100RRR111010011RRRCCCCCC0QQQQQ. */
+{ "kflag", 0x20E98000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { C_CC }},
+
+/* kflag u6 00100RRR011010011RRRuuuuuuRRRRRR. */
+{ "kflag", 0x20698000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* kflag<.cc> u6 00100RRR111010011RRRuuuuuu1QQQQQ. */
+{ "kflag", 0x20E98020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { C_CC }},
+
+/* kflag s12 00100RRR101010011RRRssssssSSSSSS. */
+{ "kflag", 0x20A98000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { SIMM12_20 }, { 0 }},
+
+/* kflag limm 00100RRR001010011RRR111110RRRRRR. */
+{ "kflag", 0x20298F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { LIMM }, { 0 }},
+
+/* kflag<.cc> limm 00100RRR111010011RRR1111100QQQQQ. */
+{ "kflag", 0x20E98F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { LIMM }, { C_CC }},
+
+/* ldZZ_W<.di><.aa> a,b 00010bbb000000000BBBDaa000AAAAAA. */
+{ "ld", 0x10000000, 0xF8FF81C0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }},
+
+/* ldZZ_W<.di><.aa> a,b,c 00100bbbaa110000DBBBCCCCCCAAAAAA. */
+{ "ld", 0x20300000, 0xF83F0000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.di><.aa> 0,b,c 00100bbbaa110000DBBBCCCCCC111110. */
+{ "ld", 0x2030003E, 0xF83F003F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.x><.aa> a,b 00010bbb000000000BBB0aa00XAAAAAA. */
+{ "ld", 0x10000000, 0xF8FF8980, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }},
+
+/* ldZZ_W<.x><.aa> a,b,c 00100bbbaa11000X0BBBCCCCCCAAAAAA. */
+{ "ld", 0x20300000, 0xF83E8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.x><.aa> 0,b,c 00100bbbaa11000X0BBBCCCCCC111110. */
+{ "ld", 0x2030003E, 0xF83E803F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa000AAAAAA. */
+{ "ld", 0x10000000, 0xF80001C0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }},
+
+/* ldZZ_W<.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa000111110. */
+{ "ld", 0x1000003E, 0xF80001FF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }},
+
+/* ldZZ_W<.x><.aa> a,b,s9 00010bbbssssssssSBBB0aa00XAAAAAA. */
+{ "ld", 0x10000000, 0xF8000980, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }},
+
+/* ldZZ_W<.x><.aa> 0,b,s9 00010bbbssssssssSBBB0aa00X111110. */
+{ "ld", 0x1000003E, 0xF80009BF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }},
+
+/* ldZZ_W<.di> a,limm 00010110000000000111D00000AAAAAA. */
+{ "ld", 0x16007000, 0xFFFFF7C0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_DI20 }},
+
+/* ldZZ_W<.di> 0,limm 00010110000000000111D00000111110. */
+{ "ld", 0x1600703E, 0xFFFFF7FF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_DI20 }},
+
+/* ldZZ_W<.di><.aa> a,b,ximm 00100bbbaa110000DBBB111100AAAAAA. */
+{ "ld", 0x20300F00, 0xF83F0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.di><.aa> a,b,limm 00100bbbaa110000DBBB111110AAAAAA. */
+{ "ld", 0x20300F80, 0xF83F0FC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.di><.aa> a,ximm,c 00100100aa110000D111CCCCCCAAAAAA. */
+{ "ld", 0x24307000, 0xFF3F7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.di><.aa> a,limm,c 00100110aa110000D111CCCCCCAAAAAA. */
+{ "ld", 0x26307000, 0xFF3F7000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.di><.aa> 0,b,limm 00100bbbaa110000DBBB111110111110. */
+{ "ld", 0x20300FBE, 0xF83F0FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.di><.aa> 0,limm,c 00100110aa110000D111CCCCCC111110. */
+{ "ld", 0x2630703E, 0xFF3F703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.x> a,limm 0001011000000000011100000XAAAAAA. */
+{ "ld", 0x16007000, 0xFFFFFF80, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_X25 }},
+
+/* ldZZ_W<.x> 0,limm 0001011000000000011100000X111110. */
+{ "ld", 0x1600703E, 0xFFFFFFBF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_X25 }},
+
+/* ldZZ_W<.x><.aa> a,b,ximm 00100bbbaa11000X0BBB111100AAAAAA. */
+{ "ld", 0x20300F00, 0xF83E8FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.x><.aa> a,b,limm 00100bbbaa11000X0BBB111110AAAAAA. */
+{ "ld", 0x20300F80, 0xF83E8FC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.x><.aa> a,ximm,c 00100100aa11000X0111CCCCCCAAAAAA. */
+{ "ld", 0x24307000, 0xFF3EF000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.x><.aa> a,limm,c 00100110aa11000X0111CCCCCCAAAAAA. */
+{ "ld", 0x26307000, 0xFF3EF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.x><.aa> 0,b,limm 00100bbbaa11000X0BBB111110111110. */
+{ "ld", 0x20300FBE, 0xF83E8FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.di><.aa> a,limm,s9 00010110ssssssssS111Daa000AAAAAA. */
+{ "ld", 0x16007000, 0xFF0071C0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }},
+
+/* ldZZ_W<.di><.aa> 0,limm,s9 00010110ssssssssS111Daa000111110. */
+{ "ld", 0x1600703E, 0xFF0071FF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }},
+
+/* ldZZ_W<.x><.aa> a,limm,s9 00010110ssssssssS1110aa00XAAAAAA. */
+{ "ld", 0x16007000, 0xFF007980, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }},
+
+/* ldZZ_W<.x><.aa> 0,limm,s9 00010110ssssssssS1110aa00X111110. */
+{ "ld", 0x1600703E, 0xFF0079BF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }},
+
+/* ldZZ_W<.x><.aa> 0,limm,c 00100110aa11000X0111CCCCCC111110. */
+{ "ld", 0x2630703E, 0xFF3EF03F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, LIMM, RC }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,b 00010bbb000000000BBBDaa01XAAAAAA. */
+{ "ldb", 0x10000080, 0xF8FF8180, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,b,c 00100bbbaa11001XDBBBCCCCCCAAAAAA. */
+{ "ldb", 0x20320000, 0xF83E0000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> 0,b,c 00100bbbaa11001XDBBBCCCCCC111110. */
+{ "ldb", 0x2032003E, 0xF83E003F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa01XAAAAAA. */
+{ "ldb", 0x10000080, 0xF8000180, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+
+/* ldbZZ_B<.x><.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa01X111110. */
+{ "ldb", 0x100000BE, 0xF80001BF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+
+/* ldbZZ_B<.x><.di> a,ximm 00010100000000000111D0001XAAAAAA. */
+{ "ldb", 0x14007080, 0xFFFFF780, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 }},
+/* ldbZZ_B<.x><.di> a,limm 00010110000000000111D0001XAAAAAA. */
+{ "ldb", 0x16007080, 0xFFFFF780, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 }},
+
+/* ldbZZ_B<.x><.di> 0,limm 00010110000000000111D0001X111110. */
+{ "ldb", 0x160070BE, 0xFFFFF7BF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,b,ximm 00100bbbaa11001XDBBB111100AAAAAA. */
+{ "ldb", 0x20320F00, 0xF83E0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+/* ldbZZ_B<.x><.di><.aa> a,b,limm 00100bbbaa11001XDBBB111110AAAAAA. */
+{ "ldb", 0x20320F80, 0xF83E0FC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,ximm,c 00100100aa11001XD111CCCCCCAAAAAA. */
+{ "ldb", 0x24327000, 0xFF3E7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+/* ldbZZ_B<.x><.di><.aa> a,limm,c 00100110aa11001XD111CCCCCCAAAAAA. */
+{ "ldb", 0x26327000, 0xFF3E7000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> 0,b,limm 00100bbbaa11001XDBBB111110111110. */
+{ "ldb", 0x20320FBE, 0xF83E0FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> 0,limm,c 00100110aa11001XD111CCCCCC111110. */
+{ "ldb", 0x2632703E, 0xFF3E703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,ximm,s9 00010100ssssssssS111Daa01XAAAAAA. */
+{ "ldb", 0x14007080, 0xFF007180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+/* ldbZZ_B<.x><.di><.aa> a,limm,s9 00010110ssssssssS111Daa01XAAAAAA. */
+{ "ldb", 0x16007080, 0xFF007180, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+
+/* ldbZZ_B<.x><.di><.aa> 0,limm,s9 00010110ssssssssS111Daa01X111110. */
+{ "ldb", 0x160070BE, 0xFF0071BF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b 00010bbb000000000BBBDaa10XAAAAAA. */
+{ "ldh", 0x10000100, 0xF8FF8180, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,c 00100bbbaa11010XDBBBCCCCCCAAAAAA. */
+{ "ldh", 0x20340000, 0xF83E0000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,c 00100bbbaa11010XDBBBCCCCCC111110. */
+{ "ldh", 0x2034003E, 0xF83E003F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa10XAAAAAA. */
+{ "ldh", 0x10000100, 0xF8000180, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa10X111110. */
+{ "ldh", 0x1000013E, 0xF80001BF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di> a,limm 00010110000000000111D0010XAAAAAA. */
+{ "ldh", 0x16007100, 0xFFFFF780, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }},
+
+/* ldhZZ_H<.x><.di> 0,limm 00010110000000000111D0010X111110. */
+{ "ldh", 0x1600713E, 0xFFFFF7BF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,ximm 00100bbbaa11010XDBBB111100AAAAAA. */
+{ "ldh", 0x20340F00, 0xF83E0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,limm 00100bbbaa11010XDBBB111110AAAAAA. */
+{ "ldh", 0x20340F80, 0xF83E0FC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,ximm,c 00100100aa11010XD111CCCCCCAAAAAA. */
+{ "ldh", 0x24347000, 0xFF3E7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,limm,c 00100110aa11010XD111CCCCCCAAAAAA. */
+{ "ldh", 0x26347000, 0xFF3E7000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,limm 00100bbbaa11010XDBBB111110111110. */
+{ "ldh", 0x20340FBE, 0xF83E0FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,limm,c 00100110aa11010XD111CCCCCC111110. */
+{ "ldh", 0x2634703E, 0xFF3E703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,limm,s9 00010110ssssssssS111Daa10XAAAAAA. */
+{ "ldh", 0x16007100, 0xFF007180, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,limm,s9 00010110ssssssssS111Daa10X111110. */
+{ "ldh", 0x1600713E, 0xFF0071BF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+
+/* ldhZZ_H<.x><.di><.aa> a,b 00010bbb000000000BBBDaa10XAAAAAA. */
+{ "ldw", 0x10000100, 0xF8FF8180, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,c 00100bbbaa11010XDBBBCCCCCCAAAAAA. */
+{ "ldw", 0x20340000, 0xF83E0000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,c 00100bbbaa11010XDBBBCCCCCC111110. */
+{ "ldw", 0x2034003E, 0xF83E003F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa10XAAAAAA. */
+{ "ldw", 0x10000100, 0xF8000180, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa10X111110. */
+{ "ldw", 0x1000013E, 0xF80001BF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di> a,limm 00010110000000000111D0010XAAAAAA. */
+{ "ldw", 0x16007100, 0xFFFFF780, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }},
+
+/* ldhZZ_H<.x><.di> 0,limm 00010110000000000111D0010X111110. */
+{ "ldw", 0x1600713E, 0xFFFFF7BF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,ximm 00100bbbaa11010XDBBB111100AAAAAA. */
+{ "ldw", 0x20340F00, 0xF83E0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,limm 00100bbbaa11010XDBBB111110AAAAAA. */
+{ "ldw", 0x20340F80, 0xF83E0FC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,limm,c 00100100aa11010XD111CCCCCCAAAAAA. */
+{ "ldw", 0x24347000, 0xFF3E7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,limm,c 00100110aa11010XD111CCCCCCAAAAAA. */
+{ "ldw", 0x26347000, 0xFF3E7000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,limm 00100bbbaa11010XDBBB111110111110. */
+{ "ldw", 0x20340FBE, 0xF83E0FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,limm,c 00100110aa11010XD111CCCCCC111110. */
+{ "ldw", 0x2634703E, 0xFF3E703F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,limm,s9 00010110ssssssssS111Daa10XAAAAAA. */
+{ "ldw", 0x16007100, 0xFF007180, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,limm,s9 00010110ssssssssS111Daa10X111110. */
+{ "ldw", 0x1600713E, 0xFF0071BF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldd<.aa><.di> a,b 00010bbb000000000BBBDaa110AAAAAA -> ldd a,[b,s9=0] */
+/* ldd<.aa><.di> a,b,s9 00010bbbssssssssSBBBDaa110AAAAAA -> ldd a,[b,s9] */
+/* ldd<.aa><.di> a,limm 00010110000000000111Daa110AAAAAA -> ldd a,[b=62,s9=0] */
+{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21 }},
+{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }},
+{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_DI20, C_AA21 }},
+
+/* ldd<.aa><.di> a,b,c 00100bbbaa110110DBBBCCCCCCAAAAAA -> ldd a,[b,c] */
+/* ldd<.aa><.di> a,b,limm 00100bbbaa110110DBBB111110AAAAAA -> ldd a,[b,c=62] */
+/* ldd<.aa><.di> a,limm,c 00100110aa110110D111CCCCCCAAAAAA -> ldd a,[b=62,c] */
+{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8 }},
+{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8 }},
+{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARC32, LOAD, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16, C_AA8 }},
+
+/* lddl<.aa> a,b 00010bbb000000000BBBq1101QAAAAAA -> lddl a,[b,s9=0] */
+/* lddl<.aa> a,b,s9 00010bbbssssssssSBBBq1101QAAAAAA -> lddl a,[b,s9] */
+/* lddl<.as> a,ximm 00010100000000000111q1101QAAAAAA -> lddl a,[b=60,s9=0] */
+/* lddl<.as> a,limm 00010110000000000111q1101QAAAAAA -> lddl a,[b=62,s9=0] */
+{ "lddl", 0x10000680, 0xF8FF8780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_AA_128S }},
+{ "lddl", 0x10000680, 0xF8000780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA_128S }},
+
+{ "lddl", 0x14007680, 0xFFFFF780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, XIMM, BRAKETdup }, { C_AS_128S }},
+{ "lddl", 0x16007680, 0xFFFFF780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_AS_128S }},
+
+/* lddl<.aa> a,b,c 00100bbb1111001QQBBBCCCCCCAAAAAA -> lddl a,[b,c] */
+/* lddl<.aa> a,b,ximm 00100bbb1111001QQBBB111100AAAAAA -> lddl a,[b,c=60] */
+/* lddl<.aa> a,b,limm 00100bbb1111001QQBBB111110AAAAAA -> lddl a,[b,c=62] */
+/* lddl<.as> a,ximm,c 001001001111001QQ111CCCCCCAAAAAA -> lddl a,[b=60,c] */
+/* lddl<.as> a,limm,c 001001101111001QQ111CCCCCCAAAAAA -> lddl a,[b=62,c] */
+{ "lddl", 0x20F20000, 0xF8FE0000, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_AA_128 }},
+
+{ "lddl", 0x20F20F00, 0xF8FE0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, XIMM, BRAKETdup }, { C_AA_128 }},
+{ "lddl", 0x20F20F80, 0xF8FE0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_AA_128 }},
+
+{ "lddl", 0x24F27000, 0xFFFE7000, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, XIMM, RC, BRAKETdup }, { C_AS_128 }},
+{ "lddl", 0x26F27000, 0xFFFE7000, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_AS_128 }},
+
+
+/* ldlZZ_L<.aa> a,b 00010bbb000000000BBB1aa001AAAAAA. */
+{ "ldl", 0x10000840, 0xF8FF89C0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldlZZ_L<.aa> 0,b 00010bbb000000000BBB1aa001111110. */
+{ "ldl", 0x1000087E, 0xF8FF89FF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldlZZ_L<.aa> a,b,c 00100bbbaa1100011BBBCCCCCCAAAAAA. */
+{ "ldl", 0x20318000, 0xF83F8000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L<.aa> 0,b,c 00100bbbaa1100011BBBCCCCCC111110. */
+{ "ldl", 0x2031803E, 0xF83F803F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L<.aa> a,b,s9 00010bbbssssssssSBBB1aa001AAAAAA. */
+{ "ldl", 0x10000840, 0xF80009C0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldlZZ_L<.aa> 0,b,s9 00010bbbssssssssSBBB1aa001111110. */
+{ "ldl", 0x1000087E, 0xF80009FF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldlZZ_L 0,limm 00010110000000000111100001111110. */
+{ "ldl", 0x1600787E, 0xFFFFFFFF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L }},
+
+/* ldlZZ_L a,limm 00010110000000000111100001AAAAAA. */
+{ "ldl", 0x16007840, 0xFFFFFFC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L }},
+
+/* ldlZZ_L<.aa> a,b,ximm 00100bbbaa1100011BBB111100AAAAAA. */
+{ "ldl", 0x20318F00, 0xF83F8FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L<.aa> a,b,limm 00100bbbaa1100011BBB111110AAAAAA. */
+{ "ldl", 0x20318F80, 0xF83F8FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L<.aa> 0,b,limm 00100bbbaa1100011BBB111110111110. */
+{ "ldl", 0x20318FBE, 0xF83F8FFF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L 0,limm,c 00100110001100011111CCCCCC111110. */
+{ "ldl", 0x2631F03E, 0xFFFFF03F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_L }},
+
+/* ldlZZ_L<.aa> a,ximm,c 00100100aa1100011111CCCCCCAAAAAA. */
+{ "ldl", 0x2431F000, 0xFF3FF000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_L , C_AA8 }},
+
+/* ldlZZ_L a,limm,c 00100110aa1100011111CCCCCCAAAAAA. */
+{ "ldl", 0x2631F000, 0xFF3FF000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LO32, RC, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L<.aa> a,limm,s9 00010110ssssssssS1111aa001AAAAAA. */
+{ "ldl", 0x16007840, 0xFF0079C0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LO32, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldlZZ_L<.aa> 0,limm,s9 00010110ssssssssS1111aa001111110. */
+{ "ldl", 0x1600787E, 0xFF0079FF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldb_sZZ_B a,b,c 01100bbbccc01aaa. */
+{ "ldb_s", 0x00006008, 0x0000F818,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_B }},
+
+/* ldb_sZZ_B c,b,u5 10001bbbcccuuuuu. */
+{ "ldb_s", 0x00008800, 0x0000F800,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B }},
+
+/* ldb_sZZ_B b,SP,u7 11000bbb001uuuuu. */
+{ "ldb_s", 0x0000C020, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B }},
+
+/* ldb_sZZ_B R0,GP,s9 1100101sssssssss. */
+{ "ldb_s", 0x0000CA00, 0x0000FE00,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM9_7_S, BRAKETdup }, { C_ZZ_B }},
+
+/* ldh_sZZ_H a,b,c 01100bbbccc10aaa. */
+{ "ldh_s", 0x00006010, 0x0000F818,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_H }},
+
+/* ldh_sZZ_H c,b,u6 10010bbbcccuuuuu. */
+{ "ldh_s", 0x00009000, 0x0000F800,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }},
+
+/* ldh_sZZ_H.X c,b,u6 10011bbbcccuuuuu. */
+{ "ldh_s", 0x00009800, 0x0000F800,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H, C_XHARD }},
+
+/* ldh_sZZ_H R0,GP,s10 1100110sssssssss. */
+{ "ldh_s", 0x0000CC00, 0x0000FE00,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { C_ZZ_H }},
+
+/* ld_s a,b,c 01100bbbccc00aaa. */
+{ "ld_s", 0x00006000, 0x0000F818,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
+
+/* ld_s.AS a,b,c 01001bbbccc00aaa. */
+{ "ld_s", 0x00004800, 0x0000F818,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, CD2, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_AS }},
+
+/* ld_s b,SP,u7 11000bbb000uuuuu. */
+{ "ld_s", 0x0000C000, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* ld_s c,b,u7 10000bbbcccuuuuu. */
+{ "ld_s", 0x00008000, 0x0000F800,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* ld_s b,PCL,u10 11010bbbuuuuuuuu. */
+{ "ld_s", 0x0000D000, 0x0000F800,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { RB_S, BRAKET, PCL_S, UIMM10_A32_8_S, BRAKETdup }, { 0 }},
+
+/* ld_s R0,GP,s11 1100100sssssssss. */
+{ "ld_s", 0x0000C800, 0x0000FE00,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM11_A32_7_S, BRAKETdup }, { 0 }},
+
+/* ld_s R1,GP,s11 01010SSSSSS00sss. */
+{ "ld_s", 0x00005000, 0x0000F818,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOAD, CD2, { R1_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }},
+
+/* leave_s u7 11000UUU110uuuu0. */
+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LEAVE, NONE, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }},
+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LEAVE, NONE, { BRAKET, R13_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }},
+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LEAVE, NONE, { UIMM7_11_S }, { 0 }},
+
+/* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000. */
+{ "llock", 0x202F0010, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LLOCK, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> 0,c 0010011000101111D111CCCCCC010000. */
+{ "llock", 0x262F7010, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LLOCK, NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> b,u6 00100bbb01101111DBBBuuuuuu010000. */
+{ "llock", 0x206F0010, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LLOCK, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> 0,u6 0010011001101111D111uuuuuu010000. */
+{ "llock", 0x266F7010, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LLOCK, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> b,limm 00100bbb00101111DBBB111110010000. */
+{ "llock", 0x202F0F90, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LLOCK, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> 0,limm 0010011000101111D111111110010000. */
+{ "llock", 0x262F7F90, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LLOCK, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* llockd<.di> b,c 00100bbb00101111DBBBCCCCCC010010. */
+{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARC32, LLOCK, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
+
+/* llockd<.di> b,limm 00100bbb00101111DBBB111110010010. */
+{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARC32, LLOCK, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
+
+/* llockl<.aq> RB,RC 01011bbb00101111FBBBcccccc010000. */
+{ "llockl", 0x582F0010, 0xF8FF003F, ARC_OPCODE_ARC64, LLOCK, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_AQ }},
+
+/* lr b,c 00100bbb00101010RBBBCCCCCCRRRRRR. */
+{ "lr", 0x202A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* lr 0,c 0010011000101010R111CCCCCCRRRRRR. */
+{ "lr", 0x262A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { ZA, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* lr b,u6 00100bbb01101010RBBBuuuuuu000000. */
+{ "lr", 0x206A0000, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* lr 0,u6 0010011001101010R111uuuuuu000000. */
+{ "lr", 0x266A7000, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* lr b,s12 00100bbb10101010RBBBssssssSSSSSS. */
+{ "lr", 0x20AA0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* lr 0,s12 0010011010101010R111ssssssSSSSSS. */
+{ "lr", 0x26AA7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { ZA, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* lr b,limm 00100bbb00101010RBBB111110RRRRRR. */
+{ "lr", 0x202A0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* lr 0,limm 0010011000101010R111111110RRRRRR. */
+{ "lr", 0x262A7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* lrl RB,RC 01011bbb001010100BBBccccccRRRRRR. */
+{ "lrl", 0x582A0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* lrl RB,u6 01011bbb011010100BBBuuuuuuRRRRRR. */
+{ "lrl", 0x586A0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* lrl RB,s12 01011bbb101010100BBBssssssSSSSSS. */
+{ "lrl", 0x58AA0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* lrl RB,ximm 01011bbb001010100BBB111100RRRRRR. */
+{ "lrl", 0x582A0F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, XIMM, BRAKETdup }, { 0 }},
+
+/* lrl RB,limm 01011bbb001010100BBB111110RRRRRR. */
+{ "lrl", 0x582A0F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* lsl16<.f> b,c 00101bbb00101111FBBBCCCCCC001010. */
+{ "lsl16", 0x282F000A, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* lsl16<.f> 0,c 0010111000101111F111CCCCCC001010. */
+{ "lsl16", 0x2E2F700A, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* lsl16<.f> b,u6 00101bbb01101111FBBBuuuuuu001010. */
+{ "lsl16", 0x286F000A, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* lsl16<.f> 0,u6 0010111001101111F111uuuuuu001010. */
+{ "lsl16", 0x2E6F700A, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsl16<.f> b,limm 00101bbb00101111FBBB111110001010. */
+{ "lsl16", 0x282F0F8A, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* lsl16<.f> 0,limm 0010111000101111F111111110001010. */
+{ "lsl16", 0x2E2F7F8A, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* lsl8<.f> b,c 00101bbb00101111FBBBCCCCCC001111. */
+{ "lsl8", 0x282F000F, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* lsl8<.f> 0,c 0010111000101111F111CCCCCC001111. */
+{ "lsl8", 0x2E2F700F, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* lsl8<.f> b,u6 00101bbb01101111FBBBuuuuuu001111. */
+{ "lsl8", 0x286F000F, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* lsl8<.f> 0,u6 0010111001101111F111uuuuuu001111. */
+{ "lsl8", 0x2E6F700F, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsl8<.f> b,limm 00101bbb00101111FBBB111110001111. */
+{ "lsl8", 0x282F0F8F, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* lsl8<.f> 0,limm 0010111000101111F111111110001111. */
+{ "lsl8", 0x2E2F7F8F, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* lsr<.f> b,c 00100bbb00101111FBBBCCCCCC000010. */
+{ "lsr", 0x202F0002, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* lsr<.f> 0,c 0010011000101111F111CCCCCC000010. */
+{ "lsr", 0x262F7002, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* lsr<.f> a,b,c 00101bbb00000001FBBBCCCCCCAAAAAA. */
+{ "lsr", 0x28010000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* lsr<.f> 0,b,c 00101bbb00000001FBBBCCCCCC111110. */
+{ "lsr", 0x2801003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* lsr<.f><.cc> b,b,c 00101bbb11000001FBBBCCCCCC0QQQQQ. */
+{ "lsr", 0x28C10000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* lsr<.f> b,u6 00100bbb01101111FBBBuuuuuu000010. */
+{ "lsr", 0x206F0002, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> 0,u6 0010011001101111F111uuuuuu000010. */
+{ "lsr", 0x266F7002, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> a,b,u6 00101bbb01000001FBBBuuuuuuAAAAAA. */
+{ "lsr", 0x28410000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> 0,b,u6 00101bbb01000001FBBBuuuuuu111110. */
+{ "lsr", 0x2841003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* lsr<.f><.cc> b,b,u6 00101bbb11000001FBBBuuuuuu1QQQQQ. */
+{ "lsr", 0x28C10020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsr<.f> b,b,s12 00101bbb10000001FBBBssssssSSSSSS. */
+{ "lsr", 0x28810000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* lsr<.f> b,limm 00100bbb00101111FBBB111110000010. */
+{ "lsr", 0x202F0F82, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* lsr<.f> 0,limm 0010011000101111F111111110000010. */
+{ "lsr", 0x262F7F82, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* lsr<.f> a,limm,c 0010111000000001F111CCCCCCAAAAAA. */
+{ "lsr", 0x2E017000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* lsr<.f> a,b,limm 00101bbb00000001FBBB111110AAAAAA. */
+{ "lsr", 0x28010F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* lsr<.f> 0,limm,c 0010111000000001F111CCCCCC111110. */
+{ "lsr", 0x2E01703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* lsr<.f> 0,b,limm 00101bbb00000001FBBB111110111110. */
+{ "lsr", 0x28010FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* lsr<.f><.cc> b,b,limm 00101bbb11000001FBBB1111100QQQQQ. */
+{ "lsr", 0x28C10F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* lsr<.f><.cc> 0,limm,c 0010111011000001F111CCCCCC0QQQQQ. */
+{ "lsr", 0x2EC17000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* lsr<.f> a,limm,u6 0010111001000001F111uuuuuuAAAAAA. */
+{ "lsr", 0x2E417000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> 0,limm,u6 0010111001000001F111uuuuuu111110. */
+{ "lsr", 0x2E41703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsr<.f><.cc> 0,limm,u6 0010111011000001F111uuuuuu1QQQQQ. */
+{ "lsr", 0x2EC17020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsr<.f> 0,limm,s12 0010111010000001F111ssssssSSSSSS. */
+{ "lsr", 0x2E817000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* lsr<.f> a,limm,limm 0010111000000001F111111110AAAAAA. */
+{ "lsr", 0x2E017F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* lsr<.f> 0,limm,limm 0010111000000001F111111110111110. */
+{ "lsr", 0x2E017FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* lsr<.f><.cc> 0,limm,limm 0010111011000001F1111111100QQQQQ. */
+{ "lsr", 0x2EC17F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* lsr16<.f> b,c 00101bbb00101111FBBBCCCCCC001011. */
+{ "lsr16", 0x282F000B, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* lsr16<.f> 0,c 0010111000101111F111CCCCCC001011. */
+{ "lsr16", 0x2E2F700B, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* lsr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001011. */
+{ "lsr16", 0x286F000B, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* lsr16<.f> 0,u6 0010111001101111F111uuuuuu001011. */
+{ "lsr16", 0x2E6F700B, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsr16<.f> b,limm 00101bbb00101111FBBB111110001011. */
+{ "lsr16", 0x282F0F8B, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* lsr16<.f> 0,limm 0010111000101111F111111110001011. */
+{ "lsr16", 0x2E2F7F8B, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* lsr8<.f> b,c 00101bbb00101111FBBBCCCCCC001110. */
+{ "lsr8", 0x282F000E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* lsr8<.f> 0,c 0010111000101111F111CCCCCC001110. */
+{ "lsr8", 0x2E2F700E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* lsr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001110. */
+{ "lsr8", 0x286F000E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* lsr8<.f> 0,u6 0010111001101111F111uuuuuu001110. */
+{ "lsr8", 0x2E6F700E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsr8<.f> b,limm 00101bbb00101111FBBB111110001110. */
+{ "lsr8", 0x282F0F8E, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* lsr8<.f> 0,limm 0010111000101111F111111110001110. */
+{ "lsr8", 0x2E2F7F8E, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* lsrl<.f> RA,RB,RC 01011bbb00100001FBBBccccccaaaaaa. */
+{ "lsrl", 0x58210000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* lsrl<.f> 0,RB,RC 01011bbb00100001FBBBcccccc111110. */
+{ "lsrl", 0x5821003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* lsrl<.f><.cc> RB,RB,RC 01011bbb11100001FBBBcccccc0QQQQQ. */
+{ "lsrl", 0x58E10000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* lsrl<.f> RA,RB,u6 01011bbb01100001FBBBuuuuuuaaaaaa. */
+{ "lsrl", 0x58610000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f> 0,RB,u6 01011bbb01100001FBBBuuuuuu111110. */
+{ "lsrl", 0x5861003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f><.cc> RB,RB,u6 01011bbb11100001FBBBuuuuuu1QQQQQ. */
+{ "lsrl", 0x58E10020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsrl<.f> RB,RB,s12 01011bbb10100001FBBBssssssSSSSSS. */
+{ "lsrl", 0x58A10000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* lsrl<.f> RA,ximm,RC 0101110000100001F111ccccccaaaaaa. */
+{ "lsrl", 0x5C217000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* lsrl<.f> RA,RB,ximm 01011bbb00100001FBBB111100aaaaaa. */
+{ "lsrl", 0x58210F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* lsrl<.f> 0,ximm,RC 0101110000100001F111cccccc111110. */
+{ "lsrl", 0x5C21703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* lsrl<.f> 0,RB,ximm 01011bbb00100001FBBB111100111110. */
+{ "lsrl", 0x58210F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* lsrl<.f><.cc> 0,ximm,RC 0101110011100001F111cccccc0QQQQQ. */
+{ "lsrl", 0x5CE17000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* lsrl<.f><.cc> RB,RB,ximm 01011bbb11100001FBBB1111000QQQQQ. */
+{ "lsrl", 0x58E10F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* lsrl<.f> RA,ximm,u6 0101110001100001F111uuuuuuaaaaaa. */
+{ "lsrl", 0x5C617000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f> 0,ximm,u6 0101110001100001F111uuuuuu111110. */
+{ "lsrl", 0x5C61703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f><.cc> 0,ximm,u6 0101110011100001F111uuuuuu1QQQQQ. */
+{ "lsrl", 0x5CE17020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsrl<.f> RA,limm,RC 0101111000100001F111ccccccaaaaaa. */
+{ "lsrl", 0x5E217000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* lsrl<.f> RA,RB,limm 01011bbb00100001FBBB111110aaaaaa. */
+{ "lsrl", 0x58210F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* lsrl<.f> 0,limm,RC 0101111000100001F111cccccc111110. */
+{ "lsrl", 0x5E21703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* lsrl<.f> 0,RB,limm 01011bbb00100001FBBB111110111110. */
+{ "lsrl", 0x58210FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* lsrl<.f><.cc> 0,limm,RC 0101111011100001F111cccccc0QQQQQ. */
+{ "lsrl", 0x5EE17000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* lsrl<.f><.cc> RB,RB,limm 01011bbb11100001FBBB1111100QQQQQ. */
+{ "lsrl", 0x58E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* lsrl<.f> RA,limm,u6 0101111001100001F111uuuuuuaaaaaa. */
+{ "lsrl", 0x5E617000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f> 0,limm,u6 0101111001100001F111uuuuuu111110. */
+{ "lsrl", 0x5E61703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f><.cc> 0,limm,u6 0101111011100001F111uuuuuu1QQQQQ. */
+{ "lsrl", 0x5EE17020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsrl<.f> 0,ximm,s12 0101110010100001F111ssssssSSSSSS. */
+{ "lsrl", 0x5CA17000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* lsrl<.f> 0,limm,s12 0101111010100001F111ssssssSSSSSS. */
+{ "lsrl", 0x5EA17000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* lsrl<.f> RA,ximm,ximm 0101110000100001F111111100aaaaaa. */
+{ "lsrl", 0x5C217F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* lsrl<.f> 0,ximm,ximm 0101110000100001F111111100111110. */
+{ "lsrl", 0x5C217F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* lsrl<.f><.cc> 0,ximm,ximm 0101110011100001F1111111000QQQQQ. */
+{ "lsrl", 0x5CE17F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* lsrl<.f> RA,limm,limm 0101111000100001F111111110aaaaaa. */
+{ "lsrl", 0x5E217F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* lsrl<.f> 0,limm,limm 0101111000100001F111111110111110. */
+{ "lsrl", 0x5E217FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* lsrl<.f><.cc> 0,limm,limm 0101111011100001F1111111100QQQQQ. */
+{ "lsrl", 0x5EE17F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* lsr_s b,c 01111bbbccc11101. */
+{ "lsr_s", 0x0000781D, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* lsr_s b,b,c 01111bbbccc11001. */
+{ "lsr_s", 0x00007819, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* lsr_s b,b,u5 10111bbb001uuuuu. */
+{ "lsr_s", 0x0000B820, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* lstl<.f> RB,RC 01011bbb00101111FBBBcccccc000010. */
+{ "lstl", 0x582F0002, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* lstl<.f> 0,RC 0101111000101111F111cccccc000010. */
+{ "lstl", 0x5E2F7002, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* lstl<.f> RB,u6 01011bbb01101111FBBBuuuuuu000010. */
+{ "lstl", 0x586F0002, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* lstl<.f> 0,u6 0101111001101111F111uuuuuu000010. */
+{ "lstl", 0x5E6F7002, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* lstl<.f> RB,ximm 01011bbb00101111FBBB111100000010. */
+{ "lstl", 0x582F0F02, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* lstl<.f> 0,ximm 0101111000101111F111111100000010. */
+{ "lstl", 0x5E2F7F02, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* lstl<.f> RB,limm 01011bbb00101111FBBB111110000010. */
+{ "lstl", 0x582F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* lstl<.f> 0,limm 0101111000101111F111111110000010. */
+{ "lstl", 0x5E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* mac<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA. */
+{ "mac", 0x280E0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mac<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110. */
+{ "mac", 0x280E003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* mac<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ. */
+{ "mac", 0x28CE0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mac<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA. */
+{ "mac", 0x284E0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mac<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110. */
+{ "mac", 0x284E003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mac<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ. */
+{ "mac", 0x28CE0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mac<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS. */
+{ "mac", 0x288E0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mac<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA. */
+{ "mac", 0x2E0E7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mac<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA. */
+{ "mac", 0x280E0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mac<.f> 0,limm,c 0010111000001110F111CCCCCC111110. */
+{ "mac", 0x2E0E703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* mac<.f> 0,b,limm 00101bbb00001110FBBB111110111110. */
+{ "mac", 0x280E0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* mac<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ. */
+{ "mac", 0x28CE0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mac<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ. */
+{ "mac", 0x2ECE7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mac<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA. */
+{ "mac", 0x2E4E7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mac<.f> 0,limm,u6 0010111001001110F111uuuuuu111110. */
+{ "mac", 0x2E4E703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mac<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ. */
+{ "mac", 0x2ECE7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mac<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS. */
+{ "mac", 0x2E8E7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mac<.f> a,limm,limm 0010111000001110F111111110AAAAAA. */
+{ "mac", 0x2E0E7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mac<.f> 0,limm,limm 0010111000001110F111111110111110. */
+{ "mac", 0x2E0E7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mac<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ. */
+{ "mac", 0x2ECE7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macd<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA. */
+{ "macd", 0x281A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { C_F }},
+
+/* macd<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110. */
+{ "macd", 0x281A003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* macd<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ. */
+{ "macd", 0x28DA0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macd<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA. */
+{ "macd", 0x285A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macd<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110. */
+{ "macd", 0x285A003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macd<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ. */
+{ "macd", 0x28DA0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macd<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS. */
+{ "macd", 0x289A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macd<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA. */
+{ "macd", 0x2E1A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macd<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA. */
+{ "macd", 0x281A0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macd<.f> 0,limm,c 0010111000011010F111CCCCCC111110. */
+{ "macd", 0x2E1A703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* macd<.f> 0,b,limm 00101bbb00011010FBBB111110111110. */
+{ "macd", 0x281A0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* macd<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ. */
+{ "macd", 0x28DA0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macd<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ. */
+{ "macd", 0x2EDA7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macd<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA. */
+{ "macd", 0x2E5A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macd<.f> 0,limm,u6 0010111001011010F111uuuuuu111110. */
+{ "macd", 0x2E5A703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macd<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ. */
+{ "macd", 0x2EDA7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macd<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS. */
+{ "macd", 0x2E9A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macd<.f> a,limm,limm 0010111000011010F111111110AAAAAA. */
+{ "macd", 0x2E1A7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macd<.f> 0,limm,limm 0010111000011010F111111110111110. */
+{ "macd", 0x2E1A7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macd<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ. */
+{ "macd", 0x2EDA7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macdu<.f> a,b,c 00101bbb00011011FBBBCCCCCCAAAAAA. */
+{ "macdu", 0x281B0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { C_F }},
+
+/* macdu<.f> 0,b,c 00101bbb00011011FBBBCCCCCC111110. */
+{ "macdu", 0x281B003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* macdu<.f><.cc> b,b,c 00101bbb11011011FBBBCCCCCC0QQQQQ. */
+{ "macdu", 0x28DB0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macdu<.f> a,b,u6 00101bbb01011011FBBBuuuuuuAAAAAA. */
+{ "macdu", 0x285B0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macdu<.f> 0,b,u6 00101bbb01011011FBBBuuuuuu111110. */
+{ "macdu", 0x285B003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macdu<.f><.cc> b,b,u6 00101bbb11011011FBBBuuuuuu1QQQQQ. */
+{ "macdu", 0x28DB0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdu<.f> b,b,s12 00101bbb10011011FBBBssssssSSSSSS. */
+{ "macdu", 0x289B0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macdu<.f> a,limm,c 0010111000011011F111CCCCCCAAAAAA. */
+{ "macdu", 0x2E1B7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macdu<.f> a,b,limm 00101bbb00011011FBBB111110AAAAAA. */
+{ "macdu", 0x281B0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macdu<.f> 0,limm,c 0010111000011011F111CCCCCC111110. */
+{ "macdu", 0x2E1B703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* macdu<.f> 0,b,limm 00101bbb00011011FBBB111110111110. */
+{ "macdu", 0x281B0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* macdu<.f><.cc> b,b,limm 00101bbb11011011FBBB1111100QQQQQ. */
+{ "macdu", 0x28DB0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macdu<.f><.cc> 0,limm,c 0010111011011011F111CCCCCC0QQQQQ. */
+{ "macdu", 0x2EDB7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macdu<.f> a,limm,u6 0010111001011011F111uuuuuuAAAAAA. */
+{ "macdu", 0x2E5B7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdu<.f> 0,limm,u6 0010111001011011F111uuuuuu111110. */
+{ "macdu", 0x2E5B703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdu<.f><.cc> 0,limm,u6 0010111011011011F111uuuuuu1QQQQQ. */
+{ "macdu", 0x2EDB7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdu<.f> 0,limm,s12 0010111010011011F111ssssssSSSSSS. */
+{ "macdu", 0x2E9B7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macdu<.f> a,limm,limm 0010111000011011F111111110AAAAAA. */
+{ "macdu", 0x2E1B7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macdu<.f> 0,limm,limm 0010111000011011F111111110111110. */
+{ "macdu", 0x2E1B7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macdu<.f><.cc> 0,limm,limm 0010111011011011F1111111100QQQQQ. */
+{ "macdu", 0x2EDB7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macu<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA. */
+{ "macu", 0x280F0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* macu<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110. */
+{ "macu", 0x280F003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* macu<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ. */
+{ "macu", 0x28CF0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macu<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA. */
+{ "macu", 0x284F0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macu<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110. */
+{ "macu", 0x284F003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macu<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ. */
+{ "macu", 0x28CF0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macu<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS. */
+{ "macu", 0x288F0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macu<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA. */
+{ "macu", 0x2E0F7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macu<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA. */
+{ "macu", 0x280F0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macu<.f> 0,limm,c 0010111000001111F111CCCCCC111110. */
+{ "macu", 0x2E0F703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* macu<.f> 0,b,limm 00101bbb00001111FBBB111110111110. */
+{ "macu", 0x280F0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* macu<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ. */
+{ "macu", 0x28CF0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macu<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ. */
+{ "macu", 0x2ECF7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macu<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA. */
+{ "macu", 0x2E4F7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macu<.f> 0,limm,u6 0010111001001111F111uuuuuu111110. */
+{ "macu", 0x2E4F703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macu<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ. */
+{ "macu", 0x2ECF7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macu<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS. */
+{ "macu", 0x2E8F7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macu<.f> a,limm,limm 0010111000001111F111111110AAAAAA. */
+{ "macu", 0x2E0F7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macu<.f> 0,limm,limm 0010111000001111F111111110111110. */
+{ "macu", 0x2E0F7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macu<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ. */
+{ "macu", 0x2ECF7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* max<.f> a,b,c 00100bbb00001000FBBBCCCCCCAAAAAA. */
+{ "max", 0x20080000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* max<.f> 0,b,c 00100bbb00001000FBBBCCCCCC111110. */
+{ "max", 0x2008003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* max<.f><.cc> b,b,c 00100bbb11001000FBBBCCCCCC0QQQQQ. */
+{ "max", 0x20C80000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* max<.f> a,b,u6 00100bbb01001000FBBBuuuuuuAAAAAA. */
+{ "max", 0x20480000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* max<.f> 0,b,u6 00100bbb01001000FBBBuuuuuu111110. */
+{ "max", 0x2048003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* max<.f><.cc> b,b,u6 00100bbb11001000FBBBuuuuuu1QQQQQ. */
+{ "max", 0x20C80020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* max<.f> b,b,s12 00100bbb10001000FBBBssssssSSSSSS. */
+{ "max", 0x20880000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* max<.f> a,limm,c 0010011000001000F111CCCCCCAAAAAA. */
+{ "max", 0x26087000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* max<.f> a,b,limm 00100bbb00001000FBBB111110AAAAAA. */
+{ "max", 0x20080F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* max<.f> 0,limm,c 0010011000001000F111CCCCCC111110. */
+{ "max", 0x2608703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* max<.f> 0,b,limm 00100bbb00001000FBBB111110111110. */
+{ "max", 0x20080FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* max<.f><.cc> b,b,limm 00100bbb11001000FBBB1111100QQQQQ. */
+{ "max", 0x20C80F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* max<.f><.cc> 0,limm,c 0010011011001000F111CCCCCC0QQQQQ. */
+{ "max", 0x26C87000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* max<.f> a,limm,u6 0010011001001000F111uuuuuuAAAAAA. */
+{ "max", 0x26487000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* max<.f> 0,limm,u6 0010011001001000F111uuuuuu111110. */
+{ "max", 0x2648703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* max<.f><.cc> 0,limm,u6 0010011011001000F111uuuuuu1QQQQQ. */
+{ "max", 0x26C87020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* max<.f> 0,limm,s12 0010011010001000F111ssssssSSSSSS. */
+{ "max", 0x26887000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* max<.f> a,limm,limm 0010011000001000F111111110AAAAAA. */
+{ "max", 0x26087F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* max<.f> 0,limm,limm 0010011000001000F111111110111110. */
+{ "max", 0x26087FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* max<.f><.cc> 0,limm,limm 0010011011001000F1111111100QQQQQ. */
+{ "max", 0x26C87F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* maxl<.f> RA,RB,RC 01011bbb00001000FBBBccccccaaaaaa. */
+{ "maxl", 0x58080000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* maxl<.f> 0,RB,RC 01011bbb00001000FBBBcccccc111110. */
+{ "maxl", 0x5808003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* maxl<.f><.cc> RB,RB,RC 01011bbb11001000FBBBcccccc0QQQQQ. */
+{ "maxl", 0x58C80000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* maxl<.f> RA,RB,u6 01011bbb01001000FBBBuuuuuuaaaaaa. */
+{ "maxl", 0x58480000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* maxl<.f> 0,RB,u6 01011bbb01001000FBBBuuuuuu111110. */
+{ "maxl", 0x5848003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* maxl<.f><.cc> RB,RB,u6 01011bbb11001000FBBBuuuuuu1QQQQQ. */
+{ "maxl", 0x58C80020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* maxl<.f> RB,RB,s12 01011bbb10001000FBBBssssssSSSSSS. */
+{ "maxl", 0x58880000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* maxl<.f> RA,ximm,RC 0101110000001000F111ccccccaaaaaa. */
+{ "maxl", 0x5C087000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* maxl<.f> RA,RB,ximm 01011bbb00001000FBBB111100aaaaaa. */
+{ "maxl", 0x58080F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* maxl<.f> 0,ximm,RC 0101110000001000F111cccccc111110. */
+{ "maxl", 0x5C08703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* maxl<.f> 0,RB,ximm 01011bbb00001000FBBB111100111110. */
+{ "maxl", 0x58080F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* maxl<.f><.cc> 0,ximm,RC 0101110011001000F111cccccc0QQQQQ. */
+{ "maxl", 0x5CC87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* maxl<.f><.cc> RB,RB,ximm 01011bbb11001000FBBB1111000QQQQQ. */
+{ "maxl", 0x58C80F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* maxl<.f> RA,ximm,u6 0101110001001000F111uuuuuuaaaaaa. */
+{ "maxl", 0x5C487000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* maxl<.f> 0,ximm,u6 0101110001001000F111uuuuuu111110. */
+{ "maxl", 0x5C48703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* maxl<.f><.cc> 0,ximm,u6 0101110011001000F111uuuuuu1QQQQQ. */
+{ "maxl", 0x5CC87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* maxl<.f> RA,limm,RC 0101111000001000F111ccccccaaaaaa. */
+{ "maxl", 0x5E087000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* maxl<.f> RA,RB,limm 01011bbb00001000FBBB111110aaaaaa. */
+{ "maxl", 0x58080F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* maxl<.f> 0,limm,RC 0101111000001000F111cccccc111110. */
+{ "maxl", 0x5E08703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* maxl<.f> 0,RB,limm 01011bbb00001000FBBB111110111110. */
+{ "maxl", 0x58080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* maxl<.f><.cc> 0,limm,RC 0101111011001000F111cccccc0QQQQQ. */
+{ "maxl", 0x5EC87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* maxl<.f><.cc> RB,RB,limm 01011bbb11001000FBBB1111100QQQQQ. */
+{ "maxl", 0x58C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* maxl<.f> RA,limm,u6 0101111001001000F111uuuuuuaaaaaa. */
+{ "maxl", 0x5E487000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* maxl<.f> 0,limm,u6 0101111001001000F111uuuuuu111110. */
+{ "maxl", 0x5E48703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* maxl<.f><.cc> 0,limm,u6 0101111011001000F111uuuuuu1QQQQQ. */
+{ "maxl", 0x5EC87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* maxl<.f> 0,ximm,s12 0101110010001000F111ssssssSSSSSS. */
+{ "maxl", 0x5C887000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* maxl<.f> 0,limm,s12 0101111010001000F111ssssssSSSSSS. */
+{ "maxl", 0x5E887000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* maxl<.f> RA,ximm,ximm 0101110000001000F111111100aaaaaa. */
+{ "maxl", 0x5C087F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* maxl<.f> 0,ximm,ximm 0101110000001000F111111100111110. */
+{ "maxl", 0x5C087F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* maxl<.f><.cc> 0,ximm,ximm 0101110011001000F1111111000QQQQQ. */
+{ "maxl", 0x5CC87F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* maxl<.f> RA,limm,limm 0101111000001000F111111110aaaaaa. */
+{ "maxl", 0x5E087F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* maxl<.f> 0,limm,limm 0101111000001000F111111110111110. */
+{ "maxl", 0x5E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* maxl<.f><.cc> 0,limm,limm 0101111011001000F1111111100QQQQQ. */
+{ "maxl", 0x5EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* min<.f> a,b,c 00100bbb00001001FBBBCCCCCCAAAAAA. */
+{ "min", 0x20090000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* min<.f> 0,b,c 00100bbb00001001FBBBCCCCCC111110. */
+{ "min", 0x2009003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* min<.f><.cc> b,b,c 00100bbb11001001FBBBCCCCCC0QQQQQ. */
+{ "min", 0x20C90000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* min<.f> a,b,u6 00100bbb01001001FBBBuuuuuuAAAAAA. */
+{ "min", 0x20490000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* min<.f> 0,b,u6 00100bbb01001001FBBBuuuuuu111110. */
+{ "min", 0x2049003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* min<.f><.cc> b,b,u6 00100bbb11001001FBBBuuuuuu1QQQQQ. */
+{ "min", 0x20C90020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* min<.f> b,b,s12 00100bbb10001001FBBBssssssSSSSSS. */
+{ "min", 0x20890000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* min<.f> a,limm,c 0010011000001001F111CCCCCCAAAAAA. */
+{ "min", 0x26097000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* min<.f> a,b,limm 00100bbb00001001FBBB111110AAAAAA. */
+{ "min", 0x20090F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* min<.f> 0,limm,c 0010011000001001F111CCCCCC111110. */
+{ "min", 0x2609703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* min<.f> 0,b,limm 00100bbb00001001FBBB111110111110. */
+{ "min", 0x20090FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* min<.f><.cc> b,b,limm 00100bbb11001001FBBB1111100QQQQQ. */
+{ "min", 0x20C90F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* min<.f><.cc> 0,limm,c 0010011011001001F111CCCCCC0QQQQQ. */
+{ "min", 0x26C97000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* min<.f> a,limm,u6 0010011001001001F111uuuuuuAAAAAA. */
+{ "min", 0x26497000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* min<.f> 0,limm,u6 0010011001001001F111uuuuuu111110. */
+{ "min", 0x2649703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* min<.f><.cc> 0,limm,u6 0010011011001001F111uuuuuu1QQQQQ. */
+{ "min", 0x26C97020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* min<.f> 0,limm,s12 0010011010001001F111ssssssSSSSSS. */
+{ "min", 0x26897000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* min<.f> a,limm,limm 0010011000001001F111111110AAAAAA. */
+{ "min", 0x26097F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* min<.f> 0,limm,limm 0010011000001001F111111110111110. */
+{ "min", 0x26097FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* min<.f><.cc> 0,limm,limm 0010011011001001F1111111100QQQQQ. */
+{ "min", 0x26C97F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* minl<.f> RA,RB,RC 01011bbb00001001FBBBccccccaaaaaa. */
+{ "minl", 0x58090000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* minl<.f> 0,RB,RC 01011bbb00001001FBBBcccccc111110. */
+{ "minl", 0x5809003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* minl<.f><.cc> RB,RB,RC 01011bbb11001001FBBBcccccc0QQQQQ. */
+{ "minl", 0x58C90000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* minl<.f> RA,RB,u6 01011bbb01001001FBBBuuuuuuaaaaaa. */
+{ "minl", 0x58490000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* minl<.f> 0,RB,u6 01011bbb01001001FBBBuuuuuu111110. */
+{ "minl", 0x5849003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* minl<.f><.cc> RB,RB,u6 01011bbb11001001FBBBuuuuuu1QQQQQ. */
+{ "minl", 0x58C90020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* minl<.f> RB,RB,s12 01011bbb10001001FBBBssssssSSSSSS. */
+{ "minl", 0x58890000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* minl<.f> RA,ximm,RC 0101110000001001F111ccccccaaaaaa. */
+{ "minl", 0x5C097000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* minl<.f> RA,RB,ximm 01011bbb00001001FBBB111100aaaaaa. */
+{ "minl", 0x58090F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* minl<.f> 0,ximm,RC 0101110000001001F111cccccc111110. */
+{ "minl", 0x5C09703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* minl<.f> 0,RB,ximm 01011bbb00001001FBBB111100111110. */
+{ "minl", 0x58090F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* minl<.f><.cc> 0,ximm,RC 0101110011001001F111cccccc0QQQQQ. */
+{ "minl", 0x5CC97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* minl<.f><.cc> RB,RB,ximm 01011bbb11001001FBBB1111000QQQQQ. */
+{ "minl", 0x58C90F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* minl<.f> RA,ximm,u6 0101110001001001F111uuuuuuaaaaaa. */
+{ "minl", 0x5C497000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* minl<.f> 0,ximm,u6 0101110001001001F111uuuuuu111110. */
+{ "minl", 0x5C49703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* minl<.f><.cc> 0,ximm,u6 0101110011001001F111uuuuuu1QQQQQ. */
+{ "minl", 0x5CC97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* minl<.f> RA,limm,RC 0101111000001001F111ccccccaaaaaa. */
+{ "minl", 0x5E097000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* minl<.f> RA,RB,limm 01011bbb00001001FBBB111110aaaaaa. */
+{ "minl", 0x58090F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* minl<.f> 0,limm,RC 0101111000001001F111cccccc111110. */
+{ "minl", 0x5E09703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* minl<.f> 0,RB,limm 01011bbb00001001FBBB111110111110. */
+{ "minl", 0x58090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* minl<.f><.cc> 0,limm,RC 0101111011001001F111cccccc0QQQQQ. */
+{ "minl", 0x5EC97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* minl<.f><.cc> RB,RB,limm 01011bbb11001001FBBB1111100QQQQQ. */
+{ "minl", 0x58C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* minl<.f> RA,limm,u6 0101111001001001F111uuuuuuaaaaaa. */
+{ "minl", 0x5E497000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* minl<.f> 0,limm,u6 0101111001001001F111uuuuuu111110. */
+{ "minl", 0x5E49703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* minl<.f><.cc> 0,limm,u6 0101111011001001F111uuuuuu1QQQQQ. */
+{ "minl", 0x5EC97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* minl<.f> 0,ximm,s12 0101110010001001F111ssssssSSSSSS. */
+{ "minl", 0x5C897000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* minl<.f> 0,limm,s12 0101111010001001F111ssssssSSSSSS. */
+{ "minl", 0x5E897000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* minl<.f> RA,ximm,ximm 0101110000001001F111111100aaaaaa. */
+{ "minl", 0x5C097F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* minl<.f> 0,ximm,ximm 0101110000001001F111111100111110. */
+{ "minl", 0x5C097F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* minl<.f><.cc> 0,ximm,ximm 0101110011001001F1111111000QQQQQ. */
+{ "minl", 0x5CC97F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* minl<.f> RA,limm,limm 0101111000001001F111111110aaaaaa. */
+{ "minl", 0x5E097F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* minl<.f> 0,limm,limm 0101111000001001F111111110111110. */
+{ "minl", 0x5E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* minl<.f><.cc> 0,limm,limm 0101111011001001F1111111100QQQQQ. */
+{ "minl", 0x5EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* nop 00100110010010100111000000000000. */
+{ "nop", 0x264A7000, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR. */
+{ "mov", 0x200A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { RB, RC }, { C_F }},
+
+/* mov<.f> 0,c 0010011000001010F111CCCCCCRRRRRR. */
+{ "mov", 0x260A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RC }, { C_F }},
+
+/* mov<.f><.cc> b,c 00100bbb11001010FBBBCCCCCC0QQQQQ. */
+{ "mov", 0x20CA0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { RB, RC }, { C_F, C_CC }},
+
+/* mov<.f><.cc> 0,c 0010011011001010F111CCCCCC0QQQQQ. */
+{ "mov", 0x26CA7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RC }, { C_F, C_CC }},
+
+/* mov<.f> b,u6 00100bbb01001010FBBBuuuuuuRRRRRR. */
+{ "mov", 0x204A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* mov<.f> 0,u6 0010011001001010F111uuuuuuRRRRRR. */
+{ "mov", 0x264A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
+{ "mov", 0x20CA0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { RB, UIMM6_20 }, { C_F, C_CC }},
+
+/* mov<.f><.cc> 0,u6 0010011011001010F111uuuuuu1QQQQQ. */
+{ "mov", 0x26CA7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, UIMM6_20 }, { C_F, C_CC }},
+
+/* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
+{ "mov", 0x208A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { RB, SIMM12_20 }, { C_F }},
+
+/* mov<.f> 0,s12 0010011010001010F111ssssssSSSSSS. */
+{ "mov", 0x268A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, SIMM12_20 }, { C_F }},
+
+/* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
+{ "mov", 0x200A0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { RB, LIMM }, { C_F }},
+
+/* mov<.f> 0,limm 0010011000001010F111111110RRRRRR. */
+{ "mov", 0x260A7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM }, { C_F }},
+
+/* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
+{ "mov", 0x20CA0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { RB, LIMM }, { C_F, C_CC }},
+
+/* mov<.f><.cc> 0,limm 0010011011001010F1111111100QQQQQ. */
+{ "mov", 0x26CA7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM }, { C_F, C_CC }},
+
+/* movhl RB,RC 01011bbb000010110BBBccccccRRRRRR. */
+{ "movhl", 0x580B0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* movhl<.cc> RB,RC 01011bbb110010110BBBcccccc0QQQQQ. */
+{ "movhl", 0x58CB0000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* movhl RB,u6 01011bbb010010110BBBuuuuuuRRRRRR. */
+{ "movhl", 0x584B0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* movhl<.cc> RB,u6 01011bbb110010110BBBuuuuuu1QQQQQ. */
+{ "movhl", 0x58CB0020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* movhl RB,s12 01011bbb100010110BBBssssssSSSSSS. */
+{ "movhl", 0x588B0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* movhl RB,limm 01011bbb000010110BBB111110RRRRRR. */
+{ "movhl", 0x580B0F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, HI32 }, { 0 }},
+
+/* movhl<.cc> RB,limm 01011bbb110010110BBB1111100QQQQQ. */
+{ "movhl", 0x58CB0F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, HI32 }, { C_CC }},
+
+/* movhl_s h,limm 01110000hhh010HH. */
+{ "movhl_s", 0x00007008, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, HI32 }, { 0 }},
+
+/* movl<.f> RB,RC 01011bbb00001010FBBBccccccRRRRRR. */
+{ "movl", 0x580A0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* movl<.f><.cc> RB,RC 01011bbb11001010FBBBcccccc0QQQQQ. */
+{ "movl", 0x58CA0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F, C_CC }},
+
+/* movl<.f> RB,u6 01011bbb01001010FBBBuuuuuuRRRRRR. */
+{ "movl", 0x584A0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* movl<.f><.cc> RB,u6 01011bbb11001010FBBBuuuuuu1QQQQQ. */
+{ "movl", 0x58CA0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F, C_CC }},
+
+/* movl<.f> RB,s12 01011bbb10001010FBBBssssssSSSSSS. */
+{ "movl", 0x588A0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { C_F }},
+
+/* movl<.f> RB,ximm 01011bbb00001010FBBB111100RRRRRR. */
+{ "movl", 0x580A0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* movl<.f><.cc> RB,ximm 01011bbb11001010FBBB1111000QQQQQ. */
+{ "movl", 0x58CA0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F, C_CC }},
+
+/* movl<.f> RB,limm 01011bbb00001010FBBB111110RRRRRR. */
+{ "movl", 0x580A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* movl<.f><.cc> RB,limm 01011bbb11001010FBBB1111100QQQQQ. */
+{ "movl", 0x58CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F, C_CC }},
+
+/* movl_s g,h 01000ggghhhGG1HH. */
+{ "movl_s", 0x00004004, 0x0000F804, ARC_OPCODE_ARC64, ARITH, NONE, { G_S, RH_S }, { 0 }},
+
+/* movl_s b,u8 11011bbbuuuuuuuu. */
+{ "movl_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, UIMM8_8_S }, { 0 }},
+
+/* movl_s g,limm 01000ggg110GG111. */
+{ "movl_s", 0x000040C7, 0x0000F8E7, ARC_OPCODE_ARC64, MOVE, NONE, { G_S, LIMM_S }, { 0 }},
+
+/* mov_s.NE b,h 01110bbbhhh111HH. */
+{ "mov_s", 0x0000701C, 0x0000F81C,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { RB_S, RH_S }, { C_NE, C_CC_NE}},
+
+/* mov_s g,h 01000ggghhhGG0HH. */
+{ "mov_s", 0x00004000, 0x0000F804,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { G_S, RH_S }, { 0 }},
+
+/* mov_s 0,h 01000110hhh110HH. */
+{ "mov_s", 0x00004618, 0x0000FF1C,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { ZA_S, RH_S }, { 0 }},
+
+/* mov_s h,s3 01110ssshhh011HH. */
+{ "mov_s", 0x0000700C, 0x0000F81C,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { RH_S, SIMM3_5_S }, { 0 }},
+
+/* mov_s 0,s3 01110sss11001111. */
+{ "mov_s", 0x000070CF, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { ZA_S, SIMM3_5_S }, { 0 }},
+
+/* mov_s b,u8 11011bbbuuuuuuuu. */
+{ "mov_s", 0x0000D800, 0x0000F800,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { RB_S, UIMM8_8_S }, { 0 }},
+
+/* mov_s.NE b,limm 01110bbb11011111. */
+{ "mov_s", 0x000070DF, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { RB_S, LIMM_S }, { C_NE, C_CC_NE}},
+
+/* mov_s g,limm 01000ggg110GG011. */
+{ "mov_s", 0x000040C3, 0x0000F8E7,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { G_S, LIMM_S }, { 0 }},
+
+/* mov_s 0,limm 0100011011011011. */
+{ "mov_s", 0x000046DB, 0x0000FFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, { ZA_S, LIMM_S }, { 0 }},
+
+/* mpy<.f> a,b,c 00100bbb00011010FBBBCCCCCCAAAAAA. */
+{ "mpy", 0x201A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpy<.f> 0,b,c 00100bbb00011010FBBBCCCCCC111110. */
+{ "mpy", 0x201A003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpy<.f><.cc> b,b,c 00100bbb11011010FBBBCCCCCC0QQQQQ. */
+{ "mpy", 0x20DA0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
+{ "mpy", 0x205A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpy<.f> 0,b,u6 00100bbb01011010FBBBuuuuuu111110. */
+{ "mpy", 0x205A003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpy<.f><.cc> b,b,u6 00100bbb11011010FBBBuuuuuu1QQQQQ. */
+{ "mpy", 0x20DA0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpy<.f> b,b,s12 00100bbb10011010FBBBssssssSSSSSS. */
+{ "mpy", 0x209A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpy<.f> a,limm,c 0010011000011010F111CCCCCCAAAAAA. */
+{ "mpy", 0x261A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
+{ "mpy", 0x201A0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpy<.f> 0,limm,c 0010011000011010F111CCCCCC111110. */
+{ "mpy", 0x261A703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpy<.f> 0,b,limm 00100bbb00011010FBBB111110111110. */
+{ "mpy", 0x201A0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpy<.f><.cc> b,b,limm 00100bbb11011010FBBB1111100QQQQQ. */
+{ "mpy", 0x20DA0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpy<.f><.cc> 0,limm,c 0010011011011010F111CCCCCC0QQQQQ. */
+{ "mpy", 0x26DA7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpy<.f> a,limm,u6 0010011001011010F111uuuuuuAAAAAA. */
+{ "mpy", 0x265A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpy<.f> 0,limm,u6 0010011001011010F111uuuuuu111110. */
+{ "mpy", 0x265A703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpy<.f><.cc> 0,limm,u6 0010011011011010F111uuuuuu1QQQQQ. */
+{ "mpy", 0x26DA7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpy<.f> 0,limm,s12 0010011010011010F111ssssssSSSSSS. */
+{ "mpy", 0x269A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpy<.f> a,limm,limm 0010011000011010F111111110AAAAAA. */
+{ "mpy", 0x261A7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpy<.f> 0,limm,limm 0010011000011010F111111110111110. */
+{ "mpy", 0x261A7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpy<.f><.cc> 0,limm,limm 0010011011011010F1111111100QQQQQ. */
+{ "mpy", 0x26DA7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyd<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA. */
+{ "mpyd", 0x28180000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpyd<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110. */
+{ "mpyd", 0x2818003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* mpyd<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ. */
+{ "mpyd", 0x28D80000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyd<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA. */
+{ "mpyd", 0x28580000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110. */
+{ "mpyd", 0x2858003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ. */
+{ "mpyd", 0x28D80020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyd<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS. */
+{ "mpyd", 0x28980000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyd<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA. */
+{ "mpyd", 0x2E187000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpyd<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA. */
+{ "mpyd", 0x28180F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpyd<.f> 0,limm,c 0010111000011000F111CCCCCC111110. */
+{ "mpyd", 0x2E18703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyd<.f> 0,b,limm 00101bbb00011000FBBB111110111110. */
+{ "mpyd", 0x28180FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyd<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ. */
+{ "mpyd", 0x28D80F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyd<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ. */
+{ "mpyd", 0x2ED87000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyd<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA. */
+{ "mpyd", 0x2E587000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f> 0,limm,u6 0010111001011000F111uuuuuu111110. */
+{ "mpyd", 0x2E58703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ. */
+{ "mpyd", 0x2ED87020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyd<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS. */
+{ "mpyd", 0x2E987000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyd<.f> a,limm,limm 0010111000011000F111111110AAAAAA. */
+{ "mpyd", 0x2E187F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpyd<.f> 0,limm,limm 0010111000011000F111111110111110. */
+{ "mpyd", 0x2E187FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyd<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ. */
+{ "mpyd", 0x2ED87F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpydf<.f> a,b,c 00110bbb00010010FBBBCCCCCCAAAAAA. */
+{ "mpydf", 0x30120000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpydf<.f> 0,b,c 00110bbb00010010FBBBCCCCCC111110. */
+{ "mpydf", 0x3012003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpydf<.f><.cc> b,b,c 00110bbb11010010FBBBCCCCCC0QQQQQ. */
+{ "mpydf", 0x30D20000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpydf<.f> a,b,u6 00110bbb01010010FBBBuuuuuuAAAAAA. */
+{ "mpydf", 0x30520000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f> 0,b,u6 00110bbb01010010FBBBuuuuuu111110. */
+{ "mpydf", 0x3052003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f><.cc> b,b,u6 00110bbb11010010FBBBuuuuuu1QQQQQ. */
+{ "mpydf", 0x30D20020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydf<.f> b,b,s12 00110bbb10010010FBBBssssssSSSSSS. */
+{ "mpydf", 0x30920000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpydf<.f> a,limm,c 0011011000010010F111CCCCCCAAAAAA. */
+{ "mpydf", 0x36127000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpydf<.f> a,b,limm 00110bbb00010010FBBB111110AAAAAA. */
+{ "mpydf", 0x30120F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpydf<.f> 0,limm,c 0011011000010010F111CCCCCC111110. */
+{ "mpydf", 0x3612703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpydf<.f> 0,b,limm 00110bbb00010010FBBB111110111110. */
+{ "mpydf", 0x30120FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpydf<.f><.cc> b,b,limm 00110bbb11010010FBBB1111100QQQQQ. */
+{ "mpydf", 0x30D20F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpydf<.f><.cc> 0,limm,c 0011011011010010F111CCCCCC0QQQQQ. */
+{ "mpydf", 0x36D27000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpydf<.f> a,limm,u6 0011011001010010F111uuuuuuAAAAAA. */
+{ "mpydf", 0x36527000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f> 0,limm,u6 0011011001010010F111uuuuuu111110. */
+{ "mpydf", 0x3652703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f><.cc> 0,limm,u6 0011011011010010F111uuuuuu1QQQQQ. */
+{ "mpydf", 0x36D27020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydf<.f> 0,limm,s12 0011011010010010F111ssssssSSSSSS. */
+{ "mpydf", 0x36927000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpydf<.f> a,limm,limm 0011011000010010F111111110AAAAAA. */
+{ "mpydf", 0x36127F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpydf<.f> 0,limm,limm 0011011000010010F111111110111110. */
+{ "mpydf", 0x36127FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpydf<.f><.cc> 0,limm,limm 0011011011010010F1111111100QQQQQ. */
+{ "mpydf", 0x36D27F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpydu<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA. */
+{ "mpydu", 0x28190000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpydu<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110. */
+{ "mpydu", 0x2819003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* mpydu<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ. */
+{ "mpydu", 0x28D90000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpydu<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA. */
+{ "mpydu", 0x28590000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110. */
+{ "mpydu", 0x2859003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ. */
+{ "mpydu", 0x28D90020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydu<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS. */
+{ "mpydu", 0x28990000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpydu<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA. */
+{ "mpydu", 0x2E197000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpydu<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA. */
+{ "mpydu", 0x28190F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpydu<.f> 0,limm,c 0010111000011001F111CCCCCC111110. */
+{ "mpydu", 0x2E19703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpydu<.f> 0,b,limm 00101bbb00011001FBBB111110111110. */
+{ "mpydu", 0x28190FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpydu<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ. */
+{ "mpydu", 0x28D90F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpydu<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ. */
+{ "mpydu", 0x2ED97000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpydu<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA. */
+{ "mpydu", 0x2E597000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f> 0,limm,u6 0010111001011001F111uuuuuu111110. */
+{ "mpydu", 0x2E59703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ. */
+{ "mpydu", 0x2ED97020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydu<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS. */
+{ "mpydu", 0x2E997000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpydu<.f> a,limm,limm 0010111000011001F111111110AAAAAA. */
+{ "mpydu", 0x2E197F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpydu<.f> 0,limm,limm 0010111000011001F111111110111110. */
+{ "mpydu", 0x2E197FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpydu<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ. */
+{ "mpydu", 0x2ED97F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpym<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA. */
+{ "mpym", 0x201B0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpym<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110. */
+{ "mpym", 0x201B003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpym<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ. */
+{ "mpym", 0x20DB0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpym<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA. */
+{ "mpym", 0x205B0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpym<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110. */
+{ "mpym", 0x205B003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpym<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ. */
+{ "mpym", 0x20DB0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpym<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS. */
+{ "mpym", 0x209B0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpym<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA. */
+{ "mpym", 0x261B7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpym<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA. */
+{ "mpym", 0x201B0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpym<.f> 0,limm,c 0010011000011011F111CCCCCC111110. */
+{ "mpym", 0x261B703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpym<.f> 0,b,limm 00100bbb00011011FBBB111110111110. */
+{ "mpym", 0x201B0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpym<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ. */
+{ "mpym", 0x20DB0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpym<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ. */
+{ "mpym", 0x26DB7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpym<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA. */
+{ "mpym", 0x265B7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpym<.f> 0,limm,u6 0010011001011011F111uuuuuu111110. */
+{ "mpym", 0x265B703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpym<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ. */
+{ "mpym", 0x26DB7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpym<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS. */
+{ "mpym", 0x269B7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpym<.f> a,limm,limm 0010011000011011F111111110AAAAAA. */
+{ "mpym", 0x261B7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpym<.f> 0,limm,limm 0010011000011011F111111110111110. */
+{ "mpym", 0x261B7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpym<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ. */
+{ "mpym", 0x26DB7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpymu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA. */
+{ "mpymu", 0x201C0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpymu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110. */
+{ "mpymu", 0x201C003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpymu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ. */
+{ "mpymu", 0x20DC0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpymu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA. */
+{ "mpymu", 0x205C0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110. */
+{ "mpymu", 0x205C003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ. */
+{ "mpymu", 0x20DC0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpymu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS. */
+{ "mpymu", 0x209C0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpymu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA. */
+{ "mpymu", 0x261C7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpymu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA. */
+{ "mpymu", 0x201C0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpymu<.f> 0,limm,c 0010011000011100F111CCCCCC111110. */
+{ "mpymu", 0x261C703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpymu<.f> 0,b,limm 00100bbb00011100FBBB111110111110. */
+{ "mpymu", 0x201C0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpymu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ. */
+{ "mpymu", 0x20DC0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpymu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ. */
+{ "mpymu", 0x26DC7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpymu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA. */
+{ "mpymu", 0x265C7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110. */
+{ "mpymu", 0x265C703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ. */
+{ "mpymu", 0x26DC7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpymu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS. */
+{ "mpymu", 0x269C7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpymu<.f> a,limm,limm 0010011000011100F111111110AAAAAA. */
+{ "mpymu", 0x261C7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpymu<.f> 0,limm,limm 0010011000011100F111111110111110. */
+{ "mpymu", 0x261C7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpymu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ. */
+{ "mpymu", 0x26DC7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyu<.f> a,b,c 00100bbb00011101FBBBCCCCCCAAAAAA. */
+{ "mpyu", 0x201D0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpyu<.f> 0,b,c 00100bbb00011101FBBBCCCCCC111110. */
+{ "mpyu", 0x201D003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpyu<.f><.cc> b,b,c 00100bbb11011101FBBBCCCCCC0QQQQQ. */
+{ "mpyu", 0x20DD0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyu<.f> a,b,u6 00100bbb01011101FBBBuuuuuuAAAAAA. */
+{ "mpyu", 0x205D0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f> 0,b,u6 00100bbb01011101FBBBuuuuuu111110. */
+{ "mpyu", 0x205D003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f><.cc> b,b,u6 00100bbb11011101FBBBuuuuuu1QQQQQ. */
+{ "mpyu", 0x20DD0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyu<.f> b,b,s12 00100bbb10011101FBBBssssssSSSSSS. */
+{ "mpyu", 0x209D0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyu<.f> a,limm,c 0010011000011101F111CCCCCCAAAAAA. */
+{ "mpyu", 0x261D7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpyu<.f> a,b,limm 00100bbb00011101FBBB111110AAAAAA. */
+{ "mpyu", 0x201D0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpyu<.f> 0,limm,c 0010011000011101F111CCCCCC111110. */
+{ "mpyu", 0x261D703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyu<.f> 0,b,limm 00100bbb00011101FBBB111110111110. */
+{ "mpyu", 0x201D0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyu<.f><.cc> b,b,limm 00100bbb11011101FBBB1111100QQQQQ. */
+{ "mpyu", 0x20DD0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyu<.f><.cc> 0,limm,c 0010011011011101F111CCCCCC0QQQQQ. */
+{ "mpyu", 0x26DD7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyu<.f> a,limm,u6 0010011001011101F111uuuuuuAAAAAA. */
+{ "mpyu", 0x265D7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f> 0,limm,u6 0010011001011101F111uuuuuu111110. */
+{ "mpyu", 0x265D703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f><.cc> 0,limm,u6 0010011011011101F111uuuuuu1QQQQQ. */
+{ "mpyu", 0x26DD7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyu<.f> 0,limm,s12 0010011010011101F111ssssssSSSSSS. */
+{ "mpyu", 0x269D7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyu<.f> a,limm,limm 0010011000011101F111111110AAAAAA. */
+{ "mpyu", 0x261D7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpyu<.f> 0,limm,limm 0010011000011101F111111110111110. */
+{ "mpyu", 0x261D7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyu<.f><.cc> 0,limm,limm 0010011011011101F1111111100QQQQQ. */
+{ "mpyu", 0x26DD7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,b,c 00100bbb00011111FBBBCCCCCCAAAAAA. */
+{ "mpyuw", 0x201F0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpyuw<.f> 0,b,c 00100bbb00011111FBBBCCCCCC111110. */
+{ "mpyuw", 0x201F003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, RC }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,c 00100bbb11011111FBBBCCCCCC0QQQQQ. */
+{ "mpyuw", 0x20DF0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,b,u6 00100bbb01011111FBBBuuuuuuAAAAAA. */
+{ "mpyuw", 0x205F0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f> 0,b,u6 00100bbb01011111FBBBuuuuuu111110. */
+{ "mpyuw", 0x205F003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,u6 00100bbb11011111FBBBuuuuuu1QQQQQ. */
+{ "mpyuw", 0x20DF0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyuw<.f> b,b,s12 00100bbb10011111FBBBssssssSSSSSS. */
+{ "mpyuw", 0x209F0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyuw<.f> a,limm,c 0010011000011111F111CCCCCCAAAAAA. */
+{ "mpyuw", 0x261F7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpyuw<.f> a,b,limm 00100bbb00011111FBBB111110AAAAAA. */
+{ "mpyuw", 0x201F0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpyuw<.f> 0,limm,c 0010011000011111F111CCCCCC111110. */
+{ "mpyuw", 0x261F703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyuw<.f> 0,b,limm 00100bbb00011111FBBB111110111110. */
+{ "mpyuw", 0x201F0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,limm 00100bbb11011111FBBB1111100QQQQQ. */
+{ "mpyuw", 0x20DF0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyuw<.f><.cc> 0,limm,c 0010011011011111F111CCCCCC0QQQQQ. */
+{ "mpyuw", 0x26DF7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,limm,u6 0010011001011111F111uuuuuuAAAAAA. */
+{ "mpyuw", 0x265F7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f> 0,limm,u6 0010011001011111F111uuuuuu111110. */
+{ "mpyuw", 0x265F703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f><.cc> 0,limm,u6 0010011011011111F111uuuuuu1QQQQQ. */
+{ "mpyuw", 0x26DF7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyuw<.f> 0,limm,s12 0010011010011111F111ssssssSSSSSS. */
+{ "mpyuw", 0x269F7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyuw<.f> a,limm,limm 0010011000011111F111111110AAAAAA. */
+{ "mpyuw", 0x261F7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpyuw<.f> 0,limm,limm 0010011000011111F111111110111110. */
+{ "mpyuw", 0x261F7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyuw<.f><.cc> 0,limm,limm 0010011011011111F1111111100QQQQQ. */
+{ "mpyuw", 0x26DF7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyuw_s b,b,c 01111bbbccc01010. */
+{ "mpyuw_s", 0x0000780A, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* mpyw<.f> a,b,c 00100bbb00011110FBBBCCCCCCAAAAAA. */
+{ "mpyw", 0x201E0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpyw<.f> 0,b,c 00100bbb00011110FBBBCCCCCC111110. */
+{ "mpyw", 0x201E003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, RC }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,c 00100bbb11011110FBBBCCCCCC0QQQQQ. */
+{ "mpyw", 0x20DE0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyw<.f> a,b,u6 00100bbb01011110FBBBuuuuuuAAAAAA. */
+{ "mpyw", 0x205E0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f> 0,b,u6 00100bbb01011110FBBBuuuuuu111110. */
+{ "mpyw", 0x205E003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,u6 00100bbb11011110FBBBuuuuuu1QQQQQ. */
+{ "mpyw", 0x20DE0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyw<.f> b,b,s12 00100bbb10011110FBBBssssssSSSSSS. */
+{ "mpyw", 0x209E0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyw<.f> a,limm,c 0010011000011110F111CCCCCCAAAAAA. */
+{ "mpyw", 0x261E7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpyw<.f> a,b,limm 00100bbb00011110FBBB111110AAAAAA. */
+{ "mpyw", 0x201E0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpyw<.f> 0,limm,c 0010011000011110F111CCCCCC111110. */
+{ "mpyw", 0x261E703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyw<.f> 0,b,limm 00100bbb00011110FBBB111110111110. */
+{ "mpyw", 0x201E0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,limm 00100bbb11011110FBBB1111100QQQQQ. */
+{ "mpyw", 0x20DE0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyw<.f><.cc> 0,limm,c 0010011011011110F111CCCCCC0QQQQQ. */
+{ "mpyw", 0x26DE7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyw<.f> a,limm,u6 0010011001011110F111uuuuuuAAAAAA. */
+{ "mpyw", 0x265E7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f> 0,limm,u6 0010011001011110F111uuuuuu111110. */
+{ "mpyw", 0x265E703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f><.cc> 0,limm,u6 0010011011011110F111uuuuuu1QQQQQ. */
+{ "mpyw", 0x26DE7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyw<.f> 0,limm,s12 0010011010011110F111ssssssSSSSSS. */
+{ "mpyw", 0x269E7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyw<.f> a,limm,limm 0010011000011110F111111110AAAAAA. */
+{ "mpyw", 0x261E7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpyw<.f> 0,limm,limm 0010011000011110F111111110111110. */
+{ "mpyw", 0x261E7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyw<.f><.cc> 0,limm,limm 0010011011011110F1111111100QQQQQ. */
+{ "mpyw", 0x26DE7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyw_s b,b,c 01111bbbccc01001. */
+{ "mpyw_s", 0x00007809, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* mpy_s b,b,c 01111bbbccc01100. */
+{ "mpy_s", 0x0000780C, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* neg<.f> a,b 00100bbb01001110FBBB000000AAAAAA. */
+{ "neg", 0x204E0000, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB }, { C_F }},
+
+/* neg<.f><.cc> b,b 00100bbb11001110FBBB0000001QQQQQ. */
+{ "neg", 0x20CE0020, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup }, { C_F, C_CC }},
+
+/* neg<.f> a,limm 0010011001001110F111000000AAAAAA. */
+{ "neg", 0x264E7000, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM }, { C_F }},
+
+/* neg<.f><.cc> 0,limm 0010011011001110F1110000001QQQQQ. */
+{ "neg", 0x26CE7020, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F, C_CC }},
+
+
+
+
+
+
+
+
+
+
+
+
+
+/* neg_s b,c 01111bbbccc10011. */
+{ "neg_s", 0x00007813, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* nop_s 0111100011100000. */
+{ "nop_s", 0x000078E0, 0x0000FFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* norm<.f> b,c 00101bbb00101111FBBBCCCCCC000001. */
+{ "norm", 0x282F0001, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* norm<.f> 0,c 0010111000101111F111CCCCCC000001. */
+{ "norm", 0x2E2F7001, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* norm<.f> b,u6 00101bbb01101111FBBBuuuuuu000001. */
+{ "norm", 0x286F0001, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* norm<.f> 0,u6 0010111001101111F111uuuuuu000001. */
+{ "norm", 0x2E6F7001, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* norm<.f> b,limm 00101bbb00101111FBBB111110000001. */
+{ "norm", 0x282F0F81, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* norm<.f> 0,limm 0010111000101111F111111110000001. */
+{ "norm", 0x2E2F7F81, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* normh<.f> b,c 00101bbb00101111FBBBCCCCCC001000. */
+{ "normh", 0x282F0008, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* normh<.f> 0,c 0010111000101111F111CCCCCC001000. */
+{ "normh", 0x2E2F7008, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* normh<.f> b,u6 00101bbb01101111FBBBuuuuuu001000. */
+{ "normh", 0x286F0008, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* normh<.f> 0,u6 0010111001101111F111uuuuuu001000. */
+{ "normh", 0x2E6F7008, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* normh<.f> b,limm 00101bbb00101111FBBB111110001000. */
+{ "normh", 0x282F0F88, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* normh<.f> 0,limm 0010111000101111F111111110001000. */
+{ "normh", 0x2E2F7F88, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* norml<.f> RB,RC 01011bbb00101111FBBBcccccc100001. */
+{ "norml", 0x582F0021, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* norml<.f> 0,RC 0101111000101111F111cccccc100001. */
+{ "norml", 0x5E2F7021, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* norml<.f> RB,u6 01011bbb01101111FBBBuuuuuu100001. */
+{ "norml", 0x586F0021, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* norml<.f> 0,u6 0101111001101111F111uuuuuu100001. */
+{ "norml", 0x5E6F7021, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* norml<.f> RB,ximm 01011bbb00101111FBBB111100100001. */
+{ "norml", 0x582F0F21, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* norml<.f> 0,ximm 0101111000101111F111111100100001. */
+{ "norml", 0x5E2F7F21, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* norml<.f> RB,limm 01011bbb00101111FBBB111110100001. */
+{ "norml", 0x582F0FA1, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* norml<.f> 0,limm 0101111000101111F111111110100001. */
+{ "norml", 0x5E2F7FA1, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* not<.f> b,c 00100bbb00101111FBBBCCCCCC001010. */
+{ "not", 0x202F000A, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* not<.f> 0,c 0010011000101111F111CCCCCC001010. */
+{ "not", 0x262F700A, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* not<.f> b,u6 00100bbb01101111FBBBuuuuuu001010. */
+{ "not", 0x206F000A, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* not<.f> 0,u6 0010011001101111F111uuuuuu001010. */
+{ "not", 0x266F700A, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* not<.f> b,limm 00100bbb00101111FBBB111110001010. */
+{ "not", 0x202F0F8A, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* not<.f> 0,limm 0010011000101111F111111110001010. */
+{ "not", 0x262F7F8A, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* notl<.f> RB,RC 01011bbb00101111FBBBcccccc001010. */
+{ "notl", 0x582F000A, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* notl<.f> 0,RC 0101111000101111F111cccccc001010. */
+{ "notl", 0x5E2F700A, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* notl<.f> RB,u6 01011bbb01101111FBBBuuuuuu001010. */
+{ "notl", 0x586F000A, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* notl<.f> 0,u6 0101111001101111F111uuuuuu001010. */
+{ "notl", 0x5E6F700A, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* notl<.f> RB,ximm 01011bbb00101111FBBB111100001010. */
+{ "notl", 0x582F0F0A, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* notl<.f> 0,ximm 0101111000101111F111111100001010. */
+{ "notl", 0x5E2F7F0A, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* notl<.f> RB,limm 01011bbb00101111FBBB111110001010. */
+{ "notl", 0x582F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* notl<.f> 0,limm 0101111000101111F111111110001010. */
+{ "notl", 0x5E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* not_s b,c 01111bbbccc10010. */
+{ "not_s", 0x00007812, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* or<.f> a,b,c 00100bbb00000101FBBBCCCCCCAAAAAA. */
+{ "or", 0x20050000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* or<.f> 0,b,c 00100bbb00000101FBBBCCCCCC111110. */
+{ "or", 0x2005003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* or<.f><.cc> b,b,c 00100bbb11000101FBBBCCCCCC0QQQQQ. */
+{ "or", 0x20C50000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* or<.f> a,b,u6 00100bbb01000101FBBBuuuuuuAAAAAA. */
+{ "or", 0x20450000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* or<.f> 0,b,u6 00100bbb01000101FBBBuuuuuu111110. */
+{ "or", 0x2045003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* or<.f><.cc> b,b,u6 00100bbb11000101FBBBuuuuuu1QQQQQ. */
+{ "or", 0x20C50020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* or<.f> b,b,s12 00100bbb10000101FBBBssssssSSSSSS. */
+{ "or", 0x20850000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* or<.f> a,limm,c 0010011000000101F111CCCCCCAAAAAA. */
+{ "or", 0x26057000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* or<.f> a,b,limm 00100bbb00000101FBBB111110AAAAAA. */
+{ "or", 0x20050F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* or<.f> 0,limm,c 0010011000000101F111CCCCCC111110. */
+{ "or", 0x2605703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* or<.f> 0,b,limm 00100bbb00000101FBBB111110111110. */
+{ "or", 0x20050FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* or<.f><.cc> b,b,limm 00100bbb11000101FBBB1111100QQQQQ. */
+{ "or", 0x20C50F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* or<.f><.cc> 0,limm,c 0010011011000101F111CCCCCC0QQQQQ. */
+{ "or", 0x26C57000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* or<.f> a,limm,u6 0010011001000101F111uuuuuuAAAAAA. */
+{ "or", 0x26457000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* or<.f> 0,limm,u6 0010011001000101F111uuuuuu111110. */
+{ "or", 0x2645703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* or<.f><.cc> 0,limm,u6 0010011011000101F111uuuuuu1QQQQQ. */
+{ "or", 0x26C57020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* or<.f> 0,limm,s12 0010011010000101F111ssssssSSSSSS. */
+{ "or", 0x26857000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* or<.f> a,limm,limm 0010011000000101F111111110AAAAAA. */
+{ "or", 0x26057F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* or<.f> 0,limm,limm 0010011000000101F111111110111110. */
+{ "or", 0x26057FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* or<.f><.cc> 0,limm,limm 0010011011000101F1111111100QQQQQ. */
+{ "or", 0x26C57F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* orl<.f> RA,RB,RC 01011bbb00000101FBBBccccccaaaaaa. */
+{ "orl", 0x58050000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* orl<.f> 0,RB,RC 01011bbb00000101FBBBcccccc111110. */
+{ "orl", 0x5805003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* orl<.f><.cc> RB,RB,RC 01011bbb11000101FBBBcccccc0QQQQQ. */
+{ "orl", 0x58C50000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* orl<.f> RA,RB,u6 01011bbb01000101FBBBuuuuuuaaaaaa. */
+{ "orl", 0x58450000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* orl<.f> 0,RB,u6 01011bbb01000101FBBBuuuuuu111110. */
+{ "orl", 0x5845003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* orl<.f><.cc> RB,RB,u6 01011bbb11000101FBBBuuuuuu1QQQQQ. */
+{ "orl", 0x58C50020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* orl<.f> RB,RB,s12 01011bbb10000101FBBBssssssSSSSSS. */
+{ "orl", 0x58850000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* orl<.f> RA,ximm,RC 0101110000000101F111ccccccaaaaaa. */
+{ "orl", 0x5C057000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* orl<.f> RA,RB,ximm 01011bbb00000101FBBB111100aaaaaa. */
+{ "orl", 0x58050F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* orl<.f> 0,ximm,RC 0101110000000101F111cccccc111110. */
+{ "orl", 0x5C05703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* orl<.f> 0,RB,ximm 01011bbb00000101FBBB111100111110. */
+{ "orl", 0x58050F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* orl<.f><.cc> 0,ximm,RC 0101110011000101F111cccccc0QQQQQ. */
+{ "orl", 0x5CC57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* orl<.f><.cc> RB,RB,ximm 01011bbb11000101FBBB1111000QQQQQ. */
+{ "orl", 0x58C50F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* orl<.f> RA,ximm,u6 0101110001000101F111uuuuuuaaaaaa. */
+{ "orl", 0x5C457000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* orl<.f> 0,ximm,u6 0101110001000101F111uuuuuu111110. */
+{ "orl", 0x5C45703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* orl<.f><.cc> 0,ximm,u6 0101110011000101F111uuuuuu1QQQQQ. */
+{ "orl", 0x5CC57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* orl<.f> RA,limm,RC 0101111000000101F111ccccccaaaaaa. */
+{ "orl", 0x5E057000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* orl<.f> RA,RB,limm 01011bbb00000101FBBB111110aaaaaa. */
+{ "orl", 0x58050F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LO32 }, { C_F }},
+{ "orl", 0x58050F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* orl<.f> 0,limm,RC 0101111000000101F111cccccc111110. */
+{ "orl", 0x5E05703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* orl<.f> 0,RB,limm 01011bbb00000101FBBB111110111110. */
+{ "orl", 0x58050FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* orl<.f><.cc> 0,limm,RC 0101111011000101F111cccccc0QQQQQ. */
+{ "orl", 0x5EC57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* orl<.f><.cc> RB,RB,limm 01011bbb11000101FBBB1111100QQQQQ. */
+{ "orl", 0x58C50F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* orl<.f> RA,limm,u6 0101111001000101F111uuuuuuaaaaaa. */
+{ "orl", 0x5E457000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* orl<.f> 0,limm,u6 0101111001000101F111uuuuuu111110. */
+{ "orl", 0x5E45703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* orl<.f><.cc> 0,limm,u6 0101111011000101F111uuuuuu1QQQQQ. */
+{ "orl", 0x5EC57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* orl<.f> 0,ximm,s12 0101110010000101F111ssssssSSSSSS. */
+{ "orl", 0x5C857000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* orl<.f> 0,limm,s12 0101111010000101F111ssssssSSSSSS. */
+{ "orl", 0x5E857000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* orl<.f> RA,ximm,ximm 0101110000000101F111111100aaaaaa. */
+{ "orl", 0x5C057F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* orl<.f> 0,ximm,ximm 0101110000000101F111111100111110. */
+{ "orl", 0x5C057F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* orl<.f><.cc> 0,ximm,ximm 0101110011000101F1111111000QQQQQ. */
+{ "orl", 0x5CC57F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* orl<.f> RA,limm,limm 0101111000000101F111111110aaaaaa. */
+{ "orl", 0x5E057F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* orl<.f> 0,limm,limm 0101111000000101F111111110111110. */
+{ "orl", 0x5E057FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* orl<.f><.cc> 0,limm,limm 0101111011000101F1111111100QQQQQ. */
+{ "orl", 0x5EC57F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* orl_s b,b,c 01111bbbccc10111. */
+{ "orl_s", 0x00007817, 0x0000F81F, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* orl_s h,h,ximm 01110000hhh110HH. */
+{ "orl_s", 0x00007018, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, RH_Sdup, LO32 }, { 0 }},
+
+/* orl_s h,PCL,ximm 01110010hhh110HH. */
+{ "orl_s", 0x00007218, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, PCL_S, LO32 }, { 0 }},
+
+/* or_s b,b,c 01111bbbccc00101. */
+{ "or_s", 0x00007805, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* pop_s b 11000bbb11000001. */
+{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC32, POP, NONE, { RB_S }, { C_AA_AB }},
+
+/* pop_s BLINK 11000RRR11010001. */
+{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC32, POP, NONE, { BLINK_S }, { C_AA_AB }},
+
+/* popdl_s b 11000bbb1101BBB1. */
+{ "popdl_s", 0x0000C0D1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
+
+/* popl_s b 11000bbb1100BBB1. */
+{ "popl_s", 0x0000C0C1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
+
+/* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110. */
+{ "prealloc", 0x2031003E, 0xF83F803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
+
+/* prealloc<.aa> b,s9 00010bbbssssssssSBBB0aa001111110. */
+{ "prealloc", 0x1000007E, 0xF80009FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
+
+/* prealloc<.aa> b,limm 00100bbbaa1100010BBB111110111110. */
+{ "prealloc", 0x20310FBE, 0xF83F8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
+
+/* prealloc limm,c 00100110RR1100010111CCCCCC111110. */
+{ "prealloc", 0x2631703E, 0xFF3FF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
+
+/* prealloc limm 000101100000000001110RR001111110. */
+{ "prealloc", 0x1600707E, 0xFFFFF9FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* prealloc limm,s9 00010110ssssssssS1110RR001111110. */
+{ "prealloc", 0x1600707E, 0xFF0079FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
+
+/* prefetch<.aa> b,c 00100bbbaa1100000BBBCCCCCC111110. */
+{ "prefetch", 0x2030003E, 0xF83F803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
+
+/* prefetch<.aa> b,s9 00010bbbssssssssSBBB0aa000111110. */
+{ "prefetch", 0x1000003E, 0xF80009FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
+
+/* prefetch<.aa> b,limm 00100bbbaa1100000BBB111110111110. */
+{ "prefetch", 0x20300FBE, 0xF83F8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
+
+/* prefetch limm,c 00100110RR1100000111CCCCCC111110. */
+{ "prefetch", 0x2630703E, 0xFF3FF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
+
+/* prefetch limm 000101100000000001110RR000111110. */
+{ "prefetch", 0x1600703E, 0xFFFFF9FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* prefetch limm,s9 00010110ssssssssS1110RR000111110. */
+{ "prefetch", 0x1600703E, 0xFF0079FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
+
+/* prefetchw<.aa> b,c 00100bbbaa1100001BBBCCCCCC111110. */
+{ "prefetchw", 0x2030803E, 0xF83F803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
+
+/* prefetchw<.aa> b,s9 00010bbbssssssssSBBB1aa000111110. */
+{ "prefetchw", 0x1000083E, 0xF80009FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
+
+/* prefetchw<.aa> b,limm 00100bbbaa1100001BBB111110111110. */
+{ "prefetchw", 0x20308FBE, 0xF83F8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
+
+/* prefetchw limm,c 00100110RR1100001111CCCCCC111110. */
+{ "prefetchw", 0x2630F03E, 0xFF3FF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
+
+/* prefetchw limm 000101100000000001111RR000111110. */
+{ "prefetchw", 0x1600783E, 0xFFFFF9FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* prefetchw limm,s9 00010110ssssssssS1111RR000111110. */
+{ "prefetchw", 0x1600783E, 0xFF0079FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
+
+/* push_s b 11000bbb11100001. */
+{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC32, PUSH, NONE, { RB_S }, { C_AA_AW }},
+
+/* push_s blink 11000RRR11110001. */
+{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC32, PUSH, NONE, { BLINK_S }, { C_AA_AW }},
+
+/* pushdl_s b 11000bbb1111BBB1. */
+{ "pushdl_s", 0x0000C0F1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
+
+/* pushl_s b 11000bbb1110BBB1. */
+{ "pushl_s", 0x0000C0E1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
+
+/* qmach<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA. */
+{ "qmach", 0x28340000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* qmach<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110. */
+{ "qmach", 0x2834003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmach<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ. */
+{ "qmach", 0x28F40000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* qmach<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA. */
+{ "qmach", 0x28740000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* qmach<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110. */
+{ "qmach", 0x2874003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmach<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ. */
+{ "qmach", 0x28F40020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmach<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS. */
+{ "qmach", 0x28B40000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmach<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA. */
+{ "qmach", 0x2E347000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* qmach<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA. */
+{ "qmach", 0x28340F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* qmach<.f> 0,limm,c 0010111000110100F111CCCCCC111110. */
+{ "qmach", 0x2E34703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmach<.f> 0,b,limm 00101bbb00110100FBBB111110111110. */
+{ "qmach", 0x28340FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmach<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ. */
+{ "qmach", 0x28F40F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmach<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ. */
+{ "qmach", 0x2EF47000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmach<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA. */
+{ "qmach", 0x2E747000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmach<.f> 0,limm,u6 0010111001110100F111uuuuuu111110. */
+{ "qmach", 0x2E74703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmach<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ. */
+{ "qmach", 0x2EF47020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmach<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS. */
+{ "qmach", 0x2EB47000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmach<.f> a,limm,limm 0010111000110100F111111110AAAAAA. */
+{ "qmach", 0x2E347F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* qmach<.f> 0,limm,limm 0010111000110100F111111110111110. */
+{ "qmach", 0x2E347FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmach<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ. */
+{ "qmach", 0x2EF47F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* qmachu<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA. */
+{ "qmachu", 0x28350000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* qmachu<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110. */
+{ "qmachu", 0x2835003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmachu<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ. */
+{ "qmachu", 0x28F50000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* qmachu<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA. */
+{ "qmachu", 0x28750000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110. */
+{ "qmachu", 0x2875003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ. */
+{ "qmachu", 0x28F50020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmachu<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS. */
+{ "qmachu", 0x28B50000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmachu<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA. */
+{ "qmachu", 0x2E357000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* qmachu<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA. */
+{ "qmachu", 0x28350F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* qmachu<.f> 0,limm,c 0010111000110101F111CCCCCC111110. */
+{ "qmachu", 0x2E35703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmachu<.f> 0,b,limm 00101bbb00110101FBBB111110111110. */
+{ "qmachu", 0x28350FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmachu<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ. */
+{ "qmachu", 0x28F50F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmachu<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ. */
+{ "qmachu", 0x2EF57000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmachu<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA. */
+{ "qmachu", 0x2E757000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f> 0,limm,u6 0010111001110101F111uuuuuu111110. */
+{ "qmachu", 0x2E75703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ. */
+{ "qmachu", 0x2EF57020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmachu<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS. */
+{ "qmachu", 0x2EB57000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmachu<.f> a,limm,limm 0010111000110101F111111110AAAAAA. */
+{ "qmachu", 0x2E357F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* qmachu<.f> 0,limm,limm 0010111000110101F111111110111110. */
+{ "qmachu", 0x2E357FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmachu<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ. */
+{ "qmachu", 0x2EF57F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* qmpyh<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA. */
+{ "qmpyh", 0x28300000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* qmpyh<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110. */
+{ "qmpyh", 0x2830003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmpyh<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ. */
+{ "qmpyh", 0x28F00000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* qmpyh<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA. */
+{ "qmpyh", 0x28700000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110. */
+{ "qmpyh", 0x2870003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ. */
+{ "qmpyh", 0x28F00020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyh<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS. */
+{ "qmpyh", 0x28B00000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmpyh<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA. */
+{ "qmpyh", 0x2E307000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* qmpyh<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA. */
+{ "qmpyh", 0x28300F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* qmpyh<.f> 0,limm,c 0010111000110000F111CCCCCC111110. */
+{ "qmpyh", 0x2E30703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmpyh<.f> 0,b,limm 00101bbb00110000FBBB111110111110. */
+{ "qmpyh", 0x28300FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmpyh<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ. */
+{ "qmpyh", 0x28F00F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmpyh<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ. */
+{ "qmpyh", 0x2EF07000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmpyh<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA. */
+{ "qmpyh", 0x2E707000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f> 0,limm,u6 0010111001110000F111uuuuuu111110. */
+{ "qmpyh", 0x2E70703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ. */
+{ "qmpyh", 0x2EF07020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyh<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS. */
+{ "qmpyh", 0x2EB07000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmpyh<.f> a,limm,limm 0010111000110000F111111110AAAAAA. */
+{ "qmpyh", 0x2E307F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyh<.f> 0,limm,limm 0010111000110000F111111110111110. */
+{ "qmpyh", 0x2E307FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyh<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ. */
+{ "qmpyh", 0x2EF07F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* qmpyhu<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA. */
+{ "qmpyhu", 0x28310000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* qmpyhu<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110. */
+{ "qmpyhu", 0x2831003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmpyhu<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ. */
+{ "qmpyhu", 0x28F10000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* qmpyhu<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA. */
+{ "qmpyhu", 0x28710000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110. */
+{ "qmpyhu", 0x2871003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ. */
+{ "qmpyhu", 0x28F10020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyhu<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS. */
+{ "qmpyhu", 0x28B10000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmpyhu<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA. */
+{ "qmpyhu", 0x2E317000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* qmpyhu<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA. */
+{ "qmpyhu", 0x28310F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* qmpyhu<.f> 0,limm,c 0010111000110001F111CCCCCC111110. */
+{ "qmpyhu", 0x2E31703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmpyhu<.f> 0,b,limm 00101bbb00110001FBBB111110111110. */
+{ "qmpyhu", 0x28310FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmpyhu<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ. */
+{ "qmpyhu", 0x28F10F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmpyhu<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ. */
+{ "qmpyhu", 0x2EF17000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmpyhu<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA. */
+{ "qmpyhu", 0x2E717000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f> 0,limm,u6 0010111001110001F111uuuuuu111110. */
+{ "qmpyhu", 0x2E71703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ. */
+{ "qmpyhu", 0x2EF17020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyhu<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS. */
+{ "qmpyhu", 0x2EB17000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmpyhu<.f> a,limm,limm 0010111000110001F111111110AAAAAA. */
+{ "qmpyhu", 0x2E317F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyhu<.f> 0,limm,limm 0010111000110001F111111110111110. */
+{ "qmpyhu", 0x2E317FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyhu<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ. */
+{ "qmpyhu", 0x2EF17F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rcmp b,c 00100bbb000011011BBBCCCCCCRRRRRR. */
+{ "rcmp", 0x200D8000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* rcmp<.cc> b,c 00100bbb110011011BBBCCCCCC0QQQQQ. */
+{ "rcmp", 0x20CD8000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* rcmp b,u6 00100bbb010011011BBBuuuuuuRRRRRR. */
+{ "rcmp", 0x204D8000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* rcmp<.cc> b,u6 00100bbb110011011BBBuuuuuu1QQQQQ. */
+{ "rcmp", 0x20CD8020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* rcmp b,s12 00100bbb100011011BBBssssssSSSSSS. */
+{ "rcmp", 0x208D8000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* rcmp limm,c 00100110000011011111CCCCCCRRRRRR. */
+{ "rcmp", 0x260DF000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* rcmp b,limm 00100bbb000011011BBB111110RRRRRR. */
+{ "rcmp", 0x200D8F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* rcmp<.cc> limm,c 00100110110011011111CCCCCC0QQQQQ. */
+{ "rcmp", 0x26CDF000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { C_CC }},
+
+/* rcmp<.cc> b,limm 00100bbb110011011BBB1111100QQQQQ. */
+{ "rcmp", 0x20CD8F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* rcmp limm,u6 00100110010011011111uuuuuuRRRRRR. */
+{ "rcmp", 0x264DF000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* rcmp<.cc> limm,u6 00100110110011011111uuuuuu1QQQQQ. */
+{ "rcmp", 0x26CDF020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* rcmp limm,s12 00100110100011011111ssssssSSSSSS. */
+{ "rcmp", 0x268DF000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* rcmp limm,limm 00100110000011011111111110RRRRRR. */
+{ "rcmp", 0x260DFF80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* rcmp<.cc> limm,limm 001001101100110111111111100QQQQQ. */
+{ "rcmp", 0x26CDFF80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* rcmpl RB,RC 01011bbb000011011BBBccccccRRRRRR. */
+{ "rcmpl", 0x580D8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* rcmpl<.cc> RB,RC 01011bbb110011011BBBcccccc0QQQQQ. */
+{ "rcmpl", 0x58CD8000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* rcmpl RB,u6 01011bbb010011011BBBuuuuuuRRRRRR. */
+{ "rcmpl", 0x584D8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* rcmpl<.cc> RB,u6 01011bbb110011011BBBuuuuuu1QQQQQ. */
+{ "rcmpl", 0x58CD8020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* rcmpl RB,s12 01011bbb100011011BBBssssssSSSSSS. */
+{ "rcmpl", 0x588D8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* rcmpl ximm,RC 01011100000011011111ccccccRRRRRR. */
+{ "rcmpl", 0x5C0DF000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { XIMM, RC }, { 0 }},
+
+/* rcmpl RB,ximm 01011bbb000011011BBB111100RRRRRR. */
+{ "rcmpl", 0x580D8F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 }},
+
+/* rcmpl<.cc> RB,ximm 01011bbb110011011BBB1111000QQQQQ. */
+{ "rcmpl", 0x58CD8F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC }},
+
+/* rcmpl limm,RC 01011110000011011111ccccccRRRRRR. */
+{ "rcmpl", 0x5E0DF000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* rcmpl RB,limm 01011bbb000011011BBB111110RRRRRR. */
+{ "rcmpl", 0x580D8F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* rcmpl<.cc> RB,limm 01011bbb110011011BBB1111100QQQQQ. */
+{ "rcmpl", 0x58CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* rcmpl limm,u6 01011110010011011111uuuuuuRRRRRR. */
+{ "rcmpl", 0x5E4DF000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* rem<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA. */
+{ "rem", 0x28080000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
+
+/* rem<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110. */
+{ "rem", 0x2808003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
+
+/* rem<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ. */
+{ "rem", 0x28C80000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* rem<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA. */
+{ "rem", 0x28480000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* rem<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110. */
+{ "rem", 0x2848003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* rem<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ. */
+{ "rem", 0x28C80020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* rem<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS. */
+{ "rem", 0x28880000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* rem<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA. */
+{ "rem", 0x2E087000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* rem<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA. */
+{ "rem", 0x28080F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* rem<.f> 0,limm,c 0010111000001000F111CCCCCC111110. */
+{ "rem", 0x2E08703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* rem<.f> 0,b,limm 00101bbb00001000FBBB111110111110. */
+{ "rem", 0x28080FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* rem<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ. */
+{ "rem", 0x28C80F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* rem<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ. */
+{ "rem", 0x2EC87000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* rem<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA. */
+{ "rem", 0x2E487000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* rem<.f> 0,limm,u6 0010111001001000F111uuuuuu111110. */
+{ "rem", 0x2E48703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rem<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ. */
+{ "rem", 0x2EC87020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* rem<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS. */
+{ "rem", 0x2E887000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* rem<.f> a,limm,limm 0010111000001000F111111110AAAAAA. */
+{ "rem", 0x2E087F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* rem<.f> 0,limm,limm 0010111000001000F111111110111110. */
+{ "rem", 0x2E087FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* rem<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ. */
+{ "rem", 0x2EC87F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* reml<.f> RA,RB,RC 01011bbb00101000FBBBccccccaaaaaa. */
+{ "reml", 0x58280000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* reml<.f> 0,RB,RC 01011bbb00101000FBBBcccccc111110. */
+{ "reml", 0x5828003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* reml<.f><.cc> RB,RB,RC 01011bbb11101000FBBBcccccc0QQQQQ. */
+{ "reml", 0x58E80000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* reml<.f> RA,RB,u6 01011bbb01101000FBBBuuuuuuaaaaaa. */
+{ "reml", 0x58680000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* reml<.f> 0,RB,u6 01011bbb01101000FBBBuuuuuu111110. */
+{ "reml", 0x5868003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* reml<.f><.cc> RB,RB,u6 01011bbb11101000FBBBuuuuuu1QQQQQ. */
+{ "reml", 0x58E80020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* reml<.f> RB,RB,s12 01011bbb10101000FBBBssssssSSSSSS. */
+{ "reml", 0x58A80000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* reml<.f> RA,ximm,RC 0101110000101000F111ccccccaaaaaa. */
+{ "reml", 0x5C287000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* reml<.f> RA,RB,ximm 01011bbb00101000FBBB111100aaaaaa. */
+{ "reml", 0x58280F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* reml<.f> 0,ximm,RC 0101110000101000F111cccccc111110. */
+{ "reml", 0x5C28703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* reml<.f> 0,RB,ximm 01011bbb00101000FBBB111100111110. */
+{ "reml", 0x58280F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* reml<.f><.cc> 0,ximm,RC 0101110011101000F111cccccc0QQQQQ. */
+{ "reml", 0x5CE87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* reml<.f><.cc> RB,RB,ximm 01011bbb11101000FBBB1111000QQQQQ. */
+{ "reml", 0x58E80F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* reml<.f> RA,ximm,u6 0101110001101000F111uuuuuuaaaaaa. */
+{ "reml", 0x5C687000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* reml<.f> 0,ximm,u6 0101110001101000F111uuuuuu111110. */
+{ "reml", 0x5C68703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* reml<.f><.cc> 0,ximm,u6 0101110011101000F111uuuuuu1QQQQQ. */
+{ "reml", 0x5CE87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* reml<.f> RA,limm,RC 0101111000101000F111ccccccaaaaaa. */
+{ "reml", 0x5E287000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* reml<.f> RA,RB,limm 01011bbb00101000FBBB111110aaaaaa. */
+{ "reml", 0x58280F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* reml<.f> 0,limm,RC 0101111000101000F111cccccc111110. */
+{ "reml", 0x5E28703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* reml<.f> 0,RB,limm 01011bbb00101000FBBB111110111110. */
+{ "reml", 0x58280FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* reml<.f><.cc> 0,limm,RC 0101111011101000F111cccccc0QQQQQ. */
+{ "reml", 0x5EE87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* reml<.f><.cc> RB,RB,limm 01011bbb11101000FBBB1111100QQQQQ. */
+{ "reml", 0x58E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* reml<.f> RA,limm,u6 0101111001101000F111uuuuuuaaaaaa. */
+{ "reml", 0x5E687000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* reml<.f> 0,limm,u6 0101111001101000F111uuuuuu111110. */
+{ "reml", 0x5E68703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* reml<.f><.cc> 0,limm,u6 0101111011101000F111uuuuuu1QQQQQ. */
+{ "reml", 0x5EE87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* reml<.f> 0,ximm,s12 0101110010101000F111ssssssSSSSSS. */
+{ "reml", 0x5CA87000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* reml<.f> 0,limm,s12 0101111010101000F111ssssssSSSSSS. */
+{ "reml", 0x5EA87000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* reml<.f> RA,ximm,ximm 0101110000101000F111111100aaaaaa. */
+{ "reml", 0x5C287F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* reml<.f> 0,ximm,ximm 0101110000101000F111111100111110. */
+{ "reml", 0x5C287F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* reml<.f><.cc> 0,ximm,ximm 0101110011101000F1111111000QQQQQ. */
+{ "reml", 0x5CE87F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* reml<.f> RA,limm,limm 0101111000101000F111111110aaaaaa. */
+{ "reml", 0x5E287F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* reml<.f> 0,limm,limm 0101111000101000F111111110111110. */
+{ "reml", 0x5E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* reml<.f><.cc> 0,limm,limm 0101111011101000F1111111100QQQQQ. */
+{ "reml", 0x5EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* remu<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA. */
+{ "remu", 0x28090000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
+
+/* remu<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110. */
+{ "remu", 0x2809003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
+
+/* remu<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ. */
+{ "remu", 0x28C90000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* remu<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA. */
+{ "remu", 0x28490000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* remu<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110. */
+{ "remu", 0x2849003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* remu<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ. */
+{ "remu", 0x28C90020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* remu<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS. */
+{ "remu", 0x28890000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* remu<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA. */
+{ "remu", 0x2E097000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* remu<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA. */
+{ "remu", 0x28090F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* remu<.f> 0,limm,c 0010111000001001F111CCCCCC111110. */
+{ "remu", 0x2E09703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* remu<.f> 0,b,limm 00101bbb00001001FBBB111110111110. */
+{ "remu", 0x28090FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* remu<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ. */
+{ "remu", 0x28C90F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* remu<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ. */
+{ "remu", 0x2EC97000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* remu<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA. */
+{ "remu", 0x2E497000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* remu<.f> 0,limm,u6 0010111001001001F111uuuuuu111110. */
+{ "remu", 0x2E49703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* remu<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ. */
+{ "remu", 0x2EC97020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* remu<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS. */
+{ "remu", 0x2E897000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* remu<.f> a,limm,limm 0010111000001001F111111110AAAAAA. */
+{ "remu", 0x2E097F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* remu<.f> 0,limm,limm 0010111000001001F111111110111110. */
+{ "remu", 0x2E097FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* remu<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */
+{ "remu", 0x2EC97F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* remul<.f> RA,RB,RC 01011bbb00101001FBBBccccccaaaaaa. */
+{ "remul", 0x58290000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* remul<.f> 0,RB,RC 01011bbb00101001FBBBcccccc111110. */
+{ "remul", 0x5829003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* remul<.f><.cc> RB,RB,RC 01011bbb11101001FBBBcccccc0QQQQQ. */
+{ "remul", 0x58E90000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* remul<.f> RA,RB,u6 01011bbb01101001FBBBuuuuuuaaaaaa. */
+{ "remul", 0x58690000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* remul<.f> 0,RB,u6 01011bbb01101001FBBBuuuuuu111110. */
+{ "remul", 0x5869003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* remul<.f><.cc> RB,RB,u6 01011bbb11101001FBBBuuuuuu1QQQQQ. */
+{ "remul", 0x58E90020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* remul<.f> RB,RB,s12 01011bbb10101001FBBBssssssSSSSSS. */
+{ "remul", 0x58A90000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* remul<.f> RA,ximm,RC 0101110000101001F111ccccccaaaaaa. */
+{ "remul", 0x5C297000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* remul<.f> RA,RB,ximm 01011bbb00101001FBBB111100aaaaaa. */
+{ "remul", 0x58290F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* remul<.f> 0,ximm,RC 0101110000101001F111cccccc111110. */
+{ "remul", 0x5C29703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* remul<.f> 0,RB,ximm 01011bbb00101001FBBB111100111110. */
+{ "remul", 0x58290F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* remul<.f><.cc> 0,ximm,RC 0101110011101001F111cccccc0QQQQQ. */
+{ "remul", 0x5CE97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* remul<.f><.cc> RB,RB,ximm 01011bbb11101001FBBB1111000QQQQQ. */
+{ "remul", 0x58E90F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* remul<.f> RA,ximm,u6 0101110001101001F111uuuuuuaaaaaa. */
+{ "remul", 0x5C697000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* remul<.f> 0,ximm,u6 0101110001101001F111uuuuuu111110. */
+{ "remul", 0x5C69703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* remul<.f><.cc> 0,ximm,u6 0101110011101001F111uuuuuu1QQQQQ. */
+{ "remul", 0x5CE97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* remul<.f> RA,limm,RC 0101111000101001F111ccccccaaaaaa. */
+{ "remul", 0x5E297000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* remul<.f> RA,RB,limm 01011bbb00101001FBBB111110aaaaaa. */
+{ "remul", 0x58290F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* remul<.f> 0,limm,RC 0101111000101001F111cccccc111110. */
+{ "remul", 0x5E29703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* remul<.f> 0,RB,limm 01011bbb00101001FBBB111110111110. */
+{ "remul", 0x58290FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* remul<.f><.cc> 0,limm,RC 0101111011101001F111cccccc0QQQQQ. */
+{ "remul", 0x5EE97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* remul<.f><.cc> RB,RB,limm 01011bbb11101001FBBB1111100QQQQQ. */
+{ "remul", 0x58E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* remul<.f> RA,limm,u6 0101111001101001F111uuuuuuaaaaaa. */
+{ "remul", 0x5E697000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* remul<.f> 0,limm,u6 0101111001101001F111uuuuuu111110. */
+{ "remul", 0x5E69703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* remul<.f><.cc> 0,limm,u6 0101111011101001F111uuuuuu1QQQQQ. */
+{ "remul", 0x5EE97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* remul<.f> 0,ximm,s12 0101110010101001F111ssssssSSSSSS. */
+{ "remul", 0x5CA97000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* remul<.f> 0,limm,s12 0101111010101001F111ssssssSSSSSS. */
+{ "remul", 0x5EA97000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* remul<.f> RA,ximm,ximm 0101110000101001F111111100aaaaaa. */
+{ "remul", 0x5C297F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* remul<.f> 0,ximm,ximm 0101110000101001F111111100111110. */
+{ "remul", 0x5C297F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* remul<.f><.cc> 0,ximm,ximm 0101110011101001F1111111000QQQQQ. */
+{ "remul", 0x5CE97F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* remul<.f> RA,limm,limm 0101111000101001F111111110aaaaaa. */
+{ "remul", 0x5E297F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* remul<.f> 0,limm,limm 0101111000101001F111111110111110. */
+{ "remul", 0x5E297FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* remul<.f><.cc> 0,limm,limm 0101111011101001F1111111100QQQQQ. */
+{ "remul", 0x5EE97F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rlc<.f> b,c 00100bbb00101111FBBBCCCCCC001011. */
+{ "rlc", 0x202F000B, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* rlc<.f> 0,c 0010011000101111F111CCCCCC001011. */
+{ "rlc", 0x262F700B, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* rlc<.f> b,u6 00100bbb01101111FBBBuuuuuu001011. */
+{ "rlc", 0x206F000B, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* rlc<.f> 0,u6 0010011001101111F111uuuuuu001011. */
+{ "rlc", 0x266F700B, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rlc<.f> b,limm 00100bbb00101111FBBB111110001011. */
+{ "rlc", 0x202F0F8B, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* rlc<.f> 0,limm 0010011000101111F111111110001011. */
+{ "rlc", 0x262F7F8B, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* rol<.f> b,c 00100bbb00101111FBBBCCCCCC001101. */
+{ "rol", 0x202F000D, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* rol<.f> 0,c 0010011000101111F111CCCCCC001101. */
+{ "rol", 0x262F700D, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* rol<.f> b,u6 00100bbb01101111FBBBuuuuuu001101. */
+{ "rol", 0x206F000D, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* rol<.f> 0,u6 0010011001101111F111uuuuuu001101. */
+{ "rol", 0x266F700D, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rol<.f> b,limm 00100bbb00101111FBBB111110001101. */
+{ "rol", 0x202F0F8D, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* rol<.f> 0,limm 0010011000101111F111111110001101. */
+{ "rol", 0x262F7F8D, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* rol8<.f> b,c 00101bbb00101111FBBBCCCCCC010000. */
+{ "rol8", 0x282F0010, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, RC }, { C_F }},
+
+/* rol8<.f> 0,c 0010111000101111F111CCCCCC010000. */
+{ "rol8", 0x2E2F7010, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, RC }, { C_F }},
+
+/* rol8<.f> b,u6 00101bbb01101111FBBBuuuuuu010000. */
+{ "rol8", 0x286F0010, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* rol8<.f> 0,u6 0010111001101111F111uuuuuu010000. */
+{ "rol8", 0x2E6F7010, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* rol8<.f> b,limm 00101bbb00101111FBBB111110010000. */
+{ "rol8", 0x282F0F90, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, LIMM }, { C_F }},
+
+/* rol8<.f> 0,limm 0010111000101111F111111110010000. */
+{ "rol8", 0x2E2F7F90, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* ror<.f> b,c 00100bbb00101111FBBBCCCCCC000011. */
+{ "ror", 0x202F0003, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* ror<.f> 0,c 0010011000101111F111CCCCCC000011. */
+{ "ror", 0x262F7003, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* ror<.f> a,b,c 00101bbb00000011FBBBCCCCCCAAAAAA. */
+{ "ror", 0x28030000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* ror<.f> 0,b,c 00101bbb00000011FBBBCCCCCC111110. */
+{ "ror", 0x2803003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* ror<.f><.cc> b,b,c 00101bbb11000011FBBBCCCCCC0QQQQQ. */
+{ "ror", 0x28C30000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* ror<.f> b,u6 00100bbb01101111FBBBuuuuuu000011. */
+{ "ror", 0x206F0003, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* ror<.f> 0,u6 0010011001101111F111uuuuuu000011. */
+{ "ror", 0x266F7003, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* ror<.f> a,b,u6 00101bbb01000011FBBBuuuuuuAAAAAA. */
+{ "ror", 0x28430000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* ror<.f> 0,b,u6 00101bbb01000011FBBBuuuuuu111110. */
+{ "ror", 0x2843003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* ror<.f><.cc> b,b,u6 00101bbb11000011FBBBuuuuuu1QQQQQ. */
+{ "ror", 0x28C30020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* ror<.f> b,b,s12 00101bbb10000011FBBBssssssSSSSSS. */
+{ "ror", 0x28830000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* ror<.f> b,limm 00100bbb00101111FBBB111110000011. */
+{ "ror", 0x202F0F83, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* ror<.f> 0,limm 0010011000101111F111111110000011. */
+{ "ror", 0x262F7F83, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* ror<.f> a,limm,c 0010111000000011F111CCCCCCAAAAAA. */
+{ "ror", 0x2E037000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* ror<.f> a,b,limm 00101bbb00000011FBBB111110AAAAAA. */
+{ "ror", 0x28030F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* ror<.f> 0,limm,c 0010111000000011F111CCCCCC111110. */
+{ "ror", 0x2E03703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* ror<.f> 0,b,limm 00101bbb00000011FBBB111110111110. */
+{ "ror", 0x28030FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* ror<.f><.cc> b,b,limm 00101bbb11000011FBBB1111100QQQQQ. */
+{ "ror", 0x28C30F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* ror<.f><.cc> 0,limm,c 0010111011000011F111CCCCCC0QQQQQ. */
+{ "ror", 0x2EC37000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* ror<.f> a,limm,u6 0010111001000011F111uuuuuuAAAAAA. */
+{ "ror", 0x2E437000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* ror<.f> 0,limm,u6 0010111001000011F111uuuuuu111110. */
+{ "ror", 0x2E43703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* ror<.f><.cc> 0,limm,u6 0010111011000011F111uuuuuu1QQQQQ. */
+{ "ror", 0x2EC37020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* ror<.f> 0,limm,s12 0010111010000011F111ssssssSSSSSS. */
+{ "ror", 0x2E837000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* ror<.f> a,limm,limm 0010111000000011F111111110AAAAAA. */
+{ "ror", 0x2E037F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* ror<.f> 0,limm,limm 0010111000000011F111111110111110. */
+{ "ror", 0x2E037FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* ror<.f><.cc> 0,limm,limm 0010111011000011F1111111100QQQQQ. */
+{ "ror", 0x2EC37F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* ror8<.f> b,c 00101bbb00101111FBBBCCCCCC010001. */
+{ "ror8", 0x282F0011, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, RC }, { C_F }},
+
+/* ror8<.f> 0,c 0010111000101111F111CCCCCC010001. */
+{ "ror8", 0x2E2F7011, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, RC }, { C_F }},
+
+/* ror8<.f> b,u6 00101bbb01101111FBBBuuuuuu010001. */
+{ "ror8", 0x286F0011, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* ror8<.f> 0,u6 0010111001101111F111uuuuuu010001. */
+{ "ror8", 0x2E6F7011, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* ror8<.f> b,limm 00101bbb00101111FBBB111110010001. */
+{ "ror8", 0x282F0F91, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, LIMM }, { C_F }},
+
+/* ror8<.f> 0,limm 0010111000101111F111111110010001. */
+{ "ror8", 0x2E2F7F91, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* rrc<.f> b,c 00100bbb00101111FBBBCCCCCC000100. */
+{ "rrc", 0x202F0004, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* rrc<.f> 0,c 0010011000101111F111CCCCCC000100. */
+{ "rrc", 0x262F7004, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* rrc<.f> b,u6 00100bbb01101111FBBBuuuuuu000100. */
+{ "rrc", 0x206F0004, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* rrc<.f> 0,u6 0010011001101111F111uuuuuu000100. */
+{ "rrc", 0x266F7004, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rrc<.f> b,limm 00100bbb00101111FBBB111110000100. */
+{ "rrc", 0x202F0F84, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* rrc<.f> 0,limm 0010011000101111F111111110000100. */
+{ "rrc", 0x262F7F84, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* rsub<.f> a,b,c 00100bbb00001110FBBBCCCCCCAAAAAA. */
+{ "rsub", 0x200E0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* rsub<.f> 0,b,c 00100bbb00001110FBBBCCCCCC111110. */
+{ "rsub", 0x200E003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* rsub<.f><.cc> b,b,c 00100bbb11001110FBBBCCCCCC0QQQQQ. */
+{ "rsub", 0x20CE0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* rsub<.f> a,b,u6 00100bbb01001110FBBBuuuuuuAAAAAA. */
+{ "rsub", 0x204E0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* rsub<.f> 0,b,u6 00100bbb01001110FBBBuuuuuu111110. */
+{ "rsub", 0x204E003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* rsub<.f><.cc> b,b,u6 00100bbb11001110FBBBuuuuuu1QQQQQ. */
+{ "rsub", 0x20CE0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsub<.f> b,b,s12 00100bbb10001110FBBBssssssSSSSSS. */
+{ "rsub", 0x208E0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* rsub<.f> a,limm,c 0010011000001110F111CCCCCCAAAAAA. */
+{ "rsub", 0x260E7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* rsub<.f> a,b,limm 00100bbb00001110FBBB111110AAAAAA. */
+{ "rsub", 0x200E0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* rsub<.f> 0,limm,c 0010011000001110F111CCCCCC111110. */
+{ "rsub", 0x260E703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* rsub<.f> 0,b,limm 00100bbb00001110FBBB111110111110. */
+{ "rsub", 0x200E0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* rsub<.f><.cc> b,b,limm 00100bbb11001110FBBB1111100QQQQQ. */
+{ "rsub", 0x20CE0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* rsub<.f><.cc> 0,limm,c 0010011011001110F111CCCCCC0QQQQQ. */
+{ "rsub", 0x26CE7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* rsub<.f> a,limm,u6 0010011001001110F111uuuuuuAAAAAA. */
+{ "rsub", 0x264E7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rsub<.f> 0,limm,u6 0010011001001110F111uuuuuu111110. */
+{ "rsub", 0x264E703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rsub<.f><.cc> 0,limm,u6 0010011011001110F111uuuuuu1QQQQQ. */
+{ "rsub", 0x26CE7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsub<.f> 0,limm,s12 0010011010001110F111ssssssSSSSSS. */
+{ "rsub", 0x268E7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* rsub<.f> a,limm,limm 0010011000001110F111111110AAAAAA. */
+{ "rsub", 0x260E7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* rsub<.f> 0,limm,limm 0010011000001110F111111110111110. */
+{ "rsub", 0x260E7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* rsub<.f><.cc> 0,limm,limm 0010011011001110F1111111100QQQQQ. */
+{ "rsub", 0x26CE7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,RB,RC 01011bbb00001110FBBBccccccaaaaaa. */
+{ "rsubl", 0x580E0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* rsubl<.f> 0,RB,RC 01011bbb00001110FBBBcccccc111110. */
+{ "rsubl", 0x580E003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* rsubl<.f><.cc> RB,RB,RC 01011bbb11001110FBBBcccccc0QQQQQ. */
+{ "rsubl", 0x58CE0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,RB,u6 01011bbb01001110FBBBuuuuuuaaaaaa. */
+{ "rsubl", 0x584E0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f> 0,RB,u6 01011bbb01001110FBBBuuuuuu111110. */
+{ "rsubl", 0x584E003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f><.cc> RB,RB,u6 01011bbb11001110FBBBuuuuuu1QQQQQ. */
+{ "rsubl", 0x58CE0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsubl<.f> RB,RB,s12 01011bbb10001110FBBBssssssSSSSSS. */
+{ "rsubl", 0x588E0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* rsubl<.f> RA,ximm,RC 0101110000001110F111ccccccaaaaaa. */
+{ "rsubl", 0x5C0E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* rsubl<.f> RA,RB,ximm 01011bbb00001110FBBB111100aaaaaa. */
+{ "rsubl", 0x580E0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* rsubl<.f> 0,ximm,RC 0101110000001110F111cccccc111110. */
+{ "rsubl", 0x5C0E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* rsubl<.f> 0,RB,ximm 01011bbb00001110FBBB111100111110. */
+{ "rsubl", 0x580E0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* rsubl<.f><.cc> 0,ximm,RC 0101110011001110F111cccccc0QQQQQ. */
+{ "rsubl", 0x5CCE7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* rsubl<.f><.cc> RB,RB,ximm 01011bbb11001110FBBB1111000QQQQQ. */
+{ "rsubl", 0x58CE0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,ximm,u6 0101110001001110F111uuuuuuaaaaaa. */
+{ "rsubl", 0x5C4E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f> 0,ximm,u6 0101110001001110F111uuuuuu111110. */
+{ "rsubl", 0x5C4E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f><.cc> 0,ximm,u6 0101110011001110F111uuuuuu1QQQQQ. */
+{ "rsubl", 0x5CCE7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,limm,RC 0101111000001110F111ccccccaaaaaa. */
+{ "rsubl", 0x5E0E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* rsubl<.f> RA,RB,limm 01011bbb00001110FBBB111110aaaaaa. */
+{ "rsubl", 0x580E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* rsubl<.f> 0,limm,RC 0101111000001110F111cccccc111110. */
+{ "rsubl", 0x5E0E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* rsubl<.f> 0,RB,limm 01011bbb00001110FBBB111110111110. */
+{ "rsubl", 0x580E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* rsubl<.f><.cc> 0,limm,RC 0101111011001110F111cccccc0QQQQQ. */
+{ "rsubl", 0x5ECE7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* rsubl<.f><.cc> RB,RB,limm 01011bbb11001110FBBB1111100QQQQQ. */
+{ "rsubl", 0x58CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,limm,u6 0101111001001110F111uuuuuuaaaaaa. */
+{ "rsubl", 0x5E4E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f> 0,limm,u6 0101111001001110F111uuuuuu111110. */
+{ "rsubl", 0x5E4E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f><.cc> 0,limm,u6 0101111011001110F111uuuuuu1QQQQQ. */
+{ "rsubl", 0x5ECE7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsubl<.f> 0,ximm,s12 0101110010001110F111ssssssSSSSSS. */
+{ "rsubl", 0x5C8E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* rsubl<.f> 0,limm,s12 0101111010001110F111ssssssSSSSSS. */
+{ "rsubl", 0x5E8E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* rsubl<.f> RA,ximm,ximm 0101110000001110F111111100aaaaaa. */
+{ "rsubl", 0x5C0E7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* rsubl<.f> 0,ximm,ximm 0101110000001110F111111100111110. */
+{ "rsubl", 0x5C0E7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* rsubl<.f><.cc> 0,ximm,ximm 0101110011001110F1111111000QQQQQ. */
+{ "rsubl", 0x5CCE7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,limm,limm 0101111000001110F111111110aaaaaa. */
+{ "rsubl", 0x5E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* rsubl<.f> 0,limm,limm 0101111000001110F111111110111110. */
+{ "rsubl", 0x5E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* rsubl<.f><.cc> 0,limm,limm 0101111011001110F1111111100QQQQQ. */
+{ "rsubl", 0x5ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rtie 00100100011011110000000000111111. */
+{ "rtie", 0x246F003F, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* sbc<.f> a,b,c 00100bbb00000011FBBBCCCCCCAAAAAA. */
+{ "sbc", 0x20030000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sbc<.f> 0,b,c 00100bbb00000011FBBBCCCCCC111110. */
+{ "sbc", 0x2003003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sbc<.f><.cc> b,b,c 00100bbb11000011FBBBCCCCCC0QQQQQ. */
+{ "sbc", 0x20C30000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sbc<.f> a,b,u6 00100bbb01000011FBBBuuuuuuAAAAAA. */
+{ "sbc", 0x20430000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sbc<.f> 0,b,u6 00100bbb01000011FBBBuuuuuu111110. */
+{ "sbc", 0x2043003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sbc<.f><.cc> b,b,u6 00100bbb11000011FBBBuuuuuu1QQQQQ. */
+{ "sbc", 0x20C30020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbc<.f> b,b,s12 00100bbb10000011FBBBssssssSSSSSS. */
+{ "sbc", 0x20830000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sbc<.f> a,limm,c 0010011000000011F111CCCCCCAAAAAA. */
+{ "sbc", 0x26037000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sbc<.f> a,b,limm 00100bbb00000011FBBB111110AAAAAA. */
+{ "sbc", 0x20030F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sbc<.f> 0,limm,c 0010011000000011F111CCCCCC111110. */
+{ "sbc", 0x2603703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sbc<.f> 0,b,limm 00100bbb00000011FBBB111110111110. */
+{ "sbc", 0x20030FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sbc<.f><.cc> b,b,limm 00100bbb11000011FBBB1111100QQQQQ. */
+{ "sbc", 0x20C30F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sbc<.f><.cc> 0,limm,c 0010011011000011F111CCCCCC0QQQQQ. */
+{ "sbc", 0x26C37000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sbc<.f> a,limm,u6 0010011001000011F111uuuuuuAAAAAA. */
+{ "sbc", 0x26437000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbc<.f> 0,limm,u6 0010011001000011F111uuuuuu111110. */
+{ "sbc", 0x2643703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbc<.f><.cc> 0,limm,u6 0010011011000011F111uuuuuu1QQQQQ. */
+{ "sbc", 0x26C37020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbc<.f> 0,limm,s12 0010011010000011F111ssssssSSSSSS. */
+{ "sbc", 0x26837000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sbc<.f> a,limm,limm 0010011000000011F111111110AAAAAA. */
+{ "sbc", 0x26037F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sbc<.f> 0,limm,limm 0010011000000011F111111110111110. */
+{ "sbc", 0x26037FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sbc<.f><.cc> 0,limm,limm 0010011011000011F1111111100QQQQQ. */
+{ "sbc", 0x26C37F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,RB,RC 01011bbb00000011FBBBccccccaaaaaa. */
+{ "sbcl", 0x58030000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sbcl<.f> 0,RB,RC 01011bbb00000011FBBBcccccc111110. */
+{ "sbcl", 0x5803003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sbcl<.f><.cc> RB,RB,RC 01011bbb11000011FBBBcccccc0QQQQQ. */
+{ "sbcl", 0x58C30000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,RB,u6 01011bbb01000011FBBBuuuuuuaaaaaa. */
+{ "sbcl", 0x58430000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f> 0,RB,u6 01011bbb01000011FBBBuuuuuu111110. */
+{ "sbcl", 0x5843003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f><.cc> RB,RB,u6 01011bbb11000011FBBBuuuuuu1QQQQQ. */
+{ "sbcl", 0x58C30020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbcl<.f> RB,RB,s12 01011bbb10000011FBBBssssssSSSSSS. */
+{ "sbcl", 0x58830000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sbcl<.f> RA,ximm,RC 0101110000000011F111ccccccaaaaaa. */
+{ "sbcl", 0x5C037000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* sbcl<.f> RA,RB,ximm 01011bbb00000011FBBB111100aaaaaa. */
+{ "sbcl", 0x58030F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* sbcl<.f> 0,ximm,RC 0101110000000011F111cccccc111110. */
+{ "sbcl", 0x5C03703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* sbcl<.f> 0,RB,ximm 01011bbb00000011FBBB111100111110. */
+{ "sbcl", 0x58030F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* sbcl<.f><.cc> 0,ximm,RC 0101110011000011F111cccccc0QQQQQ. */
+{ "sbcl", 0x5CC37000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* sbcl<.f><.cc> RB,RB,ximm 01011bbb11000011FBBB1111000QQQQQ. */
+{ "sbcl", 0x58C30F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,ximm,u6 0101110001000011F111uuuuuuaaaaaa. */
+{ "sbcl", 0x5C437000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f> 0,ximm,u6 0101110001000011F111uuuuuu111110. */
+{ "sbcl", 0x5C43703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f><.cc> 0,ximm,u6 0101110011000011F111uuuuuu1QQQQQ. */
+{ "sbcl", 0x5CC37020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,limm,RC 0101111000000011F111ccccccaaaaaa. */
+{ "sbcl", 0x5E037000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sbcl<.f> RA,RB,limm 01011bbb00000011FBBB111110aaaaaa. */
+{ "sbcl", 0x58030F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sbcl<.f> 0,limm,RC 0101111000000011F111cccccc111110. */
+{ "sbcl", 0x5E03703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sbcl<.f> 0,RB,limm 01011bbb00000011FBBB111110111110. */
+{ "sbcl", 0x58030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sbcl<.f><.cc> 0,limm,RC 0101111011000011F111cccccc0QQQQQ. */
+{ "sbcl", 0x5EC37000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sbcl<.f><.cc> RB,RB,limm 01011bbb11000011FBBB1111100QQQQQ. */
+{ "sbcl", 0x58C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,limm,u6 0101111001000011F111uuuuuuaaaaaa. */
+{ "sbcl", 0x5E437000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f> 0,limm,u6 0101111001000011F111uuuuuu111110. */
+{ "sbcl", 0x5E43703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f><.cc> 0,limm,u6 0101111011000011F111uuuuuu1QQQQQ. */
+{ "sbcl", 0x5EC37020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbcl<.f> 0,ximm,s12 0101110010000011F111ssssssSSSSSS. */
+{ "sbcl", 0x5C837000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* sbcl<.f> 0,limm,s12 0101111010000011F111ssssssSSSSSS. */
+{ "sbcl", 0x5E837000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sbcl<.f> RA,ximm,ximm 0101110000000011F111111100aaaaaa. */
+{ "sbcl", 0x5C037F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* sbcl<.f> 0,ximm,ximm 0101110000000011F111111100111110. */
+{ "sbcl", 0x5C037F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* sbcl<.f><.cc> 0,ximm,ximm 0101110011000011F1111111000QQQQQ. */
+{ "sbcl", 0x5CC37F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,limm,limm 0101111000000011F111111110aaaaaa. */
+{ "sbcl", 0x5E037F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sbcl<.f> 0,limm,limm 0101111000000011F111111110111110. */
+{ "sbcl", 0x5E037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sbcl<.f><.cc> 0,limm,limm 0101111011000011F1111111100QQQQQ. */
+{ "sbcl", 0x5EC37F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* scond<.di> b,c 00100bbb00101111DBBBCCCCCC010001. */
+{ "scond", 0x202F0011, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SCOND, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* scond<.di> b,u6 00100bbb01101111DBBBuuuuuu010001. */
+{ "scond", 0x206F0011, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SCOND, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* scond<.di> b,limm 00100bbb00101111DBBB111110010001. */
+{ "scond", 0x202F0F91, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SCOND, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011. */
+{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARC32, SCOND, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
+
+/* scondd<.di> b,limm 00100bbb00101111DBBB111110010011. */
+{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARC32, SCOND, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { C_DI16, C_ZZ_D }},
+
+/* scondl<.aq> RB,RC 01011bbb00101111FBBBcccccc010001. */
+{ "scondl", 0x582F0011, 0xF8FF003F, ARC_OPCODE_ARC64, SCOND, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_RL }},
+
+/* seteq<.f> a,b,c 00100bbb00111000FBBBCCCCCCAAAAAA. */
+{ "seteq", 0x20380000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* seteq<.f> 0,b,c 00100bbb00111000FBBBCCCCCC111110. */
+{ "seteq", 0x2038003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* seteq<.f><.cc> b,b,c 00100bbb11111000FBBBCCCCCC0QQQQQ. */
+{ "seteq", 0x20F80000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* seteq<.f> a,b,u6 00100bbb01111000FBBBuuuuuuAAAAAA. */
+{ "seteq", 0x20780000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* seteq<.f> 0,b,u6 00100bbb01111000FBBBuuuuuu111110. */
+{ "seteq", 0x2078003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* seteq<.f><.cc> b,b,u6 00100bbb11111000FBBBuuuuuu1QQQQQ. */
+{ "seteq", 0x20F80020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteq<.f> b,b,s12 00100bbb10111000FBBBssssssSSSSSS. */
+{ "seteq", 0x20B80000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* seteq<.f> a,limm,c 0010011000111000F111CCCCCCAAAAAA. */
+{ "seteq", 0x26387000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* seteq<.f> a,b,limm 00100bbb00111000FBBB111110AAAAAA. */
+{ "seteq", 0x20380F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* seteq<.f> 0,limm,c 0010011000111000F111CCCCCC111110. */
+{ "seteq", 0x2638703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* seteq<.f> 0,b,limm 00100bbb00111000FBBB111110111110. */
+{ "seteq", 0x20380FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* seteq<.f><.cc> b,b,limm 00100bbb11111000FBBB1111100QQQQQ. */
+{ "seteq", 0x20F80F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* seteq<.f><.cc> 0,limm,c 0010011011111000F111CCCCCC0QQQQQ. */
+{ "seteq", 0x26F87000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* seteq<.f> a,limm,u6 0010011001111000F111uuuuuuAAAAAA. */
+{ "seteq", 0x26787000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seteq<.f> 0,limm,u6 0010011001111000F111uuuuuu111110. */
+{ "seteq", 0x2678703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seteq<.f><.cc> 0,limm,u6 0010011011111000F111uuuuuu1QQQQQ. */
+{ "seteq", 0x26F87020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteq<.f> 0,limm,s12 0010011010111000F111ssssssSSSSSS. */
+{ "seteq", 0x26B87000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* seteq<.f> a,limm,limm 0010011000111000F111111110AAAAAA. */
+{ "seteq", 0x26387F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* seteq<.f> 0,limm,limm 0010011000111000F111111110111110. */
+{ "seteq", 0x26387FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* seteq<.f><.cc> 0,limm,limm 0010011011111000F1111111100QQQQQ. */
+{ "seteq", 0x26F87F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* seteql<.f> RA,RB,RC 01011bbb00111000FBBBccccccaaaaaa. */
+{ "seteql", 0x58380000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* seteql<.f> 0,RB,RC 01011bbb00111000FBBBcccccc111110. */
+{ "seteql", 0x5838003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* seteql<.f><.cc> RB,RB,RC 01011bbb11111000FBBBcccccc0QQQQQ. */
+{ "seteql", 0x58F80000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* seteql<.f> RA,RB,u6 01011bbb01111000FBBBuuuuuuaaaaaa. */
+{ "seteql", 0x58780000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* seteql<.f> 0,RB,u6 01011bbb01111000FBBBuuuuuu111110. */
+{ "seteql", 0x5878003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* seteql<.f><.cc> RB,RB,u6 01011bbb11111000FBBBuuuuuu1QQQQQ. */
+{ "seteql", 0x58F80020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteql<.f> RB,RB,s12 01011bbb10111000FBBBssssssSSSSSS. */
+{ "seteql", 0x58B80000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* seteql<.f> RA,ximm,RC 0101110000111000F111ccccccaaaaaa. */
+{ "seteql", 0x5C387000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* seteql<.f> RA,RB,ximm 01011bbb00111000FBBB111100aaaaaa. */
+{ "seteql", 0x58380F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* seteql<.f> 0,ximm,RC 0101110000111000F111cccccc111110. */
+{ "seteql", 0x5C38703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* seteql<.f> 0,RB,ximm 01011bbb00111000FBBB111100111110. */
+{ "seteql", 0x58380F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* seteql<.f><.cc> 0,ximm,RC 0101110011111000F111cccccc0QQQQQ. */
+{ "seteql", 0x5CF87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* seteql<.f><.cc> RB,RB,ximm 01011bbb11111000FBBB1111000QQQQQ. */
+{ "seteql", 0x58F80F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* seteql<.f> RA,ximm,u6 0101110001111000F111uuuuuuaaaaaa. */
+{ "seteql", 0x5C787000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* seteql<.f> 0,ximm,u6 0101110001111000F111uuuuuu111110. */
+{ "seteql", 0x5C78703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* seteql<.f><.cc> 0,ximm,u6 0101110011111000F111uuuuuu1QQQQQ. */
+{ "seteql", 0x5CF87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteql<.f> RA,limm,RC 0101111000111000F111ccccccaaaaaa. */
+{ "seteql", 0x5E387000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* seteql<.f> RA,RB,limm 01011bbb00111000FBBB111110aaaaaa. */
+{ "seteql", 0x58380F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* seteql<.f> 0,limm,RC 0101111000111000F111cccccc111110. */
+{ "seteql", 0x5E38703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* seteql<.f> 0,RB,limm 01011bbb00111000FBBB111110111110. */
+{ "seteql", 0x58380FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* seteql<.f><.cc> 0,limm,RC 0101111011111000F111cccccc0QQQQQ. */
+{ "seteql", 0x5EF87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* seteql<.f><.cc> RB,RB,limm 01011bbb11111000FBBB1111100QQQQQ. */
+{ "seteql", 0x58F80F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* seteql<.f> RA,limm,u6 0101111001111000F111uuuuuuaaaaaa. */
+{ "seteql", 0x5E787000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seteql<.f> 0,limm,u6 0101111001111000F111uuuuuu111110. */
+{ "seteql", 0x5E78703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seteql<.f><.cc> 0,limm,u6 0101111011111000F111uuuuuu1QQQQQ. */
+{ "seteql", 0x5EF87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteql<.f> 0,ximm,s12 0101110010111000F111ssssssSSSSSS. */
+{ "seteql", 0x5CB87000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* seteql<.f> 0,limm,s12 0101111010111000F111ssssssSSSSSS. */
+{ "seteql", 0x5EB87000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* seteql<.f> RA,ximm,ximm 0101110000111000F111111100aaaaaa. */
+{ "seteql", 0x5C387F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* seteql<.f> 0,ximm,ximm 0101110000111000F111111100111110. */
+{ "seteql", 0x5C387F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* seteql<.f><.cc> 0,ximm,ximm 0101110011111000F1111111000QQQQQ. */
+{ "seteql", 0x5CF87F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* seteql<.f> RA,limm,limm 0101111000111000F111111110aaaaaa. */
+{ "seteql", 0x5E387F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* seteql<.f> 0,limm,limm 0101111000111000F111111110111110. */
+{ "seteql", 0x5E387FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* seteql<.f><.cc> 0,limm,limm 0101111011111000F1111111100QQQQQ. */
+{ "seteql", 0x5EF87F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setge<.f> a,b,c 00100bbb00111011FBBBCCCCCCAAAAAA. */
+{ "setge", 0x203B0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* setge<.f> 0,b,c 00100bbb00111011FBBBCCCCCC111110. */
+{ "setge", 0x203B003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setge<.f><.cc> b,b,c 00100bbb11111011FBBBCCCCCC0QQQQQ. */
+{ "setge", 0x20FB0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setge<.f> a,b,u6 00100bbb01111011FBBBuuuuuuAAAAAA. */
+{ "setge", 0x207B0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setge<.f> 0,b,u6 00100bbb01111011FBBBuuuuuu111110. */
+{ "setge", 0x207B003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setge<.f><.cc> b,b,u6 00100bbb11111011FBBBuuuuuu1QQQQQ. */
+{ "setge", 0x20FB0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setge<.f> b,b,s12 00100bbb10111011FBBBssssssSSSSSS. */
+{ "setge", 0x20BB0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setge<.f> a,limm,c 0010011000111011F111CCCCCCAAAAAA. */
+{ "setge", 0x263B7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setge<.f> a,b,limm 00100bbb00111011FBBB111110AAAAAA. */
+{ "setge", 0x203B0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setge<.f> 0,limm,c 0010011000111011F111CCCCCC111110. */
+{ "setge", 0x263B703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setge<.f> 0,b,limm 00100bbb00111011FBBB111110111110. */
+{ "setge", 0x203B0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setge<.f><.cc> b,b,limm 00100bbb11111011FBBB1111100QQQQQ. */
+{ "setge", 0x20FB0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setge<.f><.cc> 0,limm,c 0010011011111011F111CCCCCC0QQQQQ. */
+{ "setge", 0x26FB7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setge<.f> a,limm,u6 0010011001111011F111uuuuuuAAAAAA. */
+{ "setge", 0x267B7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setge<.f> 0,limm,u6 0010011001111011F111uuuuuu111110. */
+{ "setge", 0x267B703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setge<.f><.cc> 0,limm,u6 0010011011111011F111uuuuuu1QQQQQ. */
+{ "setge", 0x26FB7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setge<.f> 0,limm,s12 0010011010111011F111ssssssSSSSSS. */
+{ "setge", 0x26BB7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setge<.f> a,limm,limm 0010011000111011F111111110AAAAAA. */
+{ "setge", 0x263B7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setge<.f> 0,limm,limm 0010011000111011F111111110111110. */
+{ "setge", 0x263B7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setge<.f><.cc> 0,limm,limm 0010011011111011F1111111100QQQQQ. */
+{ "setge", 0x26FB7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setgel<.f> RA,RB,RC 01011bbb00111011FBBBccccccaaaaaa. */
+{ "setgel", 0x583B0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setgel<.f> 0,RB,RC 01011bbb00111011FBBBcccccc111110. */
+{ "setgel", 0x583B003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setgel<.f><.cc> RB,RB,RC 01011bbb11111011FBBBcccccc0QQQQQ. */
+{ "setgel", 0x58FB0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setgel<.f> RA,RB,u6 01011bbb01111011FBBBuuuuuuaaaaaa. */
+{ "setgel", 0x587B0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setgel<.f> 0,RB,u6 01011bbb01111011FBBBuuuuuu111110. */
+{ "setgel", 0x587B003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setgel<.f><.cc> RB,RB,u6 01011bbb11111011FBBBuuuuuu1QQQQQ. */
+{ "setgel", 0x58FB0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgel<.f> RB,RB,s12 01011bbb10111011FBBBssssssSSSSSS. */
+{ "setgel", 0x58BB0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setgel<.f> RA,ximm,RC 0101110000111011F111ccccccaaaaaa. */
+{ "setgel", 0x5C3B7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setgel<.f> RA,RB,ximm 01011bbb00111011FBBB111100aaaaaa. */
+{ "setgel", 0x583B0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setgel<.f> 0,ximm,RC 0101110000111011F111cccccc111110. */
+{ "setgel", 0x5C3B703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setgel<.f> 0,RB,ximm 01011bbb00111011FBBB111100111110. */
+{ "setgel", 0x583B0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setgel<.f><.cc> 0,ximm,RC 0101110011111011F111cccccc0QQQQQ. */
+{ "setgel", 0x5CFB7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setgel<.f><.cc> RB,RB,ximm 01011bbb11111011FBBB1111000QQQQQ. */
+{ "setgel", 0x58FB0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setgel<.f> RA,ximm,u6 0101110001111011F111uuuuuuaaaaaa. */
+{ "setgel", 0x5C7B7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setgel<.f> 0,ximm,u6 0101110001111011F111uuuuuu111110. */
+{ "setgel", 0x5C7B703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setgel<.f><.cc> 0,ximm,u6 0101110011111011F111uuuuuu1QQQQQ. */
+{ "setgel", 0x5CFB7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgel<.f> RA,limm,RC 0101111000111011F111ccccccaaaaaa. */
+{ "setgel", 0x5E3B7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setgel<.f> RA,RB,limm 01011bbb00111011FBBB111110aaaaaa. */
+{ "setgel", 0x583B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setgel<.f> 0,limm,RC 0101111000111011F111cccccc111110. */
+{ "setgel", 0x5E3B703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setgel<.f> 0,RB,limm 01011bbb00111011FBBB111110111110. */
+{ "setgel", 0x583B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setgel<.f><.cc> 0,limm,RC 0101111011111011F111cccccc0QQQQQ. */
+{ "setgel", 0x5EFB7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setgel<.f><.cc> RB,RB,limm 01011bbb11111011FBBB1111100QQQQQ. */
+{ "setgel", 0x58FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setgel<.f> RA,limm,u6 0101111001111011F111uuuuuuaaaaaa. */
+{ "setgel", 0x5E7B7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgel<.f> 0,limm,u6 0101111001111011F111uuuuuu111110. */
+{ "setgel", 0x5E7B703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgel<.f><.cc> 0,limm,u6 0101111011111011F111uuuuuu1QQQQQ. */
+{ "setgel", 0x5EFB7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgel<.f> 0,ximm,s12 0101110010111011F111ssssssSSSSSS. */
+{ "setgel", 0x5CBB7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setgel<.f> 0,limm,s12 0101111010111011F111ssssssSSSSSS. */
+{ "setgel", 0x5EBB7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setgel<.f> RA,ximm,ximm 0101110000111011F111111100aaaaaa. */
+{ "setgel", 0x5C3B7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setgel<.f> 0,ximm,ximm 0101110000111011F111111100111110. */
+{ "setgel", 0x5C3B7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setgel<.f><.cc> 0,ximm,ximm 0101110011111011F1111111000QQQQQ. */
+{ "setgel", 0x5CFB7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setgel<.f> RA,limm,limm 0101111000111011F111111110aaaaaa. */
+{ "setgel", 0x5E3B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setgel<.f> 0,limm,limm 0101111000111011F111111110111110. */
+{ "setgel", 0x5E3B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setgel<.f><.cc> 0,limm,limm 0101111011111011F1111111100QQQQQ. */
+{ "setgel", 0x5EFB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setgt<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA. */
+{ "setgt", 0x203F0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* setgt<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110. */
+{ "setgt", 0x203F003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setgt<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ. */
+{ "setgt", 0x20FF0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setgt<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA. */
+{ "setgt", 0x207F0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setgt<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110. */
+{ "setgt", 0x207F003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setgt<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ. */
+{ "setgt", 0x20FF0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgt<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS. */
+{ "setgt", 0x20BF0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setgt<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA. */
+{ "setgt", 0x263F7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setgt<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA. */
+{ "setgt", 0x203F0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setgt<.f> 0,limm,c 0010011000111111F111CCCCCC111110. */
+{ "setgt", 0x263F703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setgt<.f> 0,b,limm 00100bbb00111111FBBB111110111110. */
+{ "setgt", 0x203F0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setgt<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ. */
+{ "setgt", 0x20FF0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setgt<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ. */
+{ "setgt", 0x26FF7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setgt<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA. */
+{ "setgt", 0x267F7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgt<.f> 0,limm,u6 0010011001111111F111uuuuuu111110. */
+{ "setgt", 0x267F703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgt<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ. */
+{ "setgt", 0x26FF7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgt<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS. */
+{ "setgt", 0x26BF7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setgt<.f> a,limm,limm 0010011000111111F111111110AAAAAA. */
+{ "setgt", 0x263F7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setgt<.f> 0,limm,limm 0010011000111111F111111110111110. */
+{ "setgt", 0x263F7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setgt<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ. */
+{ "setgt", 0x26FF7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,RB,RC 01011bbb00111111FBBBccccccaaaaaa. */
+{ "setgtl", 0x583F0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setgtl<.f> 0,RB,RC 01011bbb00111111FBBBcccccc111110. */
+{ "setgtl", 0x583F003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setgtl<.f><.cc> RB,RB,RC 01011bbb11111111FBBBcccccc0QQQQQ. */
+{ "setgtl", 0x58FF0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,RB,u6 01011bbb01111111FBBBuuuuuuaaaaaa. */
+{ "setgtl", 0x587F0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f> 0,RB,u6 01011bbb01111111FBBBuuuuuu111110. */
+{ "setgtl", 0x587F003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f><.cc> RB,RB,u6 01011bbb11111111FBBBuuuuuu1QQQQQ. */
+{ "setgtl", 0x58FF0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgtl<.f> RB,RB,s12 01011bbb10111111FBBBssssssSSSSSS. */
+{ "setgtl", 0x58BF0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setgtl<.f> RA,ximm,RC 0101110000111111F111ccccccaaaaaa. */
+{ "setgtl", 0x5C3F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setgtl<.f> RA,RB,ximm 01011bbb00111111FBBB111100aaaaaa. */
+{ "setgtl", 0x583F0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setgtl<.f> 0,ximm,RC 0101110000111111F111cccccc111110. */
+{ "setgtl", 0x5C3F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setgtl<.f> 0,RB,ximm 01011bbb00111111FBBB111100111110. */
+{ "setgtl", 0x583F0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setgtl<.f><.cc> 0,ximm,RC 0101110011111111F111cccccc0QQQQQ. */
+{ "setgtl", 0x5CFF7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setgtl<.f><.cc> RB,RB,ximm 01011bbb11111111FBBB1111000QQQQQ. */
+{ "setgtl", 0x58FF0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,ximm,u6 0101110001111111F111uuuuuuaaaaaa. */
+{ "setgtl", 0x5C7F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f> 0,ximm,u6 0101110001111111F111uuuuuu111110. */
+{ "setgtl", 0x5C7F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f><.cc> 0,ximm,u6 0101110011111111F111uuuuuu1QQQQQ. */
+{ "setgtl", 0x5CFF7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,limm,RC 0101111000111111F111ccccccaaaaaa. */
+{ "setgtl", 0x5E3F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setgtl<.f> RA,RB,limm 01011bbb00111111FBBB111110aaaaaa. */
+{ "setgtl", 0x583F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setgtl<.f> 0,limm,RC 0101111000111111F111cccccc111110. */
+{ "setgtl", 0x5E3F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setgtl<.f> 0,RB,limm 01011bbb00111111FBBB111110111110. */
+{ "setgtl", 0x583F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setgtl<.f><.cc> 0,limm,RC 0101111011111111F111cccccc0QQQQQ. */
+{ "setgtl", 0x5EFF7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setgtl<.f><.cc> RB,RB,limm 01011bbb11111111FBBB1111100QQQQQ. */
+{ "setgtl", 0x58FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,limm,u6 0101111001111111F111uuuuuuaaaaaa. */
+{ "setgtl", 0x5E7F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f> 0,limm,u6 0101111001111111F111uuuuuu111110. */
+{ "setgtl", 0x5E7F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f><.cc> 0,limm,u6 0101111011111111F111uuuuuu1QQQQQ. */
+{ "setgtl", 0x5EFF7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgtl<.f> 0,ximm,s12 0101110010111111F111ssssssSSSSSS. */
+{ "setgtl", 0x5CBF7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setgtl<.f> 0,limm,s12 0101111010111111F111ssssssSSSSSS. */
+{ "setgtl", 0x5EBF7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setgtl<.f> RA,ximm,ximm 0101110000111111F111111100aaaaaa. */
+{ "setgtl", 0x5C3F7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setgtl<.f> 0,ximm,ximm 0101110000111111F111111100111110. */
+{ "setgtl", 0x5C3F7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setgtl<.f><.cc> 0,ximm,ximm 0101110011111111F1111111000QQQQQ. */
+{ "setgtl", 0x5CFF7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,limm,limm 0101111000111111F111111110aaaaaa. */
+{ "setgtl", 0x5E3F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setgtl<.f> 0,limm,limm 0101111000111111F111111110111110. */
+{ "setgtl", 0x5E3F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setgtl<.f><.cc> 0,limm,limm 0101111011111111F1111111100QQQQQ. */
+{ "setgtl", 0x5EFF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* seths<.f> a,b,c 00100bbb00111101FBBBCCCCCCAAAAAA. */
+{ "seths", 0x203D0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* seths<.f> 0,b,c 00100bbb00111101FBBBCCCCCC111110. */
+{ "seths", 0x203D003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* seths<.f><.cc> b,b,c 00100bbb11111101FBBBCCCCCC0QQQQQ. */
+{ "seths", 0x20FD0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* seths<.f> a,b,u6 00100bbb01111101FBBBuuuuuuAAAAAA. */
+{ "seths", 0x207D0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* seths<.f> 0,b,u6 00100bbb01111101FBBBuuuuuu111110. */
+{ "seths", 0x207D003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* seths<.f><.cc> b,b,u6 00100bbb11111101FBBBuuuuuu1QQQQQ. */
+{ "seths", 0x20FD0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* seths<.f> b,b,s12 00100bbb10111101FBBBssssssSSSSSS. */
+{ "seths", 0x20BD0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* seths<.f> a,limm,c 0010011000111101F111CCCCCCAAAAAA. */
+{ "seths", 0x263D7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* seths<.f> a,b,limm 00100bbb00111101FBBB111110AAAAAA. */
+{ "seths", 0x203D0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* seths<.f> 0,limm,c 0010011000111101F111CCCCCC111110. */
+{ "seths", 0x263D703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* seths<.f> 0,b,limm 00100bbb00111101FBBB111110111110. */
+{ "seths", 0x203D0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* seths<.f><.cc> b,b,limm 00100bbb11111101FBBB1111100QQQQQ. */
+{ "seths", 0x20FD0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* seths<.f><.cc> 0,limm,c 0010011011111101F111CCCCCC0QQQQQ. */
+{ "seths", 0x26FD7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* seths<.f> a,limm,u6 0010011001111101F111uuuuuuAAAAAA. */
+{ "seths", 0x267D7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seths<.f> 0,limm,u6 0010011001111101F111uuuuuu111110. */
+{ "seths", 0x267D703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seths<.f><.cc> 0,limm,u6 0010011011111101F111uuuuuu1QQQQQ. */
+{ "seths", 0x26FD7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* seths<.f> 0,limm,s12 0010011010111101F111ssssssSSSSSS. */
+{ "seths", 0x26BD7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* seths<.f> a,limm,limm 0010011000111101F111111110AAAAAA. */
+{ "seths", 0x263D7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* seths<.f> 0,limm,limm 0010011000111101F111111110111110. */
+{ "seths", 0x263D7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* seths<.f><.cc> 0,limm,limm 0010011011111101F1111111100QQQQQ. */
+{ "seths", 0x26FD7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,RB,RC 01011bbb00111101FBBBccccccaaaaaa. */
+{ "sethsl", 0x583D0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sethsl<.f> 0,RB,RC 01011bbb00111101FBBBcccccc111110. */
+{ "sethsl", 0x583D003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sethsl<.f><.cc> RB,RB,RC 01011bbb11111101FBBBcccccc0QQQQQ. */
+{ "sethsl", 0x58FD0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,RB,u6 01011bbb01111101FBBBuuuuuuaaaaaa. */
+{ "sethsl", 0x587D0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f> 0,RB,u6 01011bbb01111101FBBBuuuuuu111110. */
+{ "sethsl", 0x587D003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f><.cc> RB,RB,u6 01011bbb11111101FBBBuuuuuu1QQQQQ. */
+{ "sethsl", 0x58FD0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sethsl<.f> RB,RB,s12 01011bbb10111101FBBBssssssSSSSSS. */
+{ "sethsl", 0x58BD0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sethsl<.f> RA,ximm,RC 0101110000111101F111ccccccaaaaaa. */
+{ "sethsl", 0x5C3D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* sethsl<.f> RA,RB,ximm 01011bbb00111101FBBB111100aaaaaa. */
+{ "sethsl", 0x583D0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* sethsl<.f> 0,ximm,RC 0101110000111101F111cccccc111110. */
+{ "sethsl", 0x5C3D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* sethsl<.f> 0,RB,ximm 01011bbb00111101FBBB111100111110. */
+{ "sethsl", 0x583D0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* sethsl<.f><.cc> 0,ximm,RC 0101110011111101F111cccccc0QQQQQ. */
+{ "sethsl", 0x5CFD7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* sethsl<.f><.cc> RB,RB,ximm 01011bbb11111101FBBB1111000QQQQQ. */
+{ "sethsl", 0x58FD0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,ximm,u6 0101110001111101F111uuuuuuaaaaaa. */
+{ "sethsl", 0x5C7D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f> 0,ximm,u6 0101110001111101F111uuuuuu111110. */
+{ "sethsl", 0x5C7D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f><.cc> 0,ximm,u6 0101110011111101F111uuuuuu1QQQQQ. */
+{ "sethsl", 0x5CFD7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,limm,RC 0101111000111101F111ccccccaaaaaa. */
+{ "sethsl", 0x5E3D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sethsl<.f> RA,RB,limm 01011bbb00111101FBBB111110aaaaaa. */
+{ "sethsl", 0x583D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sethsl<.f> 0,limm,RC 0101111000111101F111cccccc111110. */
+{ "sethsl", 0x5E3D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sethsl<.f> 0,RB,limm 01011bbb00111101FBBB111110111110. */
+{ "sethsl", 0x583D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sethsl<.f><.cc> 0,limm,RC 0101111011111101F111cccccc0QQQQQ. */
+{ "sethsl", 0x5EFD7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sethsl<.f><.cc> RB,RB,limm 01011bbb11111101FBBB1111100QQQQQ. */
+{ "sethsl", 0x58FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,limm,u6 0101111001111101F111uuuuuuaaaaaa. */
+{ "sethsl", 0x5E7D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f> 0,limm,u6 0101111001111101F111uuuuuu111110. */
+{ "sethsl", 0x5E7D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f><.cc> 0,limm,u6 0101111011111101F111uuuuuu1QQQQQ. */
+{ "sethsl", 0x5EFD7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sethsl<.f> 0,ximm,s12 0101110010111101F111ssssssSSSSSS. */
+{ "sethsl", 0x5CBD7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* sethsl<.f> 0,limm,s12 0101111010111101F111ssssssSSSSSS. */
+{ "sethsl", 0x5EBD7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sethsl<.f> RA,ximm,ximm 0101110000111101F111111100aaaaaa. */
+{ "sethsl", 0x5C3D7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* sethsl<.f> 0,ximm,ximm 0101110000111101F111111100111110. */
+{ "sethsl", 0x5C3D7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* sethsl<.f><.cc> 0,ximm,ximm 0101110011111101F1111111000QQQQQ. */
+{ "sethsl", 0x5CFD7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,limm,limm 0101111000111101F111111110aaaaaa. */
+{ "sethsl", 0x5E3D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sethsl<.f> 0,limm,limm 0101111000111101F111111110111110. */
+{ "sethsl", 0x5E3D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sethsl<.f><.cc> 0,limm,limm 0101111011111101F1111111100QQQQQ. */
+{ "sethsl", 0x5EFD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* seti c 00100110001011110000CCCCCC111111. */
+{ "seti", 0x262F003F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { 0 }},
+
+/* seti u6 00100110011011110000uuuuuu111111. */
+{ "seti", 0x266F003F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* seti limm 00100110001011110000111110111111. */
+{ "seti", 0x262F0FBF, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { LIMM }, { 0 }},
+
+/* seti 00100110011011110000000000111111. */
+{ "seti", 0x266F003F, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* setle<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA. */
+{ "setle", 0x203E0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* setle<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110. */
+{ "setle", 0x203E003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setle<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ. */
+{ "setle", 0x20FE0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setle<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA. */
+{ "setle", 0x207E0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setle<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110. */
+{ "setle", 0x207E003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setle<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ. */
+{ "setle", 0x20FE0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setle<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS. */
+{ "setle", 0x20BE0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setle<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA. */
+{ "setle", 0x263E7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setle<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA. */
+{ "setle", 0x203E0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setle<.f> 0,limm,c 0010011000111110F111CCCCCC111110. */
+{ "setle", 0x263E703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setle<.f> 0,b,limm 00100bbb00111110FBBB111110111110. */
+{ "setle", 0x203E0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setle<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ. */
+{ "setle", 0x20FE0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setle<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ. */
+{ "setle", 0x26FE7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setle<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA. */
+{ "setle", 0x267E7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setle<.f> 0,limm,u6 0010011001111110F111uuuuuu111110. */
+{ "setle", 0x267E703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setle<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ. */
+{ "setle", 0x26FE7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setle<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS. */
+{ "setle", 0x26BE7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setle<.f> a,limm,limm 0010011000111110F111111110AAAAAA. */
+{ "setle", 0x263E7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setle<.f> 0,limm,limm 0010011000111110F111111110111110. */
+{ "setle", 0x263E7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setle<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ. */
+{ "setle", 0x26FE7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setlel<.f> RA,RB,RC 01011bbb00111110FBBBccccccaaaaaa. */
+{ "setlel", 0x583E0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setlel<.f> 0,RB,RC 01011bbb00111110FBBBcccccc111110. */
+{ "setlel", 0x583E003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setlel<.f><.cc> RB,RB,RC 01011bbb11111110FBBBcccccc0QQQQQ. */
+{ "setlel", 0x58FE0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setlel<.f> RA,RB,u6 01011bbb01111110FBBBuuuuuuaaaaaa. */
+{ "setlel", 0x587E0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setlel<.f> 0,RB,u6 01011bbb01111110FBBBuuuuuu111110. */
+{ "setlel", 0x587E003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setlel<.f><.cc> RB,RB,u6 01011bbb11111110FBBBuuuuuu1QQQQQ. */
+{ "setlel", 0x58FE0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlel<.f> RB,RB,s12 01011bbb10111110FBBBssssssSSSSSS. */
+{ "setlel", 0x58BE0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setlel<.f> RA,ximm,RC 0101110000111110F111ccccccaaaaaa. */
+{ "setlel", 0x5C3E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setlel<.f> RA,RB,ximm 01011bbb00111110FBBB111100aaaaaa. */
+{ "setlel", 0x583E0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setlel<.f> 0,ximm,RC 0101110000111110F111cccccc111110. */
+{ "setlel", 0x5C3E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setlel<.f> 0,RB,ximm 01011bbb00111110FBBB111100111110. */
+{ "setlel", 0x583E0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setlel<.f><.cc> 0,ximm,RC 0101110011111110F111cccccc0QQQQQ. */
+{ "setlel", 0x5CFE7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setlel<.f><.cc> RB,RB,ximm 01011bbb11111110FBBB1111000QQQQQ. */
+{ "setlel", 0x58FE0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setlel<.f> RA,ximm,u6 0101110001111110F111uuuuuuaaaaaa. */
+{ "setlel", 0x5C7E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setlel<.f> 0,ximm,u6 0101110001111110F111uuuuuu111110. */
+{ "setlel", 0x5C7E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setlel<.f><.cc> 0,ximm,u6 0101110011111110F111uuuuuu1QQQQQ. */
+{ "setlel", 0x5CFE7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlel<.f> RA,limm,RC 0101111000111110F111ccccccaaaaaa. */
+{ "setlel", 0x5E3E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setlel<.f> RA,RB,limm 01011bbb00111110FBBB111110aaaaaa. */
+{ "setlel", 0x583E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setlel<.f> 0,limm,RC 0101111000111110F111cccccc111110. */
+{ "setlel", 0x5E3E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setlel<.f> 0,RB,limm 01011bbb00111110FBBB111110111110. */
+{ "setlel", 0x583E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setlel<.f><.cc> 0,limm,RC 0101111011111110F111cccccc0QQQQQ. */
+{ "setlel", 0x5EFE7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setlel<.f><.cc> RB,RB,limm 01011bbb11111110FBBB1111100QQQQQ. */
+{ "setlel", 0x58FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setlel<.f> RA,limm,u6 0101111001111110F111uuuuuuaaaaaa. */
+{ "setlel", 0x5E7E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlel<.f> 0,limm,u6 0101111001111110F111uuuuuu111110. */
+{ "setlel", 0x5E7E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlel<.f><.cc> 0,limm,u6 0101111011111110F111uuuuuu1QQQQQ. */
+{ "setlel", 0x5EFE7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlel<.f> 0,ximm,s12 0101110010111110F111ssssssSSSSSS. */
+{ "setlel", 0x5CBE7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setlel<.f> 0,limm,s12 0101111010111110F111ssssssSSSSSS. */
+{ "setlel", 0x5EBE7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setlel<.f> RA,ximm,ximm 0101110000111110F111111100aaaaaa. */
+{ "setlel", 0x5C3E7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setlel<.f> 0,ximm,ximm 0101110000111110F111111100111110. */
+{ "setlel", 0x5C3E7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setlel<.f><.cc> 0,ximm,ximm 0101110011111110F1111111000QQQQQ. */
+{ "setlel", 0x5CFE7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setlel<.f> RA,limm,limm 0101111000111110F111111110aaaaaa. */
+{ "setlel", 0x5E3E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setlel<.f> 0,limm,limm 0101111000111110F111111110111110. */
+{ "setlel", 0x5E3E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setlel<.f><.cc> 0,limm,limm 0101111011111110F1111111100QQQQQ. */
+{ "setlel", 0x5EFE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setlo<.f> a,b,c 00100bbb00111100FBBBCCCCCCAAAAAA. */
+{ "setlo", 0x203C0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* setlo<.f> 0,b,c 00100bbb00111100FBBBCCCCCC111110. */
+{ "setlo", 0x203C003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setlo<.f><.cc> b,b,c 00100bbb11111100FBBBCCCCCC0QQQQQ. */
+{ "setlo", 0x20FC0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setlo<.f> a,b,u6 00100bbb01111100FBBBuuuuuuAAAAAA. */
+{ "setlo", 0x207C0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setlo<.f> 0,b,u6 00100bbb01111100FBBBuuuuuu111110. */
+{ "setlo", 0x207C003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setlo<.f><.cc> b,b,u6 00100bbb11111100FBBBuuuuuu1QQQQQ. */
+{ "setlo", 0x20FC0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlo<.f> b,b,s12 00100bbb10111100FBBBssssssSSSSSS. */
+{ "setlo", 0x20BC0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setlo<.f> a,limm,c 0010011000111100F111CCCCCCAAAAAA. */
+{ "setlo", 0x263C7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setlo<.f> a,b,limm 00100bbb00111100FBBB111110AAAAAA. */
+{ "setlo", 0x203C0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setlo<.f> 0,limm,c 0010011000111100F111CCCCCC111110. */
+{ "setlo", 0x263C703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setlo<.f> 0,b,limm 00100bbb00111100FBBB111110111110. */
+{ "setlo", 0x203C0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setlo<.f><.cc> b,b,limm 00100bbb11111100FBBB1111100QQQQQ. */
+{ "setlo", 0x20FC0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setlo<.f><.cc> 0,limm,c 0010011011111100F111CCCCCC0QQQQQ. */
+{ "setlo", 0x26FC7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setlo<.f> a,limm,u6 0010011001111100F111uuuuuuAAAAAA. */
+{ "setlo", 0x267C7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlo<.f> 0,limm,u6 0010011001111100F111uuuuuu111110. */
+{ "setlo", 0x267C703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlo<.f><.cc> 0,limm,u6 0010011011111100F111uuuuuu1QQQQQ. */
+{ "setlo", 0x26FC7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlo<.f> 0,limm,s12 0010011010111100F111ssssssSSSSSS. */
+{ "setlo", 0x26BC7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setlo<.f> a,limm,limm 0010011000111100F111111110AAAAAA. */
+{ "setlo", 0x263C7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setlo<.f> 0,limm,limm 0010011000111100F111111110111110. */
+{ "setlo", 0x263C7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setlo<.f><.cc> 0,limm,limm 0010011011111100F1111111100QQQQQ. */
+{ "setlo", 0x26FC7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setlol<.f> RA,RB,RC 01011bbb00111100FBBBccccccaaaaaa. */
+{ "setlol", 0x583C0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setlol<.f> 0,RB,RC 01011bbb00111100FBBBcccccc111110. */
+{ "setlol", 0x583C003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setlol<.f><.cc> RB,RB,RC 01011bbb11111100FBBBcccccc0QQQQQ. */
+{ "setlol", 0x58FC0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setlol<.f> RA,RB,u6 01011bbb01111100FBBBuuuuuuaaaaaa. */
+{ "setlol", 0x587C0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setlol<.f> 0,RB,u6 01011bbb01111100FBBBuuuuuu111110. */
+{ "setlol", 0x587C003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setlol<.f><.cc> RB,RB,u6 01011bbb11111100FBBBuuuuuu1QQQQQ. */
+{ "setlol", 0x58FC0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlol<.f> RB,RB,s12 01011bbb10111100FBBBssssssSSSSSS. */
+{ "setlol", 0x58BC0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setlol<.f> RA,ximm,RC 0101110000111100F111ccccccaaaaaa. */
+{ "setlol", 0x5C3C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setlol<.f> RA,RB,ximm 01011bbb00111100FBBB111100aaaaaa. */
+{ "setlol", 0x583C0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setlol<.f> 0,ximm,RC 0101110000111100F111cccccc111110. */
+{ "setlol", 0x5C3C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setlol<.f> 0,RB,ximm 01011bbb00111100FBBB111100111110. */
+{ "setlol", 0x583C0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setlol<.f><.cc> 0,ximm,RC 0101110011111100F111cccccc0QQQQQ. */
+{ "setlol", 0x5CFC7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setlol<.f><.cc> RB,RB,ximm 01011bbb11111100FBBB1111000QQQQQ. */
+{ "setlol", 0x58FC0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setlol<.f> RA,ximm,u6 0101110001111100F111uuuuuuaaaaaa. */
+{ "setlol", 0x5C7C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setlol<.f> 0,ximm,u6 0101110001111100F111uuuuuu111110. */
+{ "setlol", 0x5C7C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setlol<.f><.cc> 0,ximm,u6 0101110011111100F111uuuuuu1QQQQQ. */
+{ "setlol", 0x5CFC7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlol<.f> RA,limm,RC 0101111000111100F111ccccccaaaaaa. */
+{ "setlol", 0x5E3C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setlol<.f> RA,RB,limm 01011bbb00111100FBBB111110aaaaaa. */
+{ "setlol", 0x583C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setlol<.f> 0,limm,RC 0101111000111100F111cccccc111110. */
+{ "setlol", 0x5E3C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setlol<.f> 0,RB,limm 01011bbb00111100FBBB111110111110. */
+{ "setlol", 0x583C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setlol<.f><.cc> 0,limm,RC 0101111011111100F111cccccc0QQQQQ. */
+{ "setlol", 0x5EFC7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setlol<.f><.cc> RB,RB,limm 01011bbb11111100FBBB1111100QQQQQ. */
+{ "setlol", 0x58FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setlol<.f> RA,limm,u6 0101111001111100F111uuuuuuaaaaaa. */
+{ "setlol", 0x5E7C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlol<.f> 0,limm,u6 0101111001111100F111uuuuuu111110. */
+{ "setlol", 0x5E7C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlol<.f><.cc> 0,limm,u6 0101111011111100F111uuuuuu1QQQQQ. */
+{ "setlol", 0x5EFC7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlol<.f> 0,ximm,s12 0101110010111100F111ssssssSSSSSS. */
+{ "setlol", 0x5CBC7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setlol<.f> 0,limm,s12 0101111010111100F111ssssssSSSSSS. */
+{ "setlol", 0x5EBC7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setlol<.f> RA,ximm,ximm 0101110000111100F111111100aaaaaa. */
+{ "setlol", 0x5C3C7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setlol<.f> 0,ximm,ximm 0101110000111100F111111100111110. */
+{ "setlol", 0x5C3C7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setlol<.f><.cc> 0,ximm,ximm 0101110011111100F1111111000QQQQQ. */
+{ "setlol", 0x5CFC7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setlol<.f> RA,limm,limm 0101111000111100F111111110aaaaaa. */
+{ "setlol", 0x5E3C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setlol<.f> 0,limm,limm 0101111000111100F111111110111110. */
+{ "setlol", 0x5E3C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setlol<.f><.cc> 0,limm,limm 0101111011111100F1111111100QQQQQ. */
+{ "setlol", 0x5EFC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setlt<.f> a,b,c 00100bbb00111010FBBBCCCCCCAAAAAA. */
+{ "setlt", 0x203A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* setlt<.f> 0,b,c 00100bbb00111010FBBBCCCCCC111110. */
+{ "setlt", 0x203A003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setlt<.f><.cc> b,b,c 00100bbb11111010FBBBCCCCCC0QQQQQ. */
+{ "setlt", 0x20FA0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setlt<.f> a,b,u6 00100bbb01111010FBBBuuuuuuAAAAAA. */
+{ "setlt", 0x207A0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setlt<.f> 0,b,u6 00100bbb01111010FBBBuuuuuu111110. */
+{ "setlt", 0x207A003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setlt<.f><.cc> b,b,u6 00100bbb11111010FBBBuuuuuu1QQQQQ. */
+{ "setlt", 0x20FA0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlt<.f> b,b,s12 00100bbb10111010FBBBssssssSSSSSS. */
+{ "setlt", 0x20BA0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setlt<.f> a,limm,c 0010011000111010F111CCCCCCAAAAAA. */
+{ "setlt", 0x263A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setlt<.f> a,b,limm 00100bbb00111010FBBB111110AAAAAA. */
+{ "setlt", 0x203A0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setlt<.f> 0,limm,c 0010011000111010F111CCCCCC111110. */
+{ "setlt", 0x263A703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setlt<.f> 0,b,limm 00100bbb00111010FBBB111110111110. */
+{ "setlt", 0x203A0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setlt<.f><.cc> b,b,limm 00100bbb11111010FBBB1111100QQQQQ. */
+{ "setlt", 0x20FA0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setlt<.f><.cc> 0,limm,c 0010011011111010F111CCCCCC0QQQQQ. */
+{ "setlt", 0x26FA7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setlt<.f> a,limm,u6 0010011001111010F111uuuuuuAAAAAA. */
+{ "setlt", 0x267A7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlt<.f> 0,limm,u6 0010011001111010F111uuuuuu111110. */
+{ "setlt", 0x267A703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlt<.f><.cc> 0,limm,u6 0010011011111010F111uuuuuu1QQQQQ. */
+{ "setlt", 0x26FA7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlt<.f> 0,limm,s12 0010011010111010F111ssssssSSSSSS. */
+{ "setlt", 0x26BA7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setlt<.f> a,limm,limm 0010011000111010F111111110AAAAAA. */
+{ "setlt", 0x263A7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setlt<.f> 0,limm,limm 0010011000111010F111111110111110. */
+{ "setlt", 0x263A7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setlt<.f><.cc> 0,limm,limm 0010011011111010F1111111100QQQQQ. */
+{ "setlt", 0x26FA7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setltl<.f> RA,RB,RC 01011bbb00111010FBBBccccccaaaaaa. */
+{ "setltl", 0x583A0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setltl<.f> 0,RB,RC 01011bbb00111010FBBBcccccc111110. */
+{ "setltl", 0x583A003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setltl<.f><.cc> RB,RB,RC 01011bbb11111010FBBBcccccc0QQQQQ. */
+{ "setltl", 0x58FA0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setltl<.f> RA,RB,u6 01011bbb01111010FBBBuuuuuuaaaaaa. */
+{ "setltl", 0x587A0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setltl<.f> 0,RB,u6 01011bbb01111010FBBBuuuuuu111110. */
+{ "setltl", 0x587A003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setltl<.f><.cc> RB,RB,u6 01011bbb11111010FBBBuuuuuu1QQQQQ. */
+{ "setltl", 0x58FA0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setltl<.f> RB,RB,s12 01011bbb10111010FBBBssssssSSSSSS. */
+{ "setltl", 0x58BA0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setltl<.f> RA,ximm,RC 0101110000111010F111ccccccaaaaaa. */
+{ "setltl", 0x5C3A7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setltl<.f> RA,RB,ximm 01011bbb00111010FBBB111100aaaaaa. */
+{ "setltl", 0x583A0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setltl<.f> 0,ximm,RC 0101110000111010F111cccccc111110. */
+{ "setltl", 0x5C3A703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setltl<.f> 0,RB,ximm 01011bbb00111010FBBB111100111110. */
+{ "setltl", 0x583A0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setltl<.f><.cc> 0,ximm,RC 0101110011111010F111cccccc0QQQQQ. */
+{ "setltl", 0x5CFA7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setltl<.f><.cc> RB,RB,ximm 01011bbb11111010FBBB1111000QQQQQ. */
+{ "setltl", 0x58FA0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setltl<.f> RA,ximm,u6 0101110001111010F111uuuuuuaaaaaa. */
+{ "setltl", 0x5C7A7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setltl<.f> 0,ximm,u6 0101110001111010F111uuuuuu111110. */
+{ "setltl", 0x5C7A703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setltl<.f><.cc> 0,ximm,u6 0101110011111010F111uuuuuu1QQQQQ. */
+{ "setltl", 0x5CFA7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setltl<.f> RA,limm,RC 0101111000111010F111ccccccaaaaaa. */
+{ "setltl", 0x5E3A7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setltl<.f> RA,RB,limm 01011bbb00111010FBBB111110aaaaaa. */
+{ "setltl", 0x583A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setltl<.f> 0,limm,RC 0101111000111010F111cccccc111110. */
+{ "setltl", 0x5E3A703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setltl<.f> 0,RB,limm 01011bbb00111010FBBB111110111110. */
+{ "setltl", 0x583A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setltl<.f><.cc> 0,limm,RC 0101111011111010F111cccccc0QQQQQ. */
+{ "setltl", 0x5EFA7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setltl<.f><.cc> RB,RB,limm 01011bbb11111010FBBB1111100QQQQQ. */
+{ "setltl", 0x58FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setltl<.f> RA,limm,u6 0101111001111010F111uuuuuuaaaaaa. */
+{ "setltl", 0x5E7A7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setltl<.f> 0,limm,u6 0101111001111010F111uuuuuu111110. */
+{ "setltl", 0x5E7A703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setltl<.f><.cc> 0,limm,u6 0101111011111010F111uuuuuu1QQQQQ. */
+{ "setltl", 0x5EFA7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setltl<.f> 0,ximm,s12 0101110010111010F111ssssssSSSSSS. */
+{ "setltl", 0x5CBA7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setltl<.f> 0,limm,s12 0101111010111010F111ssssssSSSSSS. */
+{ "setltl", 0x5EBA7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setltl<.f> RA,ximm,ximm 0101110000111010F111111100aaaaaa. */
+{ "setltl", 0x5C3A7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setltl<.f> 0,ximm,ximm 0101110000111010F111111100111110. */
+{ "setltl", 0x5C3A7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setltl<.f><.cc> 0,ximm,ximm 0101110011111010F1111111000QQQQQ. */
+{ "setltl", 0x5CFA7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setltl<.f> RA,limm,limm 0101111000111010F111111110aaaaaa. */
+{ "setltl", 0x5E3A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setltl<.f> 0,limm,limm 0101111000111010F111111110111110. */
+{ "setltl", 0x5E3A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setltl<.f><.cc> 0,limm,limm 0101111011111010F1111111100QQQQQ. */
+{ "setltl", 0x5EFA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setne<.f> a,b,c 00100bbb00111001FBBBCCCCCCAAAAAA. */
+{ "setne", 0x20390000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* setne<.f> 0,b,c 00100bbb00111001FBBBCCCCCC111110. */
+{ "setne", 0x2039003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setne<.f><.cc> b,b,c 00100bbb11111001FBBBCCCCCC0QQQQQ. */
+{ "setne", 0x20F90000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setne<.f> a,b,u6 00100bbb01111001FBBBuuuuuuAAAAAA. */
+{ "setne", 0x20790000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setne<.f> 0,b,u6 00100bbb01111001FBBBuuuuuu111110. */
+{ "setne", 0x2079003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setne<.f><.cc> b,b,u6 00100bbb11111001FBBBuuuuuu1QQQQQ. */
+{ "setne", 0x20F90020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setne<.f> b,b,s12 00100bbb10111001FBBBssssssSSSSSS. */
+{ "setne", 0x20B90000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setne<.f> a,limm,c 0010011000111001F111CCCCCCAAAAAA. */
+{ "setne", 0x26397000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setne<.f> a,b,limm 00100bbb00111001FBBB111110AAAAAA. */
+{ "setne", 0x20390F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setne<.f> 0,limm,c 0010011000111001F111CCCCCC111110. */
+{ "setne", 0x2639703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setne<.f> 0,b,limm 00100bbb00111001FBBB111110111110. */
+{ "setne", 0x20390FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setne<.f><.cc> b,b,limm 00100bbb11111001FBBB1111100QQQQQ. */
+{ "setne", 0x20F90F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setne<.f><.cc> 0,limm,c 0010011011111001F111CCCCCC0QQQQQ. */
+{ "setne", 0x26F97000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setne<.f> a,limm,u6 0010011001111001F111uuuuuuAAAAAA. */
+{ "setne", 0x26797000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setne<.f> 0,limm,u6 0010011001111001F111uuuuuu111110. */
+{ "setne", 0x2679703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setne<.f><.cc> 0,limm,u6 0010011011111001F111uuuuuu1QQQQQ. */
+{ "setne", 0x26F97020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setne<.f> 0,limm,s12 0010011010111001F111ssssssSSSSSS. */
+{ "setne", 0x26B97000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setne<.f> a,limm,limm 0010011000111001F111111110AAAAAA. */
+{ "setne", 0x26397F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setne<.f> 0,limm,limm 0010011000111001F111111110111110. */
+{ "setne", 0x26397FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setne<.f><.cc> 0,limm,limm 0010011011111001F1111111100QQQQQ. */
+{ "setne", 0x26F97F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setnel<.f> RA,RB,RC 01011bbb00111001FBBBccccccaaaaaa. */
+{ "setnel", 0x58390000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setnel<.f> 0,RB,RC 01011bbb00111001FBBBcccccc111110. */
+{ "setnel", 0x5839003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setnel<.f><.cc> RB,RB,RC 01011bbb11111001FBBBcccccc0QQQQQ. */
+{ "setnel", 0x58F90000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setnel<.f> RA,RB,u6 01011bbb01111001FBBBuuuuuuaaaaaa. */
+{ "setnel", 0x58790000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setnel<.f> 0,RB,u6 01011bbb01111001FBBBuuuuuu111110. */
+{ "setnel", 0x5879003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setnel<.f><.cc> RB,RB,u6 01011bbb11111001FBBBuuuuuu1QQQQQ. */
+{ "setnel", 0x58F90020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setnel<.f> RB,RB,s12 01011bbb10111001FBBBssssssSSSSSS. */
+{ "setnel", 0x58B90000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setnel<.f> RA,ximm,RC 0101110000111001F111ccccccaaaaaa. */
+{ "setnel", 0x5C397000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setnel<.f> RA,RB,ximm 01011bbb00111001FBBB111100aaaaaa. */
+{ "setnel", 0x58390F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setnel<.f> 0,ximm,RC 0101110000111001F111cccccc111110. */
+{ "setnel", 0x5C39703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setnel<.f> 0,RB,ximm 01011bbb00111001FBBB111100111110. */
+{ "setnel", 0x58390F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setnel<.f><.cc> 0,ximm,RC 0101110011111001F111cccccc0QQQQQ. */
+{ "setnel", 0x5CF97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setnel<.f><.cc> RB,RB,ximm 01011bbb11111001FBBB1111000QQQQQ. */
+{ "setnel", 0x58F90F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setnel<.f> RA,ximm,u6 0101110001111001F111uuuuuuaaaaaa. */
+{ "setnel", 0x5C797000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setnel<.f> 0,ximm,u6 0101110001111001F111uuuuuu111110. */
+{ "setnel", 0x5C79703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setnel<.f><.cc> 0,ximm,u6 0101110011111001F111uuuuuu1QQQQQ. */
+{ "setnel", 0x5CF97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setnel<.f> RA,limm,RC 0101111000111001F111ccccccaaaaaa. */
+{ "setnel", 0x5E397000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setnel<.f> RA,RB,limm 01011bbb00111001FBBB111110aaaaaa. */
+{ "setnel", 0x58390F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setnel<.f> 0,limm,RC 0101111000111001F111cccccc111110. */
+{ "setnel", 0x5E39703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setnel<.f> 0,RB,limm 01011bbb00111001FBBB111110111110. */
+{ "setnel", 0x58390FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setnel<.f><.cc> 0,limm,RC 0101111011111001F111cccccc0QQQQQ. */
+{ "setnel", 0x5EF97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setnel<.f><.cc> RB,RB,limm 01011bbb11111001FBBB1111100QQQQQ. */
+{ "setnel", 0x58F90F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setnel<.f> RA,limm,u6 0101111001111001F111uuuuuuaaaaaa. */
+{ "setnel", 0x5E797000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setnel<.f> 0,limm,u6 0101111001111001F111uuuuuu111110. */
+{ "setnel", 0x5E79703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setnel<.f><.cc> 0,limm,u6 0101111011111001F111uuuuuu1QQQQQ. */
+{ "setnel", 0x5EF97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setnel<.f> 0,ximm,s12 0101110010111001F111ssssssSSSSSS. */
+{ "setnel", 0x5CB97000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setnel<.f> 0,limm,s12 0101111010111001F111ssssssSSSSSS. */
+{ "setnel", 0x5EB97000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setnel<.f> RA,ximm,ximm 0101110000111001F111111100aaaaaa. */
+{ "setnel", 0x5C397F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setnel<.f> 0,ximm,ximm 0101110000111001F111111100111110. */
+{ "setnel", 0x5C397F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setnel<.f><.cc> 0,ximm,ximm 0101110011111001F1111111000QQQQQ. */
+{ "setnel", 0x5CF97F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setnel<.f> RA,limm,limm 0101111000111001F111111110aaaaaa. */
+{ "setnel", 0x5E397F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setnel<.f> 0,limm,limm 0101111000111001F111111110111110. */
+{ "setnel", 0x5E397FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setnel<.f><.cc> 0,limm,limm 0101111011111001F1111111100QQQQQ. */
+{ "setnel", 0x5EF97F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sexb<.f> b,c 00100bbb00101111FBBBCCCCCC000101. */
+{ "sexb", 0x202F0005, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexb<.f> 0,c 0010011000101111F111CCCCCC000101. */
+{ "sexb", 0x262F7005, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexb<.f> b,u6 00100bbb01101111FBBBuuuuuu000101. */
+{ "sexb", 0x206F0005, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexb<.f> 0,u6 0010011001101111F111uuuuuu000101. */
+{ "sexb", 0x266F7005, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexb<.f> b,limm 00100bbb00101111FBBB111110000101. */
+{ "sexb", 0x202F0F85, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexb<.f> 0,limm 0010011000101111F111111110000101. */
+{ "sexb", 0x262F7F85, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sexbl<.f> RB,RC 01011bbb00101111FBBBcccccc000101. */
+{ "sexbl", 0x582F0005, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexbl<.f> 0,RC 0101111000101111F111cccccc000101. */
+{ "sexbl", 0x5E2F7005, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexbl<.f> RB,u6 01011bbb01101111FBBBuuuuuu000101. */
+{ "sexbl", 0x586F0005, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexbl<.f> 0,u6 0101111001101111F111uuuuuu000101. */
+{ "sexbl", 0x5E6F7005, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexbl<.f> RB,ximm 01011bbb00101111FBBB111100000101. */
+{ "sexbl", 0x582F0F05, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* sexbl<.f> 0,ximm 0101111000101111F111111100000101. */
+{ "sexbl", 0x5E2F7F05, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* sexbl<.f> RB,limm 01011bbb00101111FBBB111110000101. */
+{ "sexbl", 0x582F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexbl<.f> 0,limm 0101111000101111F111111110000101. */
+{ "sexbl", 0x5E2F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sexb_s b,c 01111bbbccc01101. */
+{ "sexb_s", 0x0000780D, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* sexh<.f> b,c 00100bbb00101111FBBBCCCCCC000110. */
+{ "sexh", 0x202F0006, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexh<.f> 0,c 0010011000101111F111CCCCCC000110. */
+{ "sexh", 0x262F7006, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexh<.f> b,u6 00100bbb01101111FBBBuuuuuu000110. */
+{ "sexh", 0x206F0006, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexh<.f> 0,u6 0010011001101111F111uuuuuu000110. */
+{ "sexh", 0x266F7006, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexh<.f> b,limm 00100bbb00101111FBBB111110000110. */
+{ "sexh", 0x202F0F86, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexh<.f> 0,limm 0010011000101111F111111110000110. */
+{ "sexh", 0x262F7F86, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sexhl<.f> RB,RC 01011bbb00101111FBBBcccccc000110. */
+{ "sexhl", 0x582F0006, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexhl<.f> 0,RC 0101111000101111F111cccccc000110. */
+{ "sexhl", 0x5E2F7006, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexhl<.f> RB,u6 01011bbb01101111FBBBuuuuuu000110. */
+{ "sexhl", 0x586F0006, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexhl<.f> 0,u6 0101111001101111F111uuuuuu000110. */
+{ "sexhl", 0x5E6F7006, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexhl<.f> RB,ximm 01011bbb00101111FBBB111100000110. */
+{ "sexhl", 0x582F0F06, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* sexhl<.f> 0,ximm 0101111000101111F111111100000110. */
+{ "sexhl", 0x5E2F7F06, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* sexhl<.f> RB,limm 01011bbb00101111FBBB111110000110. */
+{ "sexhl", 0x582F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexhl<.f> 0,limm 0101111000101111F111111110000110. */
+{ "sexhl", 0x5E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sexh_s b,c 01111bbbccc01110. */
+{ "sexh_s", 0x0000780E, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* sexwl<.f> RB,RC 01011bbb00101111FBBBcccccc000111. */
+{ "sexwl", 0x582F0007, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexwl<.f> 0,RC 0101111000101111F111cccccc000111. */
+{ "sexwl", 0x5E2F7007, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexwl<.f> RB,u6 01011bbb01101111FBBBuuuuuu000111. */
+{ "sexwl", 0x586F0007, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexwl<.f> 0,u6 0101111001101111F111uuuuuu000111. */
+{ "sexwl", 0x5E6F7007, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexwl<.f> RB,ximm 01011bbb00101111FBBB111100000111. */
+{ "sexwl", 0x582F0F07, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* sexwl<.f> 0,ximm 0101111000101111F111111100000111. */
+{ "sexwl", 0x5E2F7F07, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* sexwl<.f> RB,limm 01011bbb00101111FBBB111110000111. */
+{ "sexwl", 0x582F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexwl<.f> 0,limm 0101111000101111F111111110000111. */
+{ "sexwl", 0x5E2F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sleep c 00100001001011110000CCCCCC111111. */
+{ "sleep", 0x212F003F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { RC }, { 0 }},
+
+/* sleep u6 00100001011011110000uuuuuu111111. */
+{ "sleep", 0x216F003F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { UIMM6_20 }, { 0 }},
+
+/* sleep limm 00100001001011110000111110111111. */
+{ "sleep", 0x212F0FBF, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { LIMM }, { 0 }},
+
+/* sleep 00100001011011110000000000111111. */
+{ "sleep", 0x216F003F, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* sr b,c 00100bbb00101011RBBBCCCCCCRRRRRR. */
+{ "sr", 0x202B0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* sr b,u6 00100bbb01101011RBBBuuuuuu000000. */
+{ "sr", 0x206B0000, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* sr b,s12 00100bbb10101011RBBBssssssSSSSSS. */
+{ "sr", 0x20AB0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* sr limm,c 0010011000101011R111CCCCCCRRRRRR. */
+{ "sr", 0x262B7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* sr b,limm 00100bbb00101011RBBB111110RRRRRR. */
+{ "sr", 0x202B0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* sr limm,u6 0010011001101011R111uuuuuu000000. */
+{ "sr", 0x266B7000, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* sr limm,s12 0010011010101011R111ssssssSSSSSS. */
+{ "sr", 0x26AB7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* sr limm,limm 0010011000101011R111111110RRRRRR. */
+{ "sr", 0x262B7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 }},
+
+/* srl RB,RC 01011bbb001010110BBBccccccRRRRRR. */
+{ "srl", 0x582B0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* srl RB,u6 01011bbb011010110BBBuuuuuuRRRRRR. */
+{ "srl", 0x586B0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* srl RB,s12 01011bbb101010110BBBssssssSSSSSS. */
+{ "srl", 0x58AB0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* srl RB,ximm 01011bbb001010110BBB111100RRRRRR. */
+{ "srl", 0x582B0F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, XIMM, BRAKETdup }, { 0 }},
+
+/* srl RB,limm 01011bbb001010110BBB111110RRRRRR. */
+{ "srl", 0x582B0F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* st<zz><.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZ0 -> st c ,[b,s9] */
+/* st<zz><.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaaZZ1 -> st w6 ,[b,s9] */
+/* st<zz><.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110DaaZZ0 -> st c=62,[b,s9] */
+/* st<zz><.di><.aa> c,limm,s9 00011110ssssssssS111CCCCCCDRRZZ0 -> st c ,[b=62,s9] */
+/* st<zz><.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDRRZZ1 -> st w6 ,[b=62,s9] */
+/* st<zz><.di><.aa> limm,limm,s9 00011110ssssssssS111111110DRRZZ0 -> st c=62,[b=62,s9] */
+{ "st", 0x18000000, 0xF8000001, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x18000001, 0xF8000001, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZW6, C_DI26, C_AA27 }},
+{ "st", 0x18000001, 0xF8000021, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZH1, C_AA27 }},
+{ "st", 0x18000F80, 0xF8000FC1, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+{ "st", 0x1E007000, 0xFF007001, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26 }},
+{ "st", 0x1E007001, 0xFF007001, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZW6, C_DI26 }},
+{ "st", 0x1E007001, 0xFF007021, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZH1 }},
+{ "st", 0x1E007F80, 0xFF007FC1, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26 }},
+
+/* stb_sZZ_B c,b,u5 10101bbbcccuuuuu. */
+{ "stb_s", 0x0000A800, 0x0000F800,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B }},
+
+/* stb_sZZ_B b,SP,u7 11000bbb011uuuuu. */
+{ "stb_s", 0x0000C060, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B }},
+
+/* std<.aa>.<di> c,b 00011bbb000000000BBBCCCCCCDaa110 -> std c,[b,s9=0] */
+/* std<.aa>.<di> w6,b 00011bbb000000000BBBwwwwwwDaa111 -> std w6,[b,s9=0] */
+/* std<.aa>.<di> limm,b 00011bbb000000000BBB111110Daa110 -> std c=62,[b,s9=0] */
+/* std<.aa>.<di> c,limm 00011110000000000111CCCCCCDaa110 -> std c,[b=62,s9=0] */
+/* std<.aa>.<di> w6,limm 00011110000000000111wwwwwwDaa111 -> std w6,[b=62,s9=0] */
+/* std<.aa>.<di> limm,limm 00011110000000000111111110Daa110 -> std c=62,[b=62,s9=0] */
+{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARC32, STORE, NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 }},
+{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 }},
+{ "std", 0x18000F86, 0xF8FF8FC7, ARC_OPCODE_ARC32, STORE, NONE, { LIMM, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 }},
+{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARC32, STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_AA27 }},
+{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_AA27 }},
+{ "std", 0x1E007F86, 0xFFFFFFC7, ARC_OPCODE_ARC32, STORE, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI26, C_AA27 }},
+
+/* std<.aa>.<di> c,b,s9 00011bbbssssssssSBBBCCCCCCDaa110 -> std c,[b,s9] */
+/* std<.aa>.<di> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaa111 -> std w6,[b,s9] */
+/* std<.aa>.<di> limm,b,s9 00011bbbssssssssSBBB111110Daa110 -> std c=62,[b,s9] */
+/* std<.aa>.<di> c,limm,s9 00011110ssssssssS111CCCCCCDaa110 -> std c,[b=62,s9] */
+/* std<.aa>.<di> w6,limm,s9 00011110ssssssssS111wwwwwwDaa111 -> std w6,[b=62,s9] */
+/* std<.aa>.<di> limm,limm,s9 00011110ssssssssS111111110Daa110 -> std c=62,[b=62,s9] */
+{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARC32, STORE, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
+{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
+{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARC32, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
+{ "std", 0x1E007006, 0xFF007007, ARC_OPCODE_ARC32, STORE, NONE, { RCD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
+{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
+{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARC32, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
+
+/* sth_sZZ_H c,b,u6 10110bbbcccuuuuu. */
+{ "sth_s", 0x0000B000, 0x0000F800,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }},
+
+/* st_s b,SP,u7 11000bbb010uuuuu. */
+{ "st_s", 0x0000C040, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* st_s c,b,u7 10100bbbcccuuuuu. */
+{ "st_s", 0x0000A000, 0x0000F800,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* st_s R0,GP,s11 01010SSSSSS10sss. */
+{ "st_s", 0x00005010, 0x0000F818,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, CD2, { R0_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }},
+
+/* sub<.f> a,b,c 00100bbb00000010FBBBCCCCCCAAAAAA. */
+{ "sub", 0x20020000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub<.f> 0,b,c 00100bbb00000010FBBBCCCCCC111110. */
+{ "sub", 0x2002003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub<.f><.cc> b,b,c 00100bbb11000010FBBBCCCCCC0QQQQQ. */
+{ "sub", 0x20C20000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
+{ "sub", 0x20420000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub<.f> 0,b,u6 00100bbb01000010FBBBuuuuuu111110. */
+{ "sub", 0x2042003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub<.f><.cc> b,b,u6 00100bbb11000010FBBBuuuuuu1QQQQQ. */
+{ "sub", 0x20C20020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub<.f> b,b,s12 00100bbb10000010FBBBssssssSSSSSS. */
+{ "sub", 0x20820000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub<.f> a,limm,c 0010011000000010F111CCCCCCAAAAAA. */
+{ "sub", 0x26027000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
+{ "sub", 0x20020F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub<.f> 0,limm,c 0010011000000010F111CCCCCC111110. */
+{ "sub", 0x2602703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub<.f> 0,b,limm 00100bbb00000010FBBB111110111110. */
+{ "sub", 0x20020FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub<.f><.cc> b,b,limm 00100bbb11000010FBBB1111100QQQQQ. */
+{ "sub", 0x20C20F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub<.f><.cc> 0,limm,c 0010011011000010F111CCCCCC0QQQQQ. */
+{ "sub", 0x26C27000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub<.f> a,limm,u6 0010011001000010F111uuuuuuAAAAAA. */
+{ "sub", 0x26427000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub<.f> 0,limm,u6 0010011001000010F111uuuuuu111110. */
+{ "sub", 0x2642703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub<.f><.cc> 0,limm,u6 0010011011000010F111uuuuuu1QQQQQ. */
+{ "sub", 0x26C27020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub<.f> 0,limm,s12 0010011010000010F111ssssssSSSSSS. */
+{ "sub", 0x26827000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub<.f> a,limm,limm 0010011000000010F111111110AAAAAA. */
+{ "sub", 0x26027F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub<.f> 0,limm,limm 0010011000000010F111111110111110. */
+{ "sub", 0x26027FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub<.f><.cc> 0,limm,limm 0010011011000010F1111111100QQQQQ. */
+{ "sub", 0x26C27F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub1<.f> a,b,c 00100bbb00010111FBBBCCCCCCAAAAAA. */
+{ "sub1", 0x20170000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub1<.f> 0,b,c 00100bbb00010111FBBBCCCCCC111110. */
+{ "sub1", 0x2017003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub1<.f><.cc> b,b,c 00100bbb11010111FBBBCCCCCC0QQQQQ. */
+{ "sub1", 0x20D70000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub1<.f> a,b,u6 00100bbb01010111FBBBuuuuuuAAAAAA. */
+{ "sub1", 0x20570000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub1<.f> 0,b,u6 00100bbb01010111FBBBuuuuuu111110. */
+{ "sub1", 0x2057003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub1<.f><.cc> b,b,u6 00100bbb11010111FBBBuuuuuu1QQQQQ. */
+{ "sub1", 0x20D70020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1<.f> b,b,s12 00100bbb10010111FBBBssssssSSSSSS. */
+{ "sub1", 0x20970000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub1<.f> a,limm,c 0010011000010111F111CCCCCCAAAAAA. */
+{ "sub1", 0x26177000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub1<.f> a,b,limm 00100bbb00010111FBBB111110AAAAAA. */
+{ "sub1", 0x20170F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub1<.f> 0,limm,c 0010011000010111F111CCCCCC111110. */
+{ "sub1", 0x2617703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub1<.f> 0,b,limm 00100bbb00010111FBBB111110111110. */
+{ "sub1", 0x20170FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub1<.f><.cc> b,b,limm 00100bbb11010111FBBB1111100QQQQQ. */
+{ "sub1", 0x20D70F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub1<.f><.cc> 0,limm,c 0010011011010111F111CCCCCC0QQQQQ. */
+{ "sub1", 0x26D77000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub1<.f> a,limm,u6 0010011001010111F111uuuuuuAAAAAA. */
+{ "sub1", 0x26577000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub1<.f> 0,limm,u6 0010011001010111F111uuuuuu111110. */
+{ "sub1", 0x2657703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub1<.f><.cc> 0,limm,u6 0010011011010111F111uuuuuu1QQQQQ. */
+{ "sub1", 0x26D77020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1<.f> 0,limm,s12 0010011010010111F111ssssssSSSSSS. */
+{ "sub1", 0x26977000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub1<.f> a,limm,limm 0010011000010111F111111110AAAAAA. */
+{ "sub1", 0x26177F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub1<.f> 0,limm,limm 0010011000010111F111111110111110. */
+{ "sub1", 0x26177FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub1<.f><.cc> 0,limm,limm 0010011011010111F1111111100QQQQQ. */
+{ "sub1", 0x26D77F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,RB,RC 01011bbb00010111FBBBccccccaaaaaa. */
+{ "sub1l", 0x58170000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub1l<.f> 0,RB,RC 01011bbb00010111FBBBcccccc111110. */
+{ "sub1l", 0x5817003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub1l<.f><.cc> RB,RB,RC 01011bbb11010111FBBBcccccc0QQQQQ. */
+{ "sub1l", 0x58D70000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,RB,u6 01011bbb01010111FBBBuuuuuuaaaaaa. */
+{ "sub1l", 0x58570000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f> 0,RB,u6 01011bbb01010111FBBBuuuuuu111110. */
+{ "sub1l", 0x5857003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f><.cc> RB,RB,u6 01011bbb11010111FBBBuuuuuu1QQQQQ. */
+{ "sub1l", 0x58D70020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1l<.f> RB,RB,s12 01011bbb10010111FBBBssssssSSSSSS. */
+{ "sub1l", 0x58970000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub1l<.f> RA,ximm,RC 0101110000010111F111ccccccaaaaaa. */
+{ "sub1l", 0x5C177000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* sub1l<.f> RA,RB,ximm 01011bbb00010111FBBB111100aaaaaa. */
+{ "sub1l", 0x58170F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* sub1l<.f> 0,ximm,RC 0101110000010111F111cccccc111110. */
+{ "sub1l", 0x5C17703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* sub1l<.f> 0,RB,ximm 01011bbb00010111FBBB111100111110. */
+{ "sub1l", 0x58170F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* sub1l<.f><.cc> 0,ximm,RC 0101110011010111F111cccccc0QQQQQ. */
+{ "sub1l", 0x5CD77000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* sub1l<.f><.cc> RB,RB,ximm 01011bbb11010111FBBB1111000QQQQQ. */
+{ "sub1l", 0x58D70F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,ximm,u6 0101110001010111F111uuuuuuaaaaaa. */
+{ "sub1l", 0x5C577000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f> 0,ximm,u6 0101110001010111F111uuuuuu111110. */
+{ "sub1l", 0x5C57703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f><.cc> 0,ximm,u6 0101110011010111F111uuuuuu1QQQQQ. */
+{ "sub1l", 0x5CD77020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,limm,RC 0101111000010111F111ccccccaaaaaa. */
+{ "sub1l", 0x5E177000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub1l<.f> RA,RB,limm 01011bbb00010111FBBB111110aaaaaa. */
+{ "sub1l", 0x58170F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub1l<.f> 0,limm,RC 0101111000010111F111cccccc111110. */
+{ "sub1l", 0x5E17703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub1l<.f> 0,RB,limm 01011bbb00010111FBBB111110111110. */
+{ "sub1l", 0x58170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub1l<.f><.cc> 0,limm,RC 0101111011010111F111cccccc0QQQQQ. */
+{ "sub1l", 0x5ED77000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub1l<.f><.cc> RB,RB,limm 01011bbb11010111FBBB1111100QQQQQ. */
+{ "sub1l", 0x58D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,limm,u6 0101111001010111F111uuuuuuaaaaaa. */
+{ "sub1l", 0x5E577000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f> 0,limm,u6 0101111001010111F111uuuuuu111110. */
+{ "sub1l", 0x5E57703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f><.cc> 0,limm,u6 0101111011010111F111uuuuuu1QQQQQ. */
+{ "sub1l", 0x5ED77020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1l<.f> 0,ximm,s12 0101110010010111F111ssssssSSSSSS. */
+{ "sub1l", 0x5C977000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* sub1l<.f> 0,limm,s12 0101111010010111F111ssssssSSSSSS. */
+{ "sub1l", 0x5E977000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub1l<.f> RA,ximm,ximm 0101110000010111F111111100aaaaaa. */
+{ "sub1l", 0x5C177F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* sub1l<.f> 0,ximm,ximm 0101110000010111F111111100111110. */
+{ "sub1l", 0x5C177F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* sub1l<.f><.cc> 0,ximm,ximm 0101110011010111F1111111000QQQQQ. */
+{ "sub1l", 0x5CD77F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,limm,limm 0101111000010111F111111110aaaaaa. */
+{ "sub1l", 0x5E177F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub1l<.f> 0,limm,limm 0101111000010111F111111110111110. */
+{ "sub1l", 0x5E177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub1l<.f><.cc> 0,limm,limm 0101111011010111F1111111100QQQQQ. */
+{ "sub1l", 0x5ED77F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub2<.f> a,b,c 00100bbb00011000FBBBCCCCCCAAAAAA. */
+{ "sub2", 0x20180000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub2<.f> 0,b,c 00100bbb00011000FBBBCCCCCC111110. */
+{ "sub2", 0x2018003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub2<.f><.cc> b,b,c 00100bbb11011000FBBBCCCCCC0QQQQQ. */
+{ "sub2", 0x20D80000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub2<.f> a,b,u6 00100bbb01011000FBBBuuuuuuAAAAAA. */
+{ "sub2", 0x20580000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub2<.f> 0,b,u6 00100bbb01011000FBBBuuuuuu111110. */
+{ "sub2", 0x2058003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub2<.f><.cc> b,b,u6 00100bbb11011000FBBBuuuuuu1QQQQQ. */
+{ "sub2", 0x20D80020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2<.f> b,b,s12 00100bbb10011000FBBBssssssSSSSSS. */
+{ "sub2", 0x20980000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub2<.f> a,limm,c 0010011000011000F111CCCCCCAAAAAA. */
+{ "sub2", 0x26187000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub2<.f> a,b,limm 00100bbb00011000FBBB111110AAAAAA. */
+{ "sub2", 0x20180F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub2<.f> 0,limm,c 0010011000011000F111CCCCCC111110. */
+{ "sub2", 0x2618703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub2<.f> 0,b,limm 00100bbb00011000FBBB111110111110. */
+{ "sub2", 0x20180FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub2<.f><.cc> b,b,limm 00100bbb11011000FBBB1111100QQQQQ. */
+{ "sub2", 0x20D80F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub2<.f><.cc> 0,limm,c 0010011011011000F111CCCCCC0QQQQQ. */
+{ "sub2", 0x26D87000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub2<.f> a,limm,u6 0010011001011000F111uuuuuuAAAAAA. */
+{ "sub2", 0x26587000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub2<.f> 0,limm,u6 0010011001011000F111uuuuuu111110. */
+{ "sub2", 0x2658703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub2<.f><.cc> 0,limm,u6 0010011011011000F111uuuuuu1QQQQQ. */
+{ "sub2", 0x26D87020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2<.f> 0,limm,s12 0010011010011000F111ssssssSSSSSS. */
+{ "sub2", 0x26987000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub2<.f> a,limm,limm 0010011000011000F111111110AAAAAA. */
+{ "sub2", 0x26187F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub2<.f> 0,limm,limm 0010011000011000F111111110111110. */
+{ "sub2", 0x26187FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub2<.f><.cc> 0,limm,limm 0010011011011000F1111111100QQQQQ. */
+{ "sub2", 0x26D87F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,RB,RC 01011bbb00011000FBBBccccccaaaaaa. */
+{ "sub2l", 0x58180000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub2l<.f> 0,RB,RC 01011bbb00011000FBBBcccccc111110. */
+{ "sub2l", 0x5818003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub2l<.f><.cc> RB,RB,RC 01011bbb11011000FBBBcccccc0QQQQQ. */
+{ "sub2l", 0x58D80000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,RB,u6 01011bbb01011000FBBBuuuuuuaaaaaa. */
+{ "sub2l", 0x58580000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f> 0,RB,u6 01011bbb01011000FBBBuuuuuu111110. */
+{ "sub2l", 0x5858003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f><.cc> RB,RB,u6 01011bbb11011000FBBBuuuuuu1QQQQQ. */
+{ "sub2l", 0x58D80020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2l<.f> RB,RB,s12 01011bbb10011000FBBBssssssSSSSSS. */
+{ "sub2l", 0x58980000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub2l<.f> RA,ximm,RC 0101110000011000F111ccccccaaaaaa. */
+{ "sub2l", 0x5C187000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* sub2l<.f> RA,RB,ximm 01011bbb00011000FBBB111100aaaaaa. */
+{ "sub2l", 0x58180F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* sub2l<.f> 0,ximm,RC 0101110000011000F111cccccc111110. */
+{ "sub2l", 0x5C18703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* sub2l<.f> 0,RB,ximm 01011bbb00011000FBBB111100111110. */
+{ "sub2l", 0x58180F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* sub2l<.f><.cc> 0,ximm,RC 0101110011011000F111cccccc0QQQQQ. */
+{ "sub2l", 0x5CD87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* sub2l<.f><.cc> RB,RB,ximm 01011bbb11011000FBBB1111000QQQQQ. */
+{ "sub2l", 0x58D80F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,ximm,u6 0101110001011000F111uuuuuuaaaaaa. */
+{ "sub2l", 0x5C587000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f> 0,ximm,u6 0101110001011000F111uuuuuu111110. */
+{ "sub2l", 0x5C58703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f><.cc> 0,ximm,u6 0101110011011000F111uuuuuu1QQQQQ. */
+{ "sub2l", 0x5CD87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,limm,RC 0101111000011000F111ccccccaaaaaa. */
+{ "sub2l", 0x5E187000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub2l<.f> RA,RB,limm 01011bbb00011000FBBB111110aaaaaa. */
+{ "sub2l", 0x58180F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub2l<.f> 0,limm,RC 0101111000011000F111cccccc111110. */
+{ "sub2l", 0x5E18703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub2l<.f> 0,RB,limm 01011bbb00011000FBBB111110111110. */
+{ "sub2l", 0x58180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub2l<.f><.cc> 0,limm,RC 0101111011011000F111cccccc0QQQQQ. */
+{ "sub2l", 0x5ED87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub2l<.f><.cc> RB,RB,limm 01011bbb11011000FBBB1111100QQQQQ. */
+{ "sub2l", 0x58D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,limm,u6 0101111001011000F111uuuuuuaaaaaa. */
+{ "sub2l", 0x5E587000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f> 0,limm,u6 0101111001011000F111uuuuuu111110. */
+{ "sub2l", 0x5E58703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f><.cc> 0,limm,u6 0101111011011000F111uuuuuu1QQQQQ. */
+{ "sub2l", 0x5ED87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2l<.f> 0,ximm,s12 0101110010011000F111ssssssSSSSSS. */
+{ "sub2l", 0x5C987000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* sub2l<.f> 0,limm,s12 0101111010011000F111ssssssSSSSSS. */
+{ "sub2l", 0x5E987000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub2l<.f> RA,ximm,ximm 0101110000011000F111111100aaaaaa. */
+{ "sub2l", 0x5C187F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* sub2l<.f> 0,ximm,ximm 0101110000011000F111111100111110. */
+{ "sub2l", 0x5C187F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* sub2l<.f><.cc> 0,ximm,ximm 0101110011011000F1111111000QQQQQ. */
+{ "sub2l", 0x5CD87F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,limm,limm 0101111000011000F111111110aaaaaa. */
+{ "sub2l", 0x5E187F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub2l<.f> 0,limm,limm 0101111000011000F111111110111110. */
+{ "sub2l", 0x5E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub2l<.f><.cc> 0,limm,limm 0101111011011000F1111111100QQQQQ. */
+{ "sub2l", 0x5ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub3<.f> a,b,c 00100bbb00011001FBBBCCCCCCAAAAAA. */
+{ "sub3", 0x20190000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub3<.f> 0,b,c 00100bbb00011001FBBBCCCCCC111110. */
+{ "sub3", 0x2019003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub3<.f><.cc> b,b,c 00100bbb11011001FBBBCCCCCC0QQQQQ. */
+{ "sub3", 0x20D90000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub3<.f> a,b,u6 00100bbb01011001FBBBuuuuuuAAAAAA. */
+{ "sub3", 0x20590000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub3<.f> 0,b,u6 00100bbb01011001FBBBuuuuuu111110. */
+{ "sub3", 0x2059003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub3<.f><.cc> b,b,u6 00100bbb11011001FBBBuuuuuu1QQQQQ. */
+{ "sub3", 0x20D90020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3<.f> b,b,s12 00100bbb10011001FBBBssssssSSSSSS. */
+{ "sub3", 0x20990000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub3<.f> a,limm,c 0010011000011001F111CCCCCCAAAAAA. */
+{ "sub3", 0x26197000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub3<.f> a,b,limm 00100bbb00011001FBBB111110AAAAAA. */
+{ "sub3", 0x20190F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub3<.f> 0,limm,c 0010011000011001F111CCCCCC111110. */
+{ "sub3", 0x2619703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub3<.f> 0,b,limm 00100bbb00011001FBBB111110111110. */
+{ "sub3", 0x20190FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub3<.f><.cc> b,b,limm 00100bbb11011001FBBB1111100QQQQQ. */
+{ "sub3", 0x20D90F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub3<.f><.cc> 0,limm,c 0010011011011001F111CCCCCC0QQQQQ. */
+{ "sub3", 0x26D97000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub3<.f> a,limm,u6 0010011001011001F111uuuuuuAAAAAA. */
+{ "sub3", 0x26597000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub3<.f> 0,limm,u6 0010011001011001F111uuuuuu111110. */
+{ "sub3", 0x2659703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub3<.f><.cc> 0,limm,u6 0010011011011001F111uuuuuu1QQQQQ. */
+{ "sub3", 0x26D97020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3<.f> 0,limm,s12 0010011010011001F111ssssssSSSSSS. */
+{ "sub3", 0x26997000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub3<.f> a,limm,limm 0010011000011001F111111110AAAAAA. */
+{ "sub3", 0x26197F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub3<.f> 0,limm,limm 0010011000011001F111111110111110. */
+{ "sub3", 0x26197FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub3<.f><.cc> 0,limm,limm 0010011011011001F1111111100QQQQQ. */
+{ "sub3", 0x26D97F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,RB,RC 01011bbb00011001FBBBccccccaaaaaa. */
+{ "sub3l", 0x58190000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub3l<.f> 0,RB,RC 01011bbb00011001FBBBcccccc111110. */
+{ "sub3l", 0x5819003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub3l<.f><.cc> RB,RB,RC 01011bbb11011001FBBBcccccc0QQQQQ. */
+{ "sub3l", 0x58D90000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,RB,u6 01011bbb01011001FBBBuuuuuuaaaaaa. */
+{ "sub3l", 0x58590000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f> 0,RB,u6 01011bbb01011001FBBBuuuuuu111110. */
+{ "sub3l", 0x5859003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f><.cc> RB,RB,u6 01011bbb11011001FBBBuuuuuu1QQQQQ. */
+{ "sub3l", 0x58D90020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3l<.f> RB,RB,s12 01011bbb10011001FBBBssssssSSSSSS. */
+{ "sub3l", 0x58990000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub3l<.f> RA,ximm,RC 0101110000011001F111ccccccaaaaaa. */
+{ "sub3l", 0x5C197000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* sub3l<.f> RA,RB,ximm 01011bbb00011001FBBB111100aaaaaa. */
+{ "sub3l", 0x58190F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* sub3l<.f> 0,ximm,RC 0101110000011001F111cccccc111110. */
+{ "sub3l", 0x5C19703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* sub3l<.f> 0,RB,ximm 01011bbb00011001FBBB111100111110. */
+{ "sub3l", 0x58190F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* sub3l<.f><.cc> 0,ximm,RC 0101110011011001F111cccccc0QQQQQ. */
+{ "sub3l", 0x5CD97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* sub3l<.f><.cc> RB,RB,ximm 01011bbb11011001FBBB1111000QQQQQ. */
+{ "sub3l", 0x58D90F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,ximm,u6 0101110001011001F111uuuuuuaaaaaa. */
+{ "sub3l", 0x5C597000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f> 0,ximm,u6 0101110001011001F111uuuuuu111110. */
+{ "sub3l", 0x5C59703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f><.cc> 0,ximm,u6 0101110011011001F111uuuuuu1QQQQQ. */
+{ "sub3l", 0x5CD97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,limm,RC 0101111000011001F111ccccccaaaaaa. */
+{ "sub3l", 0x5E197000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub3l<.f> RA,RB,limm 01011bbb00011001FBBB111110aaaaaa. */
+{ "sub3l", 0x58190F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub3l<.f> 0,limm,RC 0101111000011001F111cccccc111110. */
+{ "sub3l", 0x5E19703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub3l<.f> 0,RB,limm 01011bbb00011001FBBB111110111110. */
+{ "sub3l", 0x58190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub3l<.f><.cc> 0,limm,RC 0101111011011001F111cccccc0QQQQQ. */
+{ "sub3l", 0x5ED97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub3l<.f><.cc> RB,RB,limm 01011bbb11011001FBBB1111100QQQQQ. */
+{ "sub3l", 0x58D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,limm,u6 0101111001011001F111uuuuuuaaaaaa. */
+{ "sub3l", 0x5E597000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f> 0,limm,u6 0101111001011001F111uuuuuu111110. */
+{ "sub3l", 0x5E59703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f><.cc> 0,limm,u6 0101111011011001F111uuuuuu1QQQQQ. */
+{ "sub3l", 0x5ED97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3l<.f> 0,ximm,s12 0101110010011001F111ssssssSSSSSS. */
+{ "sub3l", 0x5C997000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* sub3l<.f> 0,limm,s12 0101111010011001F111ssssssSSSSSS. */
+{ "sub3l", 0x5E997000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub3l<.f> RA,ximm,ximm 0101110000011001F111111100aaaaaa. */
+{ "sub3l", 0x5C197F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* sub3l<.f> 0,ximm,ximm 0101110000011001F111111100111110. */
+{ "sub3l", 0x5C197F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* sub3l<.f><.cc> 0,ximm,ximm 0101110011011001F1111111000QQQQQ. */
+{ "sub3l", 0x5CD97F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,limm,limm 0101111000011001F111111110aaaaaa. */
+{ "sub3l", 0x5E197F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub3l<.f> 0,limm,limm 0101111000011001F111111110111110. */
+{ "sub3l", 0x5E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub3l<.f><.cc> 0,limm,limm 0101111011011001F1111111100QQQQQ. */
+{ "sub3l", 0x5ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* subl<.f> RA,RB,RC 01011bbb00000010FBBBccccccaaaaaa. */
+{ "subl", 0x58020000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* subl<.f> 0,RB,RC 01011bbb00000010FBBBcccccc111110. */
+{ "subl", 0x5802003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* subl<.f><.cc> RB,RB,RC 01011bbb11000010FBBBcccccc0QQQQQ. */
+{ "subl", 0x58C20000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* subl<.f> RA,RB,u6 01011bbb01000010FBBBuuuuuuaaaaaa. */
+{ "subl", 0x58420000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* subl<.f> 0,RB,u6 01011bbb01000010FBBBuuuuuu111110. */
+{ "subl", 0x5842003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* subl<.f><.cc> RB,RB,u6 01011bbb11000010FBBBuuuuuu1QQQQQ. */
+{ "subl", 0x58C20020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* subl<.f> RB,RB,s12 01011bbb10000010FBBBssssssSSSSSS. */
+{ "subl", 0x58820000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* subl<.f> RA,ximm,RC 0101110000000010F111ccccccaaaaaa. */
+{ "subl", 0x5C027000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* subl<.f> RA,RB,ximm 01011bbb00000010FBBB111100aaaaaa. */
+{ "subl", 0x58020F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* subl<.f> 0,ximm,RC 0101110000000010F111cccccc111110. */
+{ "subl", 0x5C02703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* subl<.f> 0,RB,ximm 01011bbb00000010FBBB111100111110. */
+{ "subl", 0x58020F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* subl<.f><.cc> 0,ximm,RC 0101110011000010F111cccccc0QQQQQ. */
+{ "subl", 0x5CC27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* subl<.f><.cc> RB,RB,ximm 01011bbb11000010FBBB1111000QQQQQ. */
+{ "subl", 0x58C20F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* subl<.f> RA,ximm,u6 0101110001000010F111uuuuuuaaaaaa. */
+{ "subl", 0x5C427000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* subl<.f> 0,ximm,u6 0101110001000010F111uuuuuu111110. */
+{ "subl", 0x5C42703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* subl<.f><.cc> 0,ximm,u6 0101110011000010F111uuuuuu1QQQQQ. */
+{ "subl", 0x5CC27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* subl<.f> RA,limm,RC 0101111000000010F111ccccccaaaaaa. */
+{ "subl", 0x5E027000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* subl<.f> RA,RB,limm 01011bbb00000010FBBB111110aaaaaa. */
+{ "subl", 0x58020F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* subl<.f> 0,limm,RC 0101111000000010F111cccccc111110. */
+{ "subl", 0x5E02703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* subl<.f> 0,RB,limm 01011bbb00000010FBBB111110111110. */
+{ "subl", 0x58020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* subl<.f><.cc> 0,limm,RC 0101111011000010F111cccccc0QQQQQ. */
+{ "subl", 0x5EC27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* subl<.f><.cc> RB,RB,limm 01011bbb11000010FBBB1111100QQQQQ. */
+{ "subl", 0x58C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* subl<.f> RA,limm,u6 0101111001000010F111uuuuuuaaaaaa. */
+{ "subl", 0x5E427000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* subl<.f> 0,limm,u6 0101111001000010F111uuuuuu111110. */
+{ "subl", 0x5E42703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* subl<.f><.cc> 0,limm,u6 0101111011000010F111uuuuuu1QQQQQ. */
+{ "subl", 0x5EC27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* subl<.f> 0,ximm,s12 0101110010000010F111ssssssSSSSSS. */
+{ "subl", 0x5C827000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* subl<.f> 0,limm,s12 0101111010000010F111ssssssSSSSSS. */
+{ "subl", 0x5E827000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* subl<.f> RA,ximm,ximm 0101110000000010F111111100aaaaaa. */
+{ "subl", 0x5C027F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* subl<.f> 0,ximm,ximm 0101110000000010F111111100111110. */
+{ "subl", 0x5C027F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* subl<.f><.cc> 0,ximm,ximm 0101110011000010F1111111000QQQQQ. */
+{ "subl", 0x5CC27F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* subl<.f> RA,limm,limm 0101111000000010F111111110aaaaaa. */
+{ "subl", 0x5E027F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* subl<.f> 0,limm,limm 0101111000000010F111111110111110. */
+{ "subl", 0x5E027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* subl<.f><.cc> 0,limm,limm 0101111011000010F1111111100QQQQQ. */
+{ "subl", 0x5EC27F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* subl_s SP,SP,u9 11000UU1101uuuuu. */
+{ "subl_s", 0x0000C1A0, 0x0000F9E0, ARC_OPCODE_ARC64, ARITH, NONE, { SP_S, SP_Sdup, UIMM9_A32_11_S }, { 0 }},
+
+/* subl_s b,b,c 01111bbbccc00011. */
+{ "subl_s", 0x00007803, 0x0000F81F, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* sub_s.NE b,b,b 01111bbb11000000. */
+{ "sub_s", 0x000078C0, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB_S, RB_Sdup, RB_Sdup }, { C_NE, C_CC_NE }},
+
+/* sub_s b,b,c 01111bbbccc00010. */
+{ "sub_s", 0x00007802, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* sub_s a,b,c 01001bbbccc10aaa. */
+{ "sub_s", 0x00004810, 0x0000F818,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, CD2, { RA_S, RB_S, RC_S }, { 0 }},
+
+/* sub_s b,b,u5 10111bbb011uuuuu. */
+{ "sub_s", 0x0000B860, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* sub_s SP,SP,u7 11000001101uuuuu. */
+{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC32, SUB, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
+
+/* swap<.f> b,c 00101bbb00101111FBBBCCCCCC000000. */
+{ "swap", 0x282F0000, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* swap<.f> 0,c 0010111000101111F111CCCCCC000000. */
+{ "swap", 0x2E2F7000, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* swap<.f> b,u6 00101bbb01101111FBBBuuuuuu000000. */
+{ "swap", 0x286F0000, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* swap<.f> 0,u6 0010111001101111F111uuuuuu000000. */
+{ "swap", 0x2E6F7000, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* swap<.f> b,limm 00101bbb00101111FBBB111110000000. */
+{ "swap", 0x282F0F80, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* swap<.f> 0,limm 0010111000101111F111111110000000. */
+{ "swap", 0x2E2F7F80, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* swape<.f> b,c 00101bbb00101111FBBBCCCCCC001001. */
+{ "swape", 0x282F0009, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* swape<.f> 0,c 0010111000101111F111CCCCCC001001. */
+{ "swape", 0x2E2F7009, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* swape<.f> b,u6 00101bbb01101111FBBBuuuuuu001001. */
+{ "swape", 0x286F0009, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* swape<.f> 0,u6 0010111001101111F111uuuuuu001001. */
+{ "swape", 0x2E6F7009, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* swape<.f> b,limm 00101bbb00101111FBBB111110001001. */
+{ "swape", 0x282F0F89, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* swape<.f> 0,limm 0010111000101111F111111110001001. */
+{ "swape", 0x2E2F7F89, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* swapel<.f> RB,RC 01011bbb00101111FBBBcccccc101001. */
+{ "swapel", 0x582F0029, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* swapel<.f> 0,RC 0101111000101111F111cccccc101001. */
+{ "swapel", 0x5E2F7029, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* swapel<.f> RB,u6 01011bbb01101111FBBBuuuuuu101001. */
+{ "swapel", 0x586F0029, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* swapel<.f> 0,u6 0101111001101111F111uuuuuu101001. */
+{ "swapel", 0x5E6F7029, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* swapel<.f> RB,ximm 01011bbb00101111FBBB111100101001. */
+{ "swapel", 0x582F0F29, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* swapel<.f> 0,ximm 0101111000101111F111111100101001. */
+{ "swapel", 0x5E2F7F29, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* swapel<.f> RB,limm 01011bbb00101111FBBB111110101001. */
+{ "swapel", 0x582F0FA9, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* swapel<.f> 0,limm 0101111000101111F111111110101001. */
+{ "swapel", 0x5E2F7FA9, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* swapl<.f> RB,RC 01011bbb00101111FBBBcccccc100000. */
+{ "swapl", 0x582F0020, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* swapl<.f> 0,RC 0101111000101111F111cccccc100000. */
+{ "swapl", 0x5E2F7020, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* swapl<.f> RB,u6 01011bbb01101111FBBBuuuuuu100000. */
+{ "swapl", 0x586F0020, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* swapl<.f> 0,u6 0101111001101111F111uuuuuu100000. */
+{ "swapl", 0x5E6F7020, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* swapl<.f> RB,ximm 01011bbb00101111FBBB111100100000. */
+{ "swapl", 0x582F0F20, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* swapl<.f> 0,ximm 0101111000101111F111111100100000. */
+{ "swapl", 0x5E2F7F20, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* swapl<.f> RB,limm 01011bbb00101111FBBB111110100000. */
+{ "swapl", 0x582F0FA0, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* swapl<.f> 0,limm 0101111000101111F111111110100000. */
+{ "swapl", 0x5E2F7FA0, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* swi 00100010011011110000000000111111. */
+{ "swi", 0x226F003F, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* swi_s 0111101011100000. */
+{ "swi_s", 0x00007AE0, 0x0000FFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* swi_s u6 01111uuuuuu11111. */
+{ "swi_s", 0x0000781F, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
+
+/* sync 00100011011011110000000000111111. */
+{ "sync", 0x236F003F, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* trap_s u6 01111uuuuuu11110. */
+{ "trap_s", 0x0000781E, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
+
+/* tst b,c 00100bbb000010111BBBCCCCCCRRRRRR. */
+{ "tst", 0x200B8000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { 0 }},
+
+/* tst<.cc> b,c 00100bbb110010111BBBCCCCCC0QQQQQ. */
+{ "tst", 0x20CB8000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_CC }},
+
+/* tst b,u6 00100bbb010010111BBBuuuuuuRRRRRR. */
+{ "tst", 0x204B8000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* tst<.cc> b,u6 00100bbb110010111BBBuuuuuu1QQQQQ. */
+{ "tst", 0x20CB8020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* tst b,s12 00100bbb100010111BBBssssssSSSSSS. */
+{ "tst", 0x208B8000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* tst limm,c 00100110000010111111CCCCCCRRRRRR. */
+{ "tst", 0x260BF000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, RC }, { 0 }},
+
+/* tst b,limm 00100bbb000010111BBB111110RRRRRR. */
+{ "tst", 0x200B8F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { 0 }},
+
+/* tst<.cc> b,limm 00100bbb110010111BBB1111100QQQQQ. */
+{ "tst", 0x20CB8F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_CC }},
+
+/* tst<.cc> limm,c 00100110110010111111CCCCCC0QQQQQ. */
+{ "tst", 0x26CBF000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, RC }, { C_CC }},
+
+/* tst limm,u6 00100110010010111111uuuuuuRRRRRR. */
+{ "tst", 0x264BF000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* tst<.cc> limm,u6 00100110110010111111uuuuuu1QQQQQ. */
+{ "tst", 0x26CBF020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* tst limm,s12 00100110100010111111ssssssSSSSSS. */
+{ "tst", 0x268BF000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* tst limm,limm 00100110000010111111111110RRRRRR. */
+{ "tst", 0x260BFF80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* tst<.cc> limm,limm 001001101100101111111111100QQQQQ. */
+{ "tst", 0x26CBFF80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* tstl RB,RC 01011bbb000010111BBBccccccRRRRRR. */
+{ "tstl", 0x580B8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* tstl<.cc> RB,RC 01011bbb110010111BBBcccccc0QQQQQ. */
+{ "tstl", 0x58CB8000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* tstl RB,u6 01011bbb010010111BBBuuuuuuRRRRRR. */
+{ "tstl", 0x584B8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* tstl<.cc> RB,u6 01011bbb110010111BBBuuuuuu1QQQQQ. */
+{ "tstl", 0x58CB8020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* tstl RB,s12 01011bbb100010111BBBssssssSSSSSS. */
+{ "tstl", 0x588B8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* tstl RB,ximm 01011bbb000010111BBB111100RRRRRR. */
+{ "tstl", 0x580B8F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 }},
+
+/* tstl<.cc> RB,ximm 01011bbb110010111BBB1111000QQQQQ. */
+{ "tstl", 0x58CB8F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC }},
+
+/* tstl RB,limm 01011bbb000010111BBB111110RRRRRR. */
+{ "tstl", 0x580B8F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* tstl<.cc> RB,limm 01011bbb110010111BBB1111100QQQQQ. */
+{ "tstl", 0x58CB8F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* tst_s b,c 01111bbbccc01011. */
+{ "tst_s", 0x0000780B, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* unimp_s 0111100111100000. */
+{ "unimp_s", 0x000079E0, 0x0000FFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* vadd2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA. */
+{ "vadd2", 0x283C0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vadd2 0,b,c 00101bbb001111000BBBCCCCCC111110. */
+{ "vadd2", 0x283C003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vadd2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ. */
+{ "vadd2", 0x28FC0000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vadd2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA. */
+{ "vadd2", 0x287C0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2 0,b,u6 00101bbb011111000BBBuuuuuu111110. */
+{ "vadd2", 0x287C003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ. */
+{ "vadd2", 0x28FC0020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadd2 b,b,s12 00101bbb101111000BBBssssssSSSSSS. */
+{ "vadd2", 0x28BC0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadd2 a,limm,c 00101110001111000111CCCCCCAAAAAA. */
+{ "vadd2", 0x2E3C7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vadd2 a,b,limm 00101bbb001111000BBB111110AAAAAA. */
+{ "vadd2", 0x283C0F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vadd2 0,limm,c 00101110001111000111CCCCCC111110. */
+{ "vadd2", 0x2E3C703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vadd2 0,b,limm 00101bbb001111000BBB111110111110. */
+{ "vadd2", 0x283C0FBE, 0xF8FF8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vadd2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ. */
+{ "vadd2", 0x28FC0F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vadd2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ. */
+{ "vadd2", 0x2EFC7000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadd2 a,limm,u6 00101110011111000111uuuuuuAAAAAA. */
+{ "vadd2", 0x2E7C7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2 0,limm,u6 00101110011111000111uuuuuu111110. */
+{ "vadd2", 0x2E7C703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2<.cc> 0,limm,u6 00101110111111000111uuuuuu1QQQQQ. */
+{ "vadd2", 0x2EFC7020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadd2 0,limm,s12 00101110101111000111ssssssSSSSSS. */
+{ "vadd2", 0x2EBC7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadd2 a,limm,limm 00101110001111000111111110AAAAAA. */
+{ "vadd2", 0x2E3C7F80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2 0,limm,limm 00101110001111000111111110111110. */
+{ "vadd2", 0x2E3C7FBE, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2<.cc> 0,limm,limm 001011101111110001111111100QQQQQ. */
+{ "vadd2", 0x2EFC7F80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadd2h a,b,c 00101bbb000101000BBBCCCCCCAAAAAA. */
+{ "vadd2h", 0x28140000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vadd2h 0,b,c 00101bbb000101000BBBCCCCCC111110. */
+{ "vadd2h", 0x2814003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vadd2h<.cc> b,b,c 00101bbb110101000BBBCCCCCC0QQQQQ. */
+{ "vadd2h", 0x28D40000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vadd2h a,b,u6 00101bbb010101000BBBuuuuuuAAAAAA. */
+{ "vadd2h", 0x28540000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2h 0,b,u6 00101bbb010101000BBBuuuuuu111110. */
+{ "vadd2h", 0x2854003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2h<.cc> b,b,u6 00101bbb110101000BBBuuuuuu1QQQQQ. */
+{ "vadd2h", 0x28D40020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadd2h b,b,s12 00101bbb100101000BBBssssssSSSSSS. */
+{ "vadd2h", 0x28940000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadd2h a,limm,c 00101110000101000111CCCCCCAAAAAA. */
+{ "vadd2h", 0x2E147000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vadd2h a,b,limm 00101bbb000101000BBB111110AAAAAA. */
+{ "vadd2h", 0x28140F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vadd2h 0,limm,c 00101110000101000111CCCCCC111110. */
+{ "vadd2h", 0x2E14703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vadd2h 0,b,limm 00101bbb000101000BBB111110111110. */
+{ "vadd2h", 0x28140FBE, 0xF8FF8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vadd2h<.cc> b,b,limm 00101bbb110101000BBB1111100QQQQQ. */
+{ "vadd2h", 0x28D40F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vadd2h<.cc> 0,limm,c 00101110110101000111CCCCCC0QQQQQ. */
+{ "vadd2h", 0x2ED47000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadd2h a,limm,u6 00101110010101000111uuuuuuAAAAAA. */
+{ "vadd2h", 0x2E547000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2h 0,limm,u6 00101110010101000111uuuuuu111110. */
+{ "vadd2h", 0x2E54703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2h<.cc> 0,limm,u6 00101110110101000111uuuuuu1QQQQQ. */
+{ "vadd2h", 0x2ED47020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadd2h 0,limm,s12 00101110100101000111ssssssSSSSSS. */
+{ "vadd2h", 0x2E947000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadd2h a,limm,limm 00101110000101000111111110AAAAAA. */
+{ "vadd2h", 0x2E147F80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2h 0,limm,limm 00101110000101000111111110111110. */
+{ "vadd2h", 0x2E147FBE, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2h<.cc> 0,limm,limm 001011101101010001111111100QQQQQ. */
+{ "vadd2h", 0x2ED47F80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadd4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA. */
+{ "vadd4h", 0x28380000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vadd4h 0,b,c 00101bbb001110000BBBCCCCCC111110. */
+{ "vadd4h", 0x2838003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vadd4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ. */
+{ "vadd4h", 0x28F80000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vadd4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA. */
+{ "vadd4h", 0x28780000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vadd4h 0,b,u6 00101bbb011110000BBBuuuuuu111110. */
+{ "vadd4h", 0x2878003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ. */
+{ "vadd4h", 0x28F80020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadd4h b,b,s12 00101bbb101110000BBBssssssSSSSSS. */
+{ "vadd4h", 0x28B80000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadd4h a,limm,c 00101110001110000111CCCCCCAAAAAA. */
+{ "vadd4h", 0x2E387000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vadd4h a,b,limm 00101bbb001110000BBB111110AAAAAA. */
+{ "vadd4h", 0x28380F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vadd4h 0,limm,c 00101110001110000111CCCCCC111110. */
+{ "vadd4h", 0x2E38703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vadd4h 0,b,limm 00101bbb001110000BBB111110111110. */
+{ "vadd4h", 0x28380FBE, 0xF8FF8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vadd4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ. */
+{ "vadd4h", 0x28F80F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vadd4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ. */
+{ "vadd4h", 0x2EF87000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadd4h a,limm,u6 00101110011110000111uuuuuuAAAAAA. */
+{ "vadd4h", 0x2E787000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd4h 0,limm,u6 00101110011110000111uuuuuu111110. */
+{ "vadd4h", 0x2E78703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd4h<.cc> 0,limm,u6 00101110111110000111uuuuuu1QQQQQ. */
+{ "vadd4h", 0x2EF87020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadd4h 0,limm,s12 00101110101110000111ssssssSSSSSS. */
+{ "vadd4h", 0x2EB87000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadd4h a,limm,limm 00101110001110000111111110AAAAAA. */
+{ "vadd4h", 0x2E387F80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vadd4h 0,limm,limm 00101110001110000111111110111110. */
+{ "vadd4h", 0x2E387FBE, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd4h<.cc> 0,limm,limm 001011101111100001111111100QQQQQ. */
+{ "vadd4h", 0x2EF87F80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsub a,b,c 00101bbb001111100BBBCCCCCCAAAAAA. */
+{ "vaddsub", 0x283E0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vaddsub 0,b,c 00101bbb001111100BBBCCCCCC111110. */
+{ "vaddsub", 0x283E003E, 0xF8FF803F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vaddsub<.cc> b,b,c 00101bbb111111100BBBCCCCCC0QQQQQ. */
+{ "vaddsub", 0x28FE0000, 0xF8FF8020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vaddsub a,b,u6 00101bbb011111100BBBuuuuuuAAAAAA. */
+{ "vaddsub", 0x287E0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub 0,b,u6 00101bbb011111100BBBuuuuuu111110. */
+{ "vaddsub", 0x287E003E, 0xF8FF803F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub<.cc> b,b,u6 00101bbb111111100BBBuuuuuu1QQQQQ. */
+{ "vaddsub", 0x28FE0020, 0xF8FF8020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsub b,b,s12 00101bbb101111100BBBssssssSSSSSS. */
+{ "vaddsub", 0x28BE0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsub a,limm,c 00101110001111100111CCCCCCAAAAAA. */
+{ "vaddsub", 0x2E3E7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vaddsub a,b,limm 00101bbb001111100BBB111110AAAAAA. */
+{ "vaddsub", 0x283E0F80, 0xF8FF8FC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vaddsub 0,limm,c 00101110001111100111CCCCCC111110. */
+{ "vaddsub", 0x2E3E703E, 0xFFFFF03F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsub 0,b,limm 00101bbb001111100BBB111110111110. */
+{ "vaddsub", 0x283E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsub<.cc> b,b,limm 00101bbb111111100BBB1111100QQQQQ. */
+{ "vaddsub", 0x28FE0F80, 0xF8FF8FE0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vaddsub<.cc> 0,limm,c 00101110111111100111CCCCCC0QQQQQ. */
+{ "vaddsub", 0x2EFE7000, 0xFFFFF020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsub a,limm,u6 00101110011111100111uuuuuuAAAAAA. */
+{ "vaddsub", 0x2E7E7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub 0,limm,u6 00101110011111100111uuuuuu111110. */
+{ "vaddsub", 0x2E7E703E, 0xFFFFF03F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub<.cc> 0,limm,u6 00101110111111100111uuuuuu1QQQQQ. */
+{ "vaddsub", 0x2EFE7020, 0xFFFFF020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsub 0,limm,s12 00101110101111100111ssssssSSSSSS. */
+{ "vaddsub", 0x2EBE7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsub a,limm,limm 00101110001111100111111110AAAAAA. */
+{ "vaddsub", 0x2E3E7F80, 0xFFFFFFC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub 0,limm,limm 00101110001111100111111110111110. */
+{ "vaddsub", 0x2E3E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub<.cc> 0,limm,limm 001011101111111001111111100QQQQQ. */
+{ "vaddsub", 0x2EFE7F80, 0xFFFFFFE0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsub2h a,b,c 00101bbb000101100BBBCCCCCCAAAAAA. */
+{ "vaddsub2h", 0x28160000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vaddsub2h 0,b,c 00101bbb000101100BBBCCCCCC111110. */
+{ "vaddsub2h", 0x2816003E, 0xF8FF803F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vaddsub2h<.cc> b,b,c 00101bbb110101100BBBCCCCCC0QQQQQ. */
+{ "vaddsub2h", 0x28D60000, 0xF8FF8020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vaddsub2h a,b,u6 00101bbb010101100BBBuuuuuuAAAAAA. */
+{ "vaddsub2h", 0x28560000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h 0,b,u6 00101bbb010101100BBBuuuuuu111110. */
+{ "vaddsub2h", 0x2856003E, 0xF8FF803F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h<.cc> b,b,u6 00101bbb110101100BBBuuuuuu1QQQQQ. */
+{ "vaddsub2h", 0x28D60020, 0xF8FF8020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsub2h b,b,s12 00101bbb100101100BBBssssssSSSSSS. */
+{ "vaddsub2h", 0x28960000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsub2h a,limm,c 00101110000101100111CCCCCCAAAAAA. */
+{ "vaddsub2h", 0x2E167000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vaddsub2h a,b,limm 00101bbb000101100BBB111110AAAAAA. */
+{ "vaddsub2h", 0x28160F80, 0xF8FF8FC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vaddsub2h 0,limm,c 00101110000101100111CCCCCC111110. */
+{ "vaddsub2h", 0x2E16703E, 0xFFFFF03F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsub2h 0,b,limm 00101bbb000101100BBB111110111110. */
+{ "vaddsub2h", 0x28160FBE, 0xF8FF8FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsub2h<.cc> b,b,limm 00101bbb110101100BBB1111100QQQQQ. */
+{ "vaddsub2h", 0x28D60F80, 0xF8FF8FE0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vaddsub2h<.cc> 0,limm,c 00101110110101100111CCCCCC0QQQQQ. */
+{ "vaddsub2h", 0x2ED67000, 0xFFFFF020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsub2h a,limm,u6 00101110010101100111uuuuuuAAAAAA. */
+{ "vaddsub2h", 0x2E567000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h 0,limm,u6 00101110010101100111uuuuuu111110. */
+{ "vaddsub2h", 0x2E56703E, 0xFFFFF03F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h<.cc> 0,limm,u6 00101110110101100111uuuuuu1QQQQQ. */
+{ "vaddsub2h", 0x2ED67020, 0xFFFFF020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsub2h 0,limm,s12 00101110100101100111ssssssSSSSSS. */
+{ "vaddsub2h", 0x2E967000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsub2h a,limm,limm 00101110000101100111111110AAAAAA. */
+{ "vaddsub2h", 0x2E167F80, 0xFFFFFFC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub2h 0,limm,limm 00101110000101100111111110111110. */
+{ "vaddsub2h", 0x2E167FBE, 0xFFFFFFFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub2h<.cc> 0,limm,limm 001011101101011001111111100QQQQQ. */
+{ "vaddsub2h", 0x2ED67F80, 0xFFFFFFE0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsub4h a,b,c 00101bbb001110100BBBCCCCCCAAAAAA. */
+{ "vaddsub4h", 0x283A0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vaddsub4h 0,b,c 00101bbb001110100BBBCCCCCC111110. */
+{ "vaddsub4h", 0x283A003E, 0xF8FF803F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vaddsub4h<.cc> b,b,c 00101bbb111110100BBBCCCCCC0QQQQQ. */
+{ "vaddsub4h", 0x28FA0000, 0xF8FF8020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vaddsub4h a,b,u6 00101bbb011110100BBBuuuuuuAAAAAA. */
+{ "vaddsub4h", 0x287A0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h 0,b,u6 00101bbb011110100BBBuuuuuu111110. */
+{ "vaddsub4h", 0x287A003E, 0xF8FF803F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h<.cc> b,b,u6 00101bbb111110100BBBuuuuuu1QQQQQ. */
+{ "vaddsub4h", 0x28FA0020, 0xF8FF8020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsub4h b,b,s12 00101bbb101110100BBBssssssSSSSSS. */
+{ "vaddsub4h", 0x28BA0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsub4h a,limm,c 00101110001110100111CCCCCCAAAAAA. */
+{ "vaddsub4h", 0x2E3A7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vaddsub4h a,b,limm 00101bbb001110100BBB111110AAAAAA. */
+{ "vaddsub4h", 0x283A0F80, 0xF8FF8FC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vaddsub4h 0,limm,c 00101110001110100111CCCCCC111110. */
+{ "vaddsub4h", 0x2E3A703E, 0xFFFFF03F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsub4h 0,b,limm 00101bbb001110100BBB111110111110. */
+{ "vaddsub4h", 0x283A0FBE, 0xF8FF8FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsub4h<.cc> b,b,limm 00101bbb111110100BBB1111100QQQQQ. */
+{ "vaddsub4h", 0x28FA0F80, 0xF8FF8FE0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vaddsub4h<.cc> 0,limm,c 00101110111110100111CCCCCC0QQQQQ. */
+{ "vaddsub4h", 0x2EFA7000, 0xFFFFF020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsub4h a,limm,u6 00101110011110100111uuuuuuAAAAAA. */
+{ "vaddsub4h", 0x2E7A7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h 0,limm,u6 00101110011110100111uuuuuu111110. */
+{ "vaddsub4h", 0x2E7A703E, 0xFFFFF03F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h<.cc> 0,limm,u6 00101110111110100111uuuuuu1QQQQQ. */
+{ "vaddsub4h", 0x2EFA7020, 0xFFFFF020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsub4h 0,limm,s12 00101110101110100111ssssssSSSSSS. */
+{ "vaddsub4h", 0x2EBA7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsub4h a,limm,limm 00101110001110100111111110AAAAAA. */
+{ "vaddsub4h", 0x2E3A7F80, 0xFFFFFFC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub4h 0,limm,limm 00101110001110100111111110111110. */
+{ "vaddsub4h", 0x2E3A7FBE, 0xFFFFFFFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub4h<.cc> 0,limm,limm 001011101111101001111111100QQQQQ. */
+{ "vaddsub4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2h a,b,c 00101bbb000111100BBBCCCCCCAAAAAA. */
+{ "vmac2h", 0x281E0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmac2h 0,b,c 00101bbb000111100BBBCCCCCC111110. */
+{ "vmac2h", 0x281E003E, 0xF8FF803F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2h<.cc> b,b,c 00101bbb110111100BBBCCCCCC0QQQQQ. */
+{ "vmac2h", 0x28DE0000, 0xF8FF8020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmac2h a,b,u6 00101bbb010111100BBBuuuuuuAAAAAA. */
+{ "vmac2h", 0x285E0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2h 0,b,u6 00101bbb010111100BBBuuuuuu111110. */
+{ "vmac2h", 0x285E003E, 0xF8FF803F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2h<.cc> b,b,u6 00101bbb110111100BBBuuuuuu1QQQQQ. */
+{ "vmac2h", 0x28DE0020, 0xF8FF8020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2h b,b,s12 00101bbb100111100BBBssssssSSSSSS. */
+{ "vmac2h", 0x289E0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2h a,limm,c 00101110000111100111CCCCCCAAAAAA. */
+{ "vmac2h", 0x2E1E7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmac2h a,b,limm 00101bbb000111100BBB111110AAAAAA. */
+{ "vmac2h", 0x281E0F80, 0xF8FF8FC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmac2h 0,limm,c 00101110000111100111CCCCCC111110. */
+{ "vmac2h", 0x2E1E703E, 0xFFFFF03F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2h 0,b,limm 00101bbb000111100BBB111110111110. */
+{ "vmac2h", 0x281E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2h<.cc> b,b,limm 00101bbb110111100BBB1111100QQQQQ. */
+{ "vmac2h", 0x28DE0F80, 0xF8FF8FE0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmac2h<.cc> 0,limm,c 00101110110111100111CCCCCC0QQQQQ. */
+{ "vmac2h", 0x2EDE7000, 0xFFFFF020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2h a,limm,u6 00101110010111100111uuuuuuAAAAAA. */
+{ "vmac2h", 0x2E5E7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2h 0,limm,u6 00101110010111100111uuuuuu111110. */
+{ "vmac2h", 0x2E5E703E, 0xFFFFF03F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2h<.cc> 0,limm,u6 00101110110111100111uuuuuu1QQQQQ. */
+{ "vmac2h", 0x2EDE7020, 0xFFFFF020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2h 0,limm,s12 00101110100111100111ssssssSSSSSS. */
+{ "vmac2h", 0x2E9E7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2h a,limm,limm 00101110000111100111111110AAAAAA. */
+{ "vmac2h", 0x2E1E7F80, 0xFFFFFFC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2h 0,limm,limm 00101110000111100111111110111110. */
+{ "vmac2h", 0x2E1E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2h<.cc> 0,limm,limm 001011101101111001111111100QQQQQ. */
+{ "vmac2h", 0x2EDE7F80, 0xFFFFFFE0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2hu a,b,c 00101bbb000111110BBBCCCCCCAAAAAA. */
+{ "vmac2hu", 0x281F0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmac2hu 0,b,c 00101bbb000111110BBBCCCCCC111110. */
+{ "vmac2hu", 0x281F003E, 0xF8FF803F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2hu<.cc> b,b,c 00101bbb110111110BBBCCCCCC0QQQQQ. */
+{ "vmac2hu", 0x28DF0000, 0xF8FF8020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmac2hu a,b,u6 00101bbb010111110BBBuuuuuuAAAAAA. */
+{ "vmac2hu", 0x285F0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hu 0,b,u6 00101bbb010111110BBBuuuuuu111110. */
+{ "vmac2hu", 0x285F003E, 0xF8FF803F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hu<.cc> b,b,u6 00101bbb110111110BBBuuuuuu1QQQQQ. */
+{ "vmac2hu", 0x28DF0020, 0xF8FF8020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2hu b,b,s12 00101bbb100111110BBBssssssSSSSSS. */
+{ "vmac2hu", 0x289F0000, 0xF8FF8000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2hu a,limm,c 00101110000111110111CCCCCCAAAAAA. */
+{ "vmac2hu", 0x2E1F7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmac2hu a,b,limm 00101bbb000111110BBB111110AAAAAA. */
+{ "vmac2hu", 0x281F0F80, 0xF8FF8FC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmac2hu 0,limm,c 00101110000111110111CCCCCC111110. */
+{ "vmac2hu", 0x2E1F703E, 0xFFFFF03F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2hu 0,b,limm 00101bbb000111110BBB111110111110. */
+{ "vmac2hu", 0x281F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2hu<.cc> b,b,limm 00101bbb110111110BBB1111100QQQQQ. */
+{ "vmac2hu", 0x28DF0F80, 0xF8FF8FE0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmac2hu<.cc> 0,limm,c 00101110110111110111CCCCCC0QQQQQ. */
+{ "vmac2hu", 0x2EDF7000, 0xFFFFF020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2hu a,limm,u6 00101110010111110111uuuuuuAAAAAA. */
+{ "vmac2hu", 0x2E5F7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hu 0,limm,u6 00101110010111110111uuuuuu111110. */
+{ "vmac2hu", 0x2E5F703E, 0xFFFFF03F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hu<.cc> 0,limm,u6 00101110110111110111uuuuuu1QQQQQ. */
+{ "vmac2hu", 0x2EDF7020, 0xFFFFF020, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2hu 0,limm,s12 00101110100111110111ssssssSSSSSS. */
+{ "vmac2hu", 0x2E9F7000, 0xFFFFF000, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2hu a,limm,limm 00101110000111110111111110AAAAAA. */
+{ "vmac2hu", 0x2E1F7F80, 0xFFFFFFC0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hu 0,limm,limm 00101110000111110111111110111110. */
+{ "vmac2hu", 0x2E1F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hu<.cc> 0,limm,limm 001011101101111101111111100QQQQQ. */
+{ "vmac2hu", 0x2EDF7F80, 0xFFFFFFE0, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA. */
+{ "vmpy2h", 0x281C0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110. */
+{ "vmpy2h", 0x281C003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ. */
+{ "vmpy2h", 0x28DC0000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA. */
+{ "vmpy2h", 0x285C0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110. */
+{ "vmpy2h", 0x285C003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ. */
+{ "vmpy2h", 0x28DC0020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */
+
+/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */
+{ "vmpy2h", 0x289C0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA. */
+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA. */
+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110. */
+{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110. */
+{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ. */
+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ. */
+{ "vmpy2h", 0x2EDC7000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA. */
+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110. */
+{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ. */
+{ "vmpy2h", 0x2EDC7020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS. */
+{ "vmpy2h", 0x2E9C7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA. */
+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2h 0,limm,limm 00101110000111000111111110111110. */
+{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ. */
+{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA. */
+{ "vmpy2hu", 0x281D0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110. */
+{ "vmpy2hu", 0x281D003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ. */
+{ "vmpy2hu", 0x28DD0000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA. */
+{ "vmpy2hu", 0x285D0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110. */
+{ "vmpy2hu", 0x285D003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ. */
+{ "vmpy2hu", 0x28DD0020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS. */
+{ "vmpy2hu", 0x289D0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA. */
+{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA. */
+{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110. */
+{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110. */
+{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ. */
+{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ. */
+{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA. */
+{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110. */
+{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ. */
+{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS. */
+{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA. */
+{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hu 0,limm,limm 00101110000111010111111110111110. */
+{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ. */
+{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsub2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA. */
+{ "vsub2", 0x283D0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsub2 0,b,c 00101bbb001111010BBBCCCCCC111110. */
+{ "vsub2", 0x283D003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsub2<.cc> b,b,c 00101bbb111111010BBBCCCCCC0QQQQQ. */
+{ "vsub2", 0x28FD0000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsub2 a,b,u6 00101bbb011111010BBBuuuuuuAAAAAA. */
+{ "vsub2", 0x287D0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2 0,b,u6 00101bbb011111010BBBuuuuuu111110. */
+{ "vsub2", 0x287D003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2<.cc> b,b,u6 00101bbb111111010BBBuuuuuu1QQQQQ. */
+{ "vsub2", 0x28FD0020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsub2 b,b,s12 00101bbb101111010BBBssssssSSSSSS. */
+{ "vsub2", 0x28BD0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsub2 a,limm,c 00101110001111010111CCCCCCAAAAAA. */
+{ "vsub2", 0x2E3D7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsub2 a,b,limm 00101bbb001111010BBB111110AAAAAA. */
+{ "vsub2", 0x283D0F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsub2 0,limm,c 00101110001111010111CCCCCC111110. */
+{ "vsub2", 0x2E3D703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsub2 0,b,limm 00101bbb001111010BBB111110111110. */
+{ "vsub2", 0x283D0FBE, 0xF8FF8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsub2<.cc> b,b,limm 00101bbb111111010BBB1111100QQQQQ. */
+{ "vsub2", 0x28FD0F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsub2<.cc> 0,limm,c 00101110111111010111CCCCCC0QQQQQ. */
+{ "vsub2", 0x2EFD7000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsub2 a,limm,u6 00101110011111010111uuuuuuAAAAAA. */
+{ "vsub2", 0x2E7D7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2 0,limm,u6 00101110011111010111uuuuuu111110. */
+{ "vsub2", 0x2E7D703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2<.cc> 0,limm,u6 00101110111111010111uuuuuu1QQQQQ. */
+{ "vsub2", 0x2EFD7020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsub2 0,limm,s12 00101110101111010111ssssssSSSSSS. */
+{ "vsub2", 0x2EBD7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsub2 a,limm,limm 00101110001111010111111110AAAAAA. */
+{ "vsub2", 0x2E3D7F80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2 0,limm,limm 00101110001111010111111110111110. */
+{ "vsub2", 0x2E3D7FBE, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2<.cc> 0,limm,limm 001011101111110101111111100QQQQQ. */
+{ "vsub2", 0x2EFD7F80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsub2h a,b,c 00101bbb000101010BBBCCCCCCAAAAAA. */
+{ "vsub2h", 0x28150000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsub2h 0,b,c 00101bbb000101010BBBCCCCCC111110. */
+{ "vsub2h", 0x2815003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vsub2h<.cc> b,b,c 00101bbb110101010BBBCCCCCC0QQQQQ. */
+{ "vsub2h", 0x28D50000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsub2h a,b,u6 00101bbb010101010BBBuuuuuuAAAAAA. */
+{ "vsub2h", 0x28550000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2h 0,b,u6 00101bbb010101010BBBuuuuuu111110. */
+{ "vsub2h", 0x2855003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2h<.cc> b,b,u6 00101bbb110101010BBBuuuuuu1QQQQQ. */
+{ "vsub2h", 0x28D50020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsub2h b,b,s12 00101bbb100101010BBBssssssSSSSSS. */
+{ "vsub2h", 0x28950000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsub2h a,limm,c 00101110000101010111CCCCCCAAAAAA. */
+{ "vsub2h", 0x2E157000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsub2h a,b,limm 00101bbb000101010BBB111110AAAAAA. */
+{ "vsub2h", 0x28150F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsub2h 0,limm,c 00101110000101010111CCCCCC111110. */
+{ "vsub2h", 0x2E15703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsub2h 0,b,limm 00101bbb000101010BBB111110111110. */
+{ "vsub2h", 0x28150FBE, 0xF8FF8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsub2h<.cc> b,b,limm 00101bbb110101010BBB1111100QQQQQ. */
+{ "vsub2h", 0x28D50F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsub2h<.cc> 0,limm,c 00101110110101010111CCCCCC0QQQQQ. */
+{ "vsub2h", 0x2ED57000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsub2h a,limm,u6 00101110010101010111uuuuuuAAAAAA. */
+{ "vsub2h", 0x2E557000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2h 0,limm,u6 00101110010101010111uuuuuu111110. */
+{ "vsub2h", 0x2E55703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2h<.cc> 0,limm,u6 00101110110101010111uuuuuu1QQQQQ. */
+{ "vsub2h", 0x2ED57020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsub2h 0,limm,s12 00101110100101010111ssssssSSSSSS. */
+{ "vsub2h", 0x2E957000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsub2h a,limm,limm 00101110000101010111111110AAAAAA. */
+{ "vsub2h", 0x2E157F80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2h 0,limm,limm 00101110000101010111111110111110. */
+{ "vsub2h", 0x2E157FBE, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2h<.cc> 0,limm,limm 001011101101010101111111100QQQQQ. */
+{ "vsub2h", 0x2ED57F80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsub4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA. */
+{ "vsub4h", 0x28390000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsub4h 0,b,c 00101bbb001110010BBBCCCCCC111110. */
+{ "vsub4h", 0x2839003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsub4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ. */
+{ "vsub4h", 0x28F90000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsub4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA. */
+{ "vsub4h", 0x28790000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsub4h 0,b,u6 00101bbb011110010BBBuuuuuu111110. */
+{ "vsub4h", 0x2879003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ. */
+{ "vsub4h", 0x28F90020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsub4h b,b,s12 00101bbb101110010BBBssssssSSSSSS. */
+{ "vsub4h", 0x28B90000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsub4h a,limm,c 00101110001110010111CCCCCCAAAAAA. */
+{ "vsub4h", 0x2E397000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsub4h a,b,limm 00101bbb001110010BBB111110AAAAAA. */
+{ "vsub4h", 0x28390F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsub4h 0,limm,c 00101110001110010111CCCCCC111110. */
+{ "vsub4h", 0x2E39703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsub4h 0,b,limm 00101bbb001110010BBB111110111110. */
+{ "vsub4h", 0x28390FBE, 0xF8FF8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsub4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ. */
+{ "vsub4h", 0x28F90F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsub4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ. */
+{ "vsub4h", 0x2EF97000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsub4h a,limm,u6 00101110011110010111uuuuuuAAAAAA. */
+{ "vsub4h", 0x2E797000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub4h 0,limm,u6 00101110011110010111uuuuuu111110. */
+{ "vsub4h", 0x2E79703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub4h<.cc> 0,limm,u6 00101110111110010111uuuuuu1QQQQQ. */
+{ "vsub4h", 0x2EF97020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsub4h 0,limm,s12 00101110101110010111ssssssSSSSSS. */
+{ "vsub4h", 0x2EB97000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsub4h a,limm,limm 00101110001110010111111110AAAAAA. */
+{ "vsub4h", 0x2E397F80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsub4h 0,limm,limm 00101110001110010111111110111110. */
+{ "vsub4h", 0x2E397FBE, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub4h<.cc> 0,limm,limm 001011101111100101111111100QQQQQ. */
+{ "vsub4h", 0x2EF97F80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadd a,b,c 00101bbb001111110BBBCCCCCCAAAAAA. */
+{ "vsubadd", 0x283F0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubadd 0,b,c 00101bbb001111110BBBCCCCCC111110. */
+{ "vsubadd", 0x283F003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsubadd<.cc> b,b,c 00101bbb111111110BBBCCCCCC0QQQQQ. */
+{ "vsubadd", 0x28FF0000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubadd a,b,u6 00101bbb011111110BBBuuuuuuAAAAAA. */
+{ "vsubadd", 0x287F0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd 0,b,u6 00101bbb011111110BBBuuuuuu111110. */
+{ "vsubadd", 0x287F003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd<.cc> b,b,u6 00101bbb111111110BBBuuuuuu1QQQQQ. */
+{ "vsubadd", 0x28FF0020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadd b,b,s12 00101bbb101111110BBBssssssSSSSSS. */
+{ "vsubadd", 0x28BF0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadd a,limm,c 00101110001111110111CCCCCCAAAAAA. */
+{ "vsubadd", 0x2E3F7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubadd a,b,limm 00101bbb001111110BBB111110AAAAAA. */
+{ "vsubadd", 0x283F0F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubadd 0,limm,c 00101110001111110111CCCCCC111110. */
+{ "vsubadd", 0x2E3F703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadd 0,b,limm 00101bbb001111110BBB111110111110. */
+{ "vsubadd", 0x283F0FBE, 0xF8FF8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadd<.cc> b,b,limm 00101bbb111111110BBB1111100QQQQQ. */
+{ "vsubadd", 0x28FF0F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubadd<.cc> 0,limm,c 00101110111111110111CCCCCC0QQQQQ. */
+{ "vsubadd", 0x2EFF7000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadd a,limm,u6 00101110011111110111uuuuuuAAAAAA. */
+{ "vsubadd", 0x2E7F7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd 0,limm,u6 00101110011111110111uuuuuu111110. */
+{ "vsubadd", 0x2E7F703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd<.cc> 0,limm,u6 00101110111111110111uuuuuu1QQQQQ. */
+{ "vsubadd", 0x2EFF7020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadd 0,limm,s12 00101110101111110111ssssssSSSSSS. */
+{ "vsubadd", 0x2EBF7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadd a,limm,limm 00101110001111110111111110AAAAAA. */
+{ "vsubadd", 0x2E3F7F80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd 0,limm,limm 00101110001111110111111110111110. */
+{ "vsubadd", 0x2E3F7FBE, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd<.cc> 0,limm,limm 001011101111111101111111100QQQQQ. */
+{ "vsubadd", 0x2EFF7F80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadd2h a,b,c 00101bbb000101110BBBCCCCCCAAAAAA. */
+{ "vsubadd2h", 0x28170000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubadd2h 0,b,c 00101bbb000101110BBBCCCCCC111110. */
+{ "vsubadd2h", 0x2817003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vsubadd2h<.cc> b,b,c 00101bbb110101110BBBCCCCCC0QQQQQ. */
+{ "vsubadd2h", 0x28D70000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubadd2h a,b,u6 00101bbb010101110BBBuuuuuuAAAAAA. */
+{ "vsubadd2h", 0x28570000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h 0,b,u6 00101bbb010101110BBBuuuuuu111110. */
+{ "vsubadd2h", 0x2857003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h<.cc> b,b,u6 00101bbb110101110BBBuuuuuu1QQQQQ. */
+{ "vsubadd2h", 0x28D70020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadd2h b,b,s12 00101bbb100101110BBBssssssSSSSSS. */
+{ "vsubadd2h", 0x28970000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadd2h a,limm,c 00101110000101110111CCCCCCAAAAAA. */
+{ "vsubadd2h", 0x2E177000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubadd2h a,b,limm 00101bbb000101110BBB111110AAAAAA. */
+{ "vsubadd2h", 0x28170F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubadd2h 0,limm,c 00101110000101110111CCCCCC111110. */
+{ "vsubadd2h", 0x2E17703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadd2h 0,b,limm 00101bbb000101110BBB111110111110. */
+{ "vsubadd2h", 0x28170FBE, 0xF8FF8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadd2h<.cc> b,b,limm 00101bbb110101110BBB1111100QQQQQ. */
+{ "vsubadd2h", 0x28D70F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubadd2h<.cc> 0,limm,c 00101110110101110111CCCCCC0QQQQQ. */
+{ "vsubadd2h", 0x2ED77000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadd2h a,limm,u6 00101110010101110111uuuuuuAAAAAA. */
+{ "vsubadd2h", 0x2E577000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h 0,limm,u6 00101110010101110111uuuuuu111110. */
+{ "vsubadd2h", 0x2E57703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h<.cc> 0,limm,u6 00101110110101110111uuuuuu1QQQQQ. */
+{ "vsubadd2h", 0x2ED77020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadd2h 0,limm,s12 00101110100101110111ssssssSSSSSS. */
+{ "vsubadd2h", 0x2E977000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadd2h a,limm,limm 00101110000101110111111110AAAAAA. */
+{ "vsubadd2h", 0x2E177F80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd2h 0,limm,limm 00101110000101110111111110111110. */
+{ "vsubadd2h", 0x2E177FBE, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd2h<.cc> 0,limm,limm 001011101101011101111111100QQQQQ. */
+{ "vsubadd2h", 0x2ED77F80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadd4h a,b,c 00101bbb001110110BBBCCCCCCAAAAAA. */
+{ "vsubadd4h", 0x283B0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubadd4h 0,b,c 00101bbb001110110BBBCCCCCC111110. */
+{ "vsubadd4h", 0x283B003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsubadd4h<.cc> b,b,c 00101bbb111110110BBBCCCCCC0QQQQQ. */
+{ "vsubadd4h", 0x28FB0000, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubadd4h a,b,u6 00101bbb011110110BBBuuuuuuAAAAAA. */
+{ "vsubadd4h", 0x287B0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h 0,b,u6 00101bbb011110110BBBuuuuuu111110. */
+{ "vsubadd4h", 0x287B003E, 0xF8FF803F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h<.cc> b,b,u6 00101bbb111110110BBBuuuuuu1QQQQQ. */
+{ "vsubadd4h", 0x28FB0020, 0xF8FF8020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadd4h b,b,s12 00101bbb101110110BBBssssssSSSSSS. */
+{ "vsubadd4h", 0x28BB0000, 0xF8FF8000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadd4h a,limm,c 00101110001110110111CCCCCCAAAAAA. */
+{ "vsubadd4h", 0x2E3B7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubadd4h a,b,limm 00101bbb001110110BBB111110AAAAAA. */
+{ "vsubadd4h", 0x283B0F80, 0xF8FF8FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubadd4h 0,limm,c 00101110001110110111CCCCCC111110. */
+{ "vsubadd4h", 0x2E3B703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadd4h 0,b,limm 00101bbb001110110BBB111110111110. */
+{ "vsubadd4h", 0x283B0FBE, 0xF8FF8FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadd4h<.cc> b,b,limm 00101bbb111110110BBB1111100QQQQQ. */
+{ "vsubadd4h", 0x28FB0F80, 0xF8FF8FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubadd4h<.cc> 0,limm,c 00101110111110110111CCCCCC0QQQQQ. */
+{ "vsubadd4h", 0x2EFB7000, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadd4h a,limm,u6 00101110011110110111uuuuuuAAAAAA. */
+{ "vsubadd4h", 0x2E7B7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h 0,limm,u6 00101110011110110111uuuuuu111110. */
+{ "vsubadd4h", 0x2E7B703E, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h<.cc> 0,limm,u6 00101110111110110111uuuuuu1QQQQQ. */
+{ "vsubadd4h", 0x2EFB7020, 0xFFFFF020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadd4h 0,limm,s12 00101110101110110111ssssssSSSSSS. */
+{ "vsubadd4h", 0x2EBB7000, 0xFFFFF000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadd4h a,limm,limm 00101110001110110111111110AAAAAA. */
+{ "vsubadd4h", 0x2E3B7F80, 0xFFFFFFC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd4h 0,limm,limm 00101110001110110111111110111110. */
+{ "vsubadd4h", 0x2E3B7FBE, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd4h<.cc> 0,limm,limm 001011101111101101111111100QQQQQ. */
+{ "vsubadd4h", 0x2EFB7F80, 0xFFFFFFE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* wevt c 00100000001011110001CCCCCC111111. */
+{ "wevt", 0x202F103F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { RC }, { 0 }},
+
+/* wevt 00100000011011110001000000111111. */
+{ "wevt", 0x206F103F, 0xFFFFFFFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* wevt u6 00100000011011110001uuuuuu111111. */
+{ "wevt", 0x206F103F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { UIMM6_20 }, { 0 }},
+
+/* wlfc c 00100001001011110001CCCCCC111111. */
+{ "wlfc", 0x212F103F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { RC }, { 0 }},
+
+/* wlfc u6 00100001011011110001uuuuuu111111. */
+{ "wlfc", 0x216F103F, 0xFFFFF03F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, KERNEL, NONE, { UIMM6_20 }, { 0 }},
+
+/* xbfu<.f> a,b,c 00100bbb00101101FBBBCCCCCCAAAAAA. */
+{ "xbfu", 0x202D0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* xbfu<.f> 0,b,c 00100bbb00101101FBBBCCCCCC111110. */
+{ "xbfu", 0x202D003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* xbfu<.f><.cc> b,b,c 00100bbb11101101FBBBCCCCCC0QQQQQ. */
+{ "xbfu", 0x20ED0000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* xbfu<.f> a,b,u6 00100bbb01101101FBBBuuuuuuAAAAAA. */
+{ "xbfu", 0x206D0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f> 0,b,u6 00100bbb01101101FBBBuuuuuu111110. */
+{ "xbfu", 0x206D003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f><.cc> b,b,u6 00100bbb11101101FBBBuuuuuu1QQQQQ. */
+{ "xbfu", 0x20ED0020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbfu<.f> b,b,s12 00100bbb10101101FBBBssssssSSSSSS. */
+{ "xbfu", 0x20AD0000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* xbfu<.f> a,limm,c 0010011000101101F111CCCCCCAAAAAA. */
+{ "xbfu", 0x262D7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* xbfu<.f> a,b,limm 00100bbb00101101FBBB111110AAAAAA. */
+{ "xbfu", 0x202D0F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* xbfu<.f> 0,limm,c 0010011000101101F111CCCCCC111110. */
+{ "xbfu", 0x262D703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* xbfu<.f> 0,b,limm 00100bbb00101101FBBB111110111110. */
+{ "xbfu", 0x202D0FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* xbfu<.f><.cc> b,b,limm 00100bbb11101101FBBB1111100QQQQQ. */
+{ "xbfu", 0x20ED0F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* xbfu<.f><.cc> 0,limm,c 0010011011101101F111CCCCCC0QQQQQ. */
+{ "xbfu", 0x26ED7000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* xbfu<.f> a,limm,u6 0010011001101101F111uuuuuuAAAAAA. */
+{ "xbfu", 0x266D7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f> 0,limm,u6 0010011001101101F111uuuuuu111110. */
+{ "xbfu", 0x266D703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f><.cc> 0,limm,u6 0010011011101101F111uuuuuu1QQQQQ. */
+{ "xbfu", 0x26ED7020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbfu<.f> 0,limm,s12 0010011010101101F111ssssssSSSSSS. */
+{ "xbfu", 0x26AD7000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* xbfu<.f> a,limm,limm 0010011000101101F111111110AAAAAA. */
+{ "xbfu", 0x262D7F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* xbfu<.f> 0,limm,limm 0010011000101101F111111110111110. */
+{ "xbfu", 0x262D7FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* xbfu<.f><.cc> 0,limm,limm 0010011011101101F1111111100QQQQQ. */
+{ "xbfu", 0x26ED7F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* xbful<.f> RA,RB,RC 01011bbb00101101FBBBccccccaaaaaa. */
+{ "xbful", 0x582D0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* xbful<.f> 0,RB,RC 01011bbb00101101FBBBcccccc111110. */
+{ "xbful", 0x582D003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* xbful<.f><.cc> RB,RB,RC 01011bbb11101101FBBBcccccc0QQQQQ. */
+{ "xbful", 0x58ED0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* xbful<.f> RA,RB,u6 01011bbb01101101FBBBuuuuuuaaaaaa. */
+{ "xbful", 0x586D0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* xbful<.f> 0,RB,u6 01011bbb01101101FBBBuuuuuu111110. */
+{ "xbful", 0x586D003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* xbful<.f><.cc> RB,RB,u6 01011bbb11101101FBBBuuuuuu1QQQQQ. */
+{ "xbful", 0x58ED0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbful<.f> RB,RB,s12 01011bbb10101101FBBBssssssSSSSSS. */
+{ "xbful", 0x58AD0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* xbful<.f> RA,ximm,RC 0101110000101101F111ccccccaaaaaa. */
+{ "xbful", 0x5C2D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* xbful<.f> RA,RB,ximm 01011bbb00101101FBBB111100aaaaaa. */
+{ "xbful", 0x582D0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* xbful<.f> 0,ximm,RC 0101110000101101F111cccccc111110. */
+{ "xbful", 0x5C2D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* xbful<.f> 0,RB,ximm 01011bbb00101101FBBB111100111110. */
+{ "xbful", 0x582D0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* xbful<.f><.cc> 0,ximm,RC 0101110011101101F111cccccc0QQQQQ. */
+{ "xbful", 0x5CED7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* xbful<.f><.cc> RB,RB,ximm 01011bbb11101101FBBB1111000QQQQQ. */
+{ "xbful", 0x58ED0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* xbful<.f> RA,ximm,u6 0101110001101101F111uuuuuuaaaaaa. */
+{ "xbful", 0x5C6D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* xbful<.f> 0,ximm,u6 0101110001101101F111uuuuuu111110. */
+{ "xbful", 0x5C6D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* xbful<.f><.cc> 0,ximm,u6 0101110011101101F111uuuuuu1QQQQQ. */
+{ "xbful", 0x5CED7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbful<.f> RA,limm,RC 0101111000101101F111ccccccaaaaaa. */
+{ "xbful", 0x5E2D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* xbful<.f> RA,RB,limm 01011bbb00101101FBBB111110aaaaaa. */
+{ "xbful", 0x582D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* xbful<.f> 0,limm,RC 0101111000101101F111cccccc111110. */
+{ "xbful", 0x5E2D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* xbful<.f> 0,RB,limm 01011bbb00101101FBBB111110111110. */
+{ "xbful", 0x582D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* xbful<.f><.cc> 0,limm,RC 0101111011101101F111cccccc0QQQQQ. */
+{ "xbful", 0x5EED7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* xbful<.f><.cc> RB,RB,limm 01011bbb11101101FBBB1111100QQQQQ. */
+{ "xbful", 0x58ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* xbful<.f> RA,limm,u6 0101111001101101F111uuuuuuaaaaaa. */
+{ "xbful", 0x5E6D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xbful<.f> 0,limm,u6 0101111001101101F111uuuuuu111110. */
+{ "xbful", 0x5E6D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xbful<.f><.cc> 0,limm,u6 0101111011101101F111uuuuuu1QQQQQ. */
+{ "xbful", 0x5EED7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbful<.f> 0,ximm,s12 0101110010101101F111ssssssSSSSSS. */
+{ "xbful", 0x5CAD7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* xbful<.f> 0,limm,s12 0101111010101101F111ssssssSSSSSS. */
+{ "xbful", 0x5EAD7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* xbful<.f> RA,ximm,ximm 0101110000101101F111111100aaaaaa. */
+{ "xbful", 0x5C2D7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* xbful<.f> 0,ximm,ximm 0101110000101101F111111100111110. */
+{ "xbful", 0x5C2D7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* xbful<.f><.cc> 0,ximm,ximm 0101110011101101F1111111000QQQQQ. */
+{ "xbful", 0x5CED7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* xbful<.f> RA,limm,limm 0101111000101101F111111110aaaaaa. */
+{ "xbful", 0x5E2D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* xbful<.f> 0,limm,limm 0101111000101101F111111110111110. */
+{ "xbful", 0x5E2D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* xbful<.f><.cc> 0,limm,limm 0101111011101101F1111111100QQQQQ. */
+{ "xbful", 0x5EED7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* xor<.f> a,b,c 00100bbb00000111FBBBCCCCCCAAAAAA. */
+{ "xor", 0x20070000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* xor<.f> 0,b,c 00100bbb00000111FBBBCCCCCC111110. */
+{ "xor", 0x2007003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* xor<.f><.cc> b,b,c 00100bbb11000111FBBBCCCCCC0QQQQQ. */
+{ "xor", 0x20C70000, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* xor<.f> a,b,u6 00100bbb01000111FBBBuuuuuuAAAAAA. */
+{ "xor", 0x20470000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* xor<.f> 0,b,u6 00100bbb01000111FBBBuuuuuu111110. */
+{ "xor", 0x2047003E, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* xor<.f><.cc> b,b,u6 00100bbb11000111FBBBuuuuuu1QQQQQ. */
+{ "xor", 0x20C70020, 0xF8FF0020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* xor<.f> b,b,s12 00100bbb10000111FBBBssssssSSSSSS. */
+{ "xor", 0x20870000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* xor<.f> a,limm,c 0010011000000111F111CCCCCCAAAAAA. */
+{ "xor", 0x26077000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* xor<.f> a,b,limm 00100bbb00000111FBBB111110AAAAAA. */
+{ "xor", 0x20070F80, 0xF8FF0FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* xor<.f> 0,limm,c 0010011000000111F111CCCCCC111110. */
+{ "xor", 0x2607703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* xor<.f> 0,b,limm 00100bbb00000111FBBB111110111110. */
+{ "xor", 0x20070FBE, 0xF8FF0FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* xor<.f><.cc> 0,limm,c 0010011011000111F111CCCCCC0QQQQQ. */
+{ "xor", 0x26C77000, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* xor<.f><.cc> b,b,limm 00100bbb11000111FBBB1111100QQQQQ. */
+{ "xor", 0x20C70F80, 0xF8FF0FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* xor<.f> a,limm,u6 0010011001000111F111uuuuuuAAAAAA. */
+{ "xor", 0x26477000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xor<.f> 0,limm,u6 0010011001000111F111uuuuuu111110. */
+{ "xor", 0x2647703E, 0xFFFF703F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xor<.f><.cc> 0,limm,u6 0010011011000111F111uuuuuu1QQQQQ. */
+{ "xor", 0x26C77020, 0xFFFF7020,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xor<.f> 0,limm,s12 0010011010000111F111ssssssSSSSSS. */
+{ "xor", 0x26877000, 0xFFFF7000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* xor<.f> a,limm,limm 0010011000000111F111111110AAAAAA. */
+{ "xor", 0x26077F80, 0xFFFF7FC0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* xor<.f> 0,limm,limm 0010011000000111F111111110111110. */
+{ "xor", 0x26077FBE, 0xFFFF7FFF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* xor<.f><.cc> 0,limm,limm 0010011011000111F1111111100QQQQQ. */
+{ "xor", 0x26C77F80, 0xFFFF7FE0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* xorl<.f> RA,RB,RC 01011bbb00000111FBBBccccccaaaaaa. */
+{ "xorl", 0x58070000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* xorl<.f> 0,RB,RC 01011bbb00000111FBBBcccccc111110. */
+{ "xorl", 0x5807003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* xorl<.f><.cc> RB,RB,RC 01011bbb11000111FBBBcccccc0QQQQQ. */
+{ "xorl", 0x58C70000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* xorl<.f> RA,RB,u6 01011bbb01000111FBBBuuuuuuaaaaaa. */
+{ "xorl", 0x58470000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* xorl<.f> 0,RB,u6 01011bbb01000111FBBBuuuuuu111110. */
+{ "xorl", 0x5847003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* xorl<.f><.cc> RB,RB,u6 01011bbb11000111FBBBuuuuuu1QQQQQ. */
+{ "xorl", 0x58C70020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* xorl<.f> RB,RB,s12 01011bbb10000111FBBBssssssSSSSSS. */
+{ "xorl", 0x58870000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* xorl<.f> RA,ximm,RC 0101110000000111F111ccccccaaaaaa. */
+{ "xorl", 0x5C077000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* xorl<.f> RA,RB,ximm 01011bbb00000111FBBB111100aaaaaa. */
+{ "xorl", 0x58070F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* xorl<.f> 0,ximm,RC 0101110000000111F111cccccc111110. */
+{ "xorl", 0x5C07703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* xorl<.f> 0,RB,ximm 01011bbb00000111FBBB111100111110. */
+{ "xorl", 0x58070F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* xorl<.f><.cc> 0,ximm,RC 0101110011000111F111cccccc0QQQQQ. */
+{ "xorl", 0x5CC77000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* xorl<.f><.cc> RB,RB,ximm 01011bbb11000111FBBB1111000QQQQQ. */
+{ "xorl", 0x58C70F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* xorl<.f> RA,ximm,u6 0101110001000111F111uuuuuuaaaaaa. */
+{ "xorl", 0x5C477000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* xorl<.f> 0,ximm,u6 0101110001000111F111uuuuuu111110. */
+{ "xorl", 0x5C47703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* xorl<.f><.cc> 0,ximm,u6 0101110011000111F111uuuuuu1QQQQQ. */
+{ "xorl", 0x5CC77020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xorl<.f> RA,limm,RC 0101111000000111F111ccccccaaaaaa. */
+{ "xorl", 0x5E077000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* xorl<.f> RA,RB,limm 01011bbb00000111FBBB111110aaaaaa. */
+{ "xorl", 0x58070F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* xorl<.f> 0,limm,RC 0101111000000111F111cccccc111110. */
+{ "xorl", 0x5E07703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* xorl<.f> 0,RB,limm 01011bbb00000111FBBB111110111110. */
+{ "xorl", 0x58070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* xorl<.f><.cc> 0,limm,RC 0101111011000111F111cccccc0QQQQQ. */
+{ "xorl", 0x5EC77000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* xorl<.f><.cc> RB,RB,limm 01011bbb11000111FBBB1111100QQQQQ. */
+{ "xorl", 0x58C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* xorl<.f> RA,limm,u6 0101111001000111F111uuuuuuaaaaaa. */
+{ "xorl", 0x5E477000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xorl<.f> 0,limm,u6 0101111001000111F111uuuuuu111110. */
+{ "xorl", 0x5E47703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xorl<.f><.cc> 0,limm,u6 0101111011000111F111uuuuuu1QQQQQ. */
+{ "xorl", 0x5EC77020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xorl<.f> 0,ximm,s12 0101110010000111F111ssssssSSSSSS. */
+{ "xorl", 0x5C877000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* xorl<.f> 0,limm,s12 0101111010000111F111ssssssSSSSSS. */
+{ "xorl", 0x5E877000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* xorl<.f> RA,ximm,ximm 0101110000000111F111111100aaaaaa. */
+{ "xorl", 0x5C077F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* xorl<.f> 0,ximm,ximm 0101110000000111F111111100111110. */
+{ "xorl", 0x5C077F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* xorl<.f><.cc> 0,ximm,ximm 0101110011000111F1111111000QQQQQ. */
+{ "xorl", 0x5CC77F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* xorl<.f> RA,limm,limm 0101111000000111F111111110aaaaaa. */
+{ "xorl", 0x5E077F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* xorl<.f> 0,limm,limm 0101111000000111F111111110111110. */
+{ "xorl", 0x5E077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* xorl<.f><.cc> 0,limm,limm 0101111011000111F1111111100QQQQQ. */
+{ "xorl", 0x5EC77F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* xor_s b,b,c 01111bbbccc00111. */
+{ "xor_s", 0x00007807, 0x0000F81F, ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
--
2.30.2
^ permalink raw reply [flat|nested] 14+ messages in thread