* [PATCH v2] x86: also use D for MOVBE
@ 2022-08-02 13:38 Jan Beulich
2022-08-02 15:55 ` H.J. Lu
0 siblings, 1 reply; 2+ messages in thread
From: Jan Beulich @ 2022-08-02 13:38 UTC (permalink / raw)
To: Binutils
First of all rename the meanwhile misleading Opcode_SIMD_FloatD, as it
has also been used for KMOV* and BNDMOV. Then simplify the condition
selecting which form if "reversing" to use - except for the MOV to/from
control/debug/test registers all extended opcode space insns use bit 0
(rather than bit 1) to indicate the direction (from/to memory) of an
operation. With that, D can simply be set on the first of the two
templates, while the other can be dropped.
---
v2: Add comment.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3572,7 +3572,7 @@ build_vex_prefix (const insn_template *t
if (i.tm.opcode_modifier.d)
i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
- ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
+ ? Opcode_ExtD : Opcode_SIMD_IntD;
else /* Use the next insn. */
install_template (&t[1]);
}
@@ -6757,13 +6757,13 @@ match_template (char mnem_suffix)
found_reverse_match = Opcode_VexW;
goto check_operands_345;
}
- else if (operand_types[0].bitfield.xmmword
- || operand_types[i.operands - 1].bitfield.xmmword
- || operand_types[0].bitfield.class == RegMMX
- || operand_types[i.operands - 1].bitfield.class == RegMMX
- || is_any_vex_encoding(t))
+ else if (t->opcode_modifier.opcodespace != SPACE_BASE
+ && (t->opcode_modifier.opcodespace != SPACE_0F
+ /* MOV to/from CR/DR/TR, as an exception, follow
+ the base opcode space encoding model. */
+ || (t->base_opcode | 7) != 0x27))
found_reverse_match = (t->base_opcode & 0xee) != 0x6e
- ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
+ ? Opcode_ExtD : Opcode_SIMD_IntD;
else
found_reverse_match = Opcode_D;
if (t->opcode_modifier.floatr)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -928,7 +928,7 @@ typedef struct insn_template
unset if Regmem --> Reg. */
#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
-#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
+#define Opcode_ExtD 0x1 /* Direction bit for extended opcode space insns. */
#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
/* The next value is arbitrary, as long as it's non-zero and distinct
from all other values above. */
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -161,8 +161,7 @@ movq, 0xf21, None, Cpu64, D|RegMem|Size6
mov, 0xf24, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Test, Reg32 }
// Move after swapping the bytes
-movbe, 0x0f38f0, None, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-movbe, 0x0f38f1, None, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Word|Dword|Qword|Unspecified|BaseIndex }
+movbe, 0x0f38f0, None, CpuMovbe, D|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// Move with sign extend.
// "movsbl" & "movsbw" must not be unified into "movsb" to avoid
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH v2] x86: also use D for MOVBE
2022-08-02 13:38 [PATCH v2] x86: also use D for MOVBE Jan Beulich
@ 2022-08-02 15:55 ` H.J. Lu
0 siblings, 0 replies; 2+ messages in thread
From: H.J. Lu @ 2022-08-02 15:55 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Tue, Aug 2, 2022 at 6:38 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> First of all rename the meanwhile misleading Opcode_SIMD_FloatD, as it
> has also been used for KMOV* and BNDMOV. Then simplify the condition
> selecting which form if "reversing" to use - except for the MOV to/from
> control/debug/test registers all extended opcode space insns use bit 0
> (rather than bit 1) to indicate the direction (from/to memory) of an
> operation. With that, D can simply be set on the first of the two
> templates, while the other can be dropped.
> ---
> v2: Add comment.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -3572,7 +3572,7 @@ build_vex_prefix (const insn_template *t
>
> if (i.tm.opcode_modifier.d)
> i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
> - ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
> + ? Opcode_ExtD : Opcode_SIMD_IntD;
> else /* Use the next insn. */
> install_template (&t[1]);
> }
> @@ -6757,13 +6757,13 @@ match_template (char mnem_suffix)
> found_reverse_match = Opcode_VexW;
> goto check_operands_345;
> }
> - else if (operand_types[0].bitfield.xmmword
> - || operand_types[i.operands - 1].bitfield.xmmword
> - || operand_types[0].bitfield.class == RegMMX
> - || operand_types[i.operands - 1].bitfield.class == RegMMX
> - || is_any_vex_encoding(t))
> + else if (t->opcode_modifier.opcodespace != SPACE_BASE
> + && (t->opcode_modifier.opcodespace != SPACE_0F
> + /* MOV to/from CR/DR/TR, as an exception, follow
> + the base opcode space encoding model. */
> + || (t->base_opcode | 7) != 0x27))
> found_reverse_match = (t->base_opcode & 0xee) != 0x6e
> - ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
> + ? Opcode_ExtD : Opcode_SIMD_IntD;
> else
> found_reverse_match = Opcode_D;
> if (t->opcode_modifier.floatr)
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -928,7 +928,7 @@ typedef struct insn_template
> unset if Regmem --> Reg. */
> #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
> #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
> -#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
> +#define Opcode_ExtD 0x1 /* Direction bit for extended opcode space insns. */
> #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
> /* The next value is arbitrary, as long as it's non-zero and distinct
> from all other values above. */
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -161,8 +161,7 @@ movq, 0xf21, None, Cpu64, D|RegMem|Size6
> mov, 0xf24, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Test, Reg32 }
>
> // Move after swapping the bytes
> -movbe, 0x0f38f0, None, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> -movbe, 0x0f38f1, None, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Word|Dword|Qword|Unspecified|BaseIndex }
> +movbe, 0x0f38f0, None, CpuMovbe, D|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
>
> // Move with sign extend.
> // "movsbl" & "movsbw" must not be unified into "movsb" to avoid
OK.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2022-08-02 15:56 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-08-02 13:38 [PATCH v2] x86: also use D for MOVBE Jan Beulich
2022-08-02 15:55 ` H.J. Lu
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).