* [PATCH] x86: also use D for XCHG and TEST
@ 2022-12-01 9:09 Jan Beulich
2022-12-01 16:42 ` H.J. Lu
0 siblings, 1 reply; 2+ messages in thread
From: Jan Beulich @ 2022-12-01 9:09 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
Leverage the C (commutative) attribute to also reduce the number of XCHG
and TEST templates we have. This way the reg <-> r/m (and reg <-> reg for
XCHG) forms can also be folded into a single template each, utilizing D.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6803,8 +6803,10 @@ match_template (char mnem_suffix)
|| (t->base_opcode | 7) != 0x27))
found_reverse_match = (t->base_opcode & 0xee) != 0x6e
? Opcode_ExtD : Opcode_SIMD_IntD;
- else
+ else if (!t->opcode_modifier.commutative)
found_reverse_match = Opcode_D;
+ else
+ found_reverse_match = ~0;
}
else
{
@@ -7001,9 +7003,6 @@ match_template (char mnem_suffix)
i.tm.base_opcode ^= found_reverse_match;
- i.tm.operand_types[0] = operand_types[i.operands - 1];
- i.tm.operand_types[i.operands - 1] = operand_types[0];
-
/* Certain SIMD insns have their load forms specified in the opcode
table, and hence we need to _set_ RegMem instead of clearing it.
We need to avoid setting the bit though on insns like KMOVW. */
@@ -7011,6 +7010,11 @@ match_template (char mnem_suffix)
= i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d
&& i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx
&& !i.tm.opcode_modifier.regmem;
+
+ /* Fall through. */
+ case ~0:
+ i.tm.operand_types[0] = operand_types[i.operands - 1];
+ i.tm.operand_types[i.operands - 1] = operand_types[0];
break;
case Opcode_VexW:
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -230,10 +230,8 @@ popa, 0x61, None, Cpu186|CpuNo64, Defaul
// xchg commutes: we allow both operand orders.
// In the 64bit code, xchg rax, rax is reused for new nop instruction.
-xchg, 0x90, None, 0, CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword }
-xchg, 0x90, None, 0, CheckRegSize|No_bSuf|No_sSuf, { Acc|Word|Dword|Qword, Reg16|Reg32|Reg64 }
-xchg, 0x86, None, 0, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-xchg, 0x86, None, 0, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+xchg, 0x90, None, 0, D|C|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword }
+xchg, 0x86, None, 0, D|W|C|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
// In/out from ports.
in, 0xe4, None, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword }
@@ -301,8 +299,7 @@ cmp, 0x83, 7, 0, Modrm|No_bSuf|No_sSuf,
cmp, 0x3c, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
cmp, 0x80, 7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-test, 0x84, None, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|Byte|Word|Dword|Qword|BaseIndex }
-test, 0x84, None, 0, W|CheckRegSize|Modrm|No_sSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+test, 0x84, None, 0, D|W|C|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
test, 0xa8, None, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
test, 0xf6, 0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] x86: also use D for XCHG and TEST
2022-12-01 9:09 [PATCH] x86: also use D for XCHG and TEST Jan Beulich
@ 2022-12-01 16:42 ` H.J. Lu
0 siblings, 0 replies; 2+ messages in thread
From: H.J. Lu @ 2022-12-01 16:42 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Thu, Dec 1, 2022 at 1:09 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> Leverage the C (commutative) attribute to also reduce the number of XCHG
> and TEST templates we have. This way the reg <-> r/m (and reg <-> reg for
> XCHG) forms can also be folded into a single template each, utilizing D.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -6803,8 +6803,10 @@ match_template (char mnem_suffix)
> || (t->base_opcode | 7) != 0x27))
> found_reverse_match = (t->base_opcode & 0xee) != 0x6e
> ? Opcode_ExtD : Opcode_SIMD_IntD;
> - else
> + else if (!t->opcode_modifier.commutative)
> found_reverse_match = Opcode_D;
> + else
> + found_reverse_match = ~0;
> }
> else
> {
> @@ -7001,9 +7003,6 @@ match_template (char mnem_suffix)
>
> i.tm.base_opcode ^= found_reverse_match;
>
> - i.tm.operand_types[0] = operand_types[i.operands - 1];
> - i.tm.operand_types[i.operands - 1] = operand_types[0];
> -
> /* Certain SIMD insns have their load forms specified in the opcode
> table, and hence we need to _set_ RegMem instead of clearing it.
> We need to avoid setting the bit though on insns like KMOVW. */
> @@ -7011,6 +7010,11 @@ match_template (char mnem_suffix)
> = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d
> && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx
> && !i.tm.opcode_modifier.regmem;
> +
> + /* Fall through. */
> + case ~0:
> + i.tm.operand_types[0] = operand_types[i.operands - 1];
> + i.tm.operand_types[i.operands - 1] = operand_types[0];
> break;
>
> case Opcode_VexW:
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -230,10 +230,8 @@ popa, 0x61, None, Cpu186|CpuNo64, Defaul
> // xchg commutes: we allow both operand orders.
>
> // In the 64bit code, xchg rax, rax is reused for new nop instruction.
> -xchg, 0x90, None, 0, CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword }
> -xchg, 0x90, None, 0, CheckRegSize|No_bSuf|No_sSuf, { Acc|Word|Dword|Qword, Reg16|Reg32|Reg64 }
> -xchg, 0x86, None, 0, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
> -xchg, 0x86, None, 0, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
> +xchg, 0x90, None, 0, D|C|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword }
> +xchg, 0x86, None, 0, D|W|C|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>
> // In/out from ports.
> in, 0xe4, None, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword }
> @@ -301,8 +299,7 @@ cmp, 0x83, 7, 0, Modrm|No_bSuf|No_sSuf,
> cmp, 0x3c, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
> cmp, 0x80, 7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
>
> -test, 0x84, None, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|Byte|Word|Dword|Qword|BaseIndex }
> -test, 0x84, None, 0, W|CheckRegSize|Modrm|No_sSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
> +test, 0x84, None, 0, D|W|C|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> test, 0xa8, None, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
> test, 0xf6, 0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
>
OK.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2022-12-01 16:42 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-01 9:09 [PATCH] x86: also use D for XCHG and TEST Jan Beulich
2022-12-01 16:42 ` H.J. Lu
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).