* [PATCH v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard
@ 2022-11-21 12:00 zengxiao
2022-11-23 2:52 ` Nelson Chu
0 siblings, 1 reply; 3+ messages in thread
From: zengxiao @ 2022-11-21 12:00 UTC (permalink / raw)
To: binutils; +Cc: shihua, nelson, palmer, kito.cheng, Xiao Zeng
From: Xiao Zeng <zengxiao@eswincomputing.com>
The R_RISCV_SUB6 only the lower 6 bits of the code are valid, which
can be found in 8.5. Relocations of:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0-rc4/riscv-abi.pdf
bfd/ChangeLog:
* elfnn-riscv.c (riscv_elf_relocate_section): Take the R_RISCV_SUB6
lower 6 bits as the significant bit.
* elfxx-riscv.c (riscv_elf_add_sub_reloc): Likewise.
---
bfd/elfnn-riscv.c | 4 ++++
bfd/elfxx-riscv.c | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 0570a971b5a..a02aa64786e 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -2427,6 +2427,10 @@ riscv_elf_relocate_section (bfd *output_bfd,
break;
case R_RISCV_SUB6:
+ relocation = (old_value & ~howto->dst_mask)
+ | (((old_value & howto->dst_mask) - relocation)
+ & howto->dst_mask);
+ break;
case R_RISCV_SUB8:
case R_RISCV_SUB16:
case R_RISCV_SUB32:
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index afbde56b9e5..2db24acf7a5 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -994,6 +994,10 @@ riscv_elf_add_sub_reloc (bfd *abfd,
relocation = old_value + relocation;
break;
case R_RISCV_SUB6:
+ relocation = (old_value & ~howto->dst_mask)
+ | (((old_value & howto->dst_mask) - relocation)
+ & howto->dst_mask);
+ break;
case R_RISCV_SUB8:
case R_RISCV_SUB16:
case R_RISCV_SUB32:
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard
2022-11-21 12:00 [PATCH v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard zengxiao
@ 2022-11-23 2:52 ` Nelson Chu
2022-11-23 9:05 ` Xiao Zeng
0 siblings, 1 reply; 3+ messages in thread
From: Nelson Chu @ 2022-11-23 2:52 UTC (permalink / raw)
To: zengxiao; +Cc: binutils, shihua, palmer, kito.cheng
Thanks for fixing this. We also need to add the out-of-range check
for R_RISCV_SUB6 in the riscv_elf_add_sub_reloc, and the overflow
checks for all ADD/SUB/SET relocations, but since they can be added in
the later patches, so I committed this one after passing the
riscv-gnu-toolchain regressions.
Thanks
Nelson
On Mon, Nov 21, 2022 at 8:02 PM <zengxiao@eswincomputing.com> wrote:
>
> From: Xiao Zeng <zengxiao@eswincomputing.com>
>
> The R_RISCV_SUB6 only the lower 6 bits of the code are valid, which
> can be found in 8.5. Relocations of:
> https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0-rc4/riscv-abi.pdf
>
> bfd/ChangeLog:
>
> * elfnn-riscv.c (riscv_elf_relocate_section): Take the R_RISCV_SUB6
> lower 6 bits as the significant bit.
> * elfxx-riscv.c (riscv_elf_add_sub_reloc): Likewise.
> ---
> bfd/elfnn-riscv.c | 4 ++++
> bfd/elfxx-riscv.c | 4 ++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
> index 0570a971b5a..a02aa64786e 100644
> --- a/bfd/elfnn-riscv.c
> +++ b/bfd/elfnn-riscv.c
> @@ -2427,6 +2427,10 @@ riscv_elf_relocate_section (bfd *output_bfd,
> break;
>
> case R_RISCV_SUB6:
> + relocation = (old_value & ~howto->dst_mask)
> + | (((old_value & howto->dst_mask) - relocation)
> + & howto->dst_mask);
> + break;
The old_value needs to be defined, but it's easy enough to add, so I fixed it.
> case R_RISCV_SUB8:
> case R_RISCV_SUB16:
> case R_RISCV_SUB32:
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index afbde56b9e5..2db24acf7a5 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -994,6 +994,10 @@ riscv_elf_add_sub_reloc (bfd *abfd,
> relocation = old_value + relocation;
> break;
> case R_RISCV_SUB6:
> + relocation = (old_value & ~howto->dst_mask)
> + | (((old_value & howto->dst_mask) - relocation)
> + & howto->dst_mask);
> + break;
> case R_RISCV_SUB8:
> case R_RISCV_SUB16:
> case R_RISCV_SUB32:
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard
2022-11-23 2:52 ` Nelson Chu
@ 2022-11-23 9:05 ` Xiao Zeng
0 siblings, 0 replies; 3+ messages in thread
From: Xiao Zeng @ 2022-11-23 9:05 UTC (permalink / raw)
To: Nelson Chu; +Cc: binutils, shihua, palmer, kito.cheng
On Wed, Nov 23, 2022 at 12:00:00 AM Nelson Chu <nelson@rivosinc.com> wrote:
>
>Thanks for fixing this. We also need to add the out-of-range check
>for R_RISCV_SUB6 in the riscv_elf_add_sub_reloc, and the overflow
>checks for all ADD/SUB/SET relocations, but since they can be added in
>the later patches, so I committed this one after passing the
>riscv-gnu-toolchain regressions.
OK. In the next patch, I will solve this problem.
>
>Thanks
>Nelson
>
>On Mon, Nov 21, 2022 at 8:02 PM <zengxiao@eswincomputing.com> wrote:
>>
>> From: Xiao Zeng <zengxiao@eswincomputing.com>
>>
>> The R_RISCV_SUB6 only the lower 6 bits of the code are valid, which
>> can be found in 8.5. Relocations of:
>> https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0-rc4/riscv-abi.pdf
>>
>> bfd/ChangeLog:
>>
>> * elfnn-riscv.c (riscv_elf_relocate_section): Take the R_RISCV_SUB6
>> lower 6 bits as the significant bit.
>> * elfxx-riscv.c (riscv_elf_add_sub_reloc): Likewise.
>> ---
>> bfd/elfnn-riscv.c | 4 ++++
>> bfd/elfxx-riscv.c | 4 ++++
>> 2 files changed, 8 insertions(+)
>>
>> diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
>> index 0570a971b5a..a02aa64786e 100644
>> --- a/bfd/elfnn-riscv.c
>> +++ b/bfd/elfnn-riscv.c
>> @@ -2427,6 +2427,10 @@ riscv_elf_relocate_section (bfd *output_bfd,
>> break;
>>
>> case R_RISCV_SUB6:
>> + relocation = (old_value & ~howto->dst_mask)
>> + | (((old_value & howto->dst_mask) - relocation)
>> + & howto->dst_mask);
>> + break;
>
>The old_value needs to be defined, but it's easy enough to add, so I fixed it.
Thanks Nelson
>
>> case R_RISCV_SUB8:
>> case R_RISCV_SUB16:
>> case R_RISCV_SUB32:
>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> index afbde56b9e5..2db24acf7a5 100644
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -994,6 +994,10 @@ riscv_elf_add_sub_reloc (bfd *abfd,
>> relocation = old_value + relocation;
>> break;
>> case R_RISCV_SUB6:
>> + relocation = (old_value & ~howto->dst_mask)
>> + | (((old_value & howto->dst_mask) - relocation)
>> + & howto->dst_mask);
>> + break;
>> case R_RISCV_SUB8:
>> case R_RISCV_SUB16:
>> case R_RISCV_SUB32:
>> --
>> 2.34.1
>>
Thanks
Xiao
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-11-21 12:00 [PATCH v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard zengxiao
2022-11-23 2:52 ` Nelson Chu
2022-11-23 9:05 ` Xiao Zeng
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