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From: Nelson Chu <nelson@rivosinc.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: Re: [PING^1]Re: [PATCH] RISC-V: Remove RV32EF conflict
Date: Mon, 7 Nov 2022 11:48:21 +0800	[thread overview]
Message-ID: <CAPpQWtAPjT8RepJ3akEv0nZws8VbtyveUHTxgYG5ovFB3aHQyg@mail.gmail.com> (raw)
In-Reply-To: <39cd67c0-ec74-42f3-9805-519b9b43eaca@irq.a4lg.com>

OK, please commit since it looks good to Kito.

Thanks
Nelson

On Sat, Nov 5, 2022 at 7:50 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Ping.
>
> c.f.: Original
> <https://sourceware.org/pipermail/binutils/2022-October/123716.html>
> c.f.: LGTM by Kito
> <https://sourceware.org/pipermail/binutils/2022-October/123717.html>
>
> Regards,
> Tsukasa
>
> On 2022/10/19 22:14, Tsukasa OI wrote:
> > Despite that the RISC-V ISA Manual version 2.2 prohibited "RV32EF", later
> > versions beginning with the version 20190608-Base-Ratified removed this
> > restriction.  Because the 'E' extension is still a draft, the author chose
> > to *just* remove the conflict (not checking the ISA version).
> >
> > Note that, because RV32E is only used with a soft-float calling convention,
> > there's no valid official ABI for RV32EF.  It means, even if we can assemble
> > a program with -march=rv32ef -mabi=ilp32e, floating-point registers are kept
> > in an unmanaged state (outside ABI management).
> >
> > The purpose of this commit is to suppress unnecessary errors while parsing
> > an ISA string and/or disassembling, not to allow hard-float with RVE.
> >
> > bfd/ChangeLog:
> >
> >       * elfxx-riscv.c (riscv_parse_check_conflicts): Accept RV32EF
> >       because only older specifications disallowed it.
> >
> > gas/ChangeLog:
> >
> >       * testsuite/gas/riscv/march-fail-rv32ef.d: Remove as not directly
> >       prohibited.
> >       * testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
> > ---
> >  bfd/elfxx-riscv.c                           | 7 -------
> >  gas/testsuite/gas/riscv/march-fail-rv32ef.d | 3 ---
> >  gas/testsuite/gas/riscv/march-fail-rv32ef.l | 2 --
> >  3 files changed, 12 deletions(-)
> >  delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32ef.d
> >  delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32ef.l
> >
> > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > index c89b1e53e92..334a63f0873 100644
> > --- a/bfd/elfxx-riscv.c
> > +++ b/bfd/elfxx-riscv.c
> > @@ -1870,13 +1870,6 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
> >        rps->error_handler (_("rv%d does not support the `q' extension"), xlen);
> >        no_conflict = false;
> >      }
> > -  if (riscv_lookup_subset (rps->subset_list, "e", &subset)
> > -      && riscv_lookup_subset (rps->subset_list, "f", &subset))
> > -    {
> > -      rps->error_handler
> > -        (_("rv32e does not support the `f' extension"));
> > -      no_conflict = false;
> > -    }
> >    if (riscv_lookup_subset (rps->subset_list, "zfinx", &subset)
> >        && riscv_lookup_subset (rps->subset_list, "f", &subset))
> >      {
> > diff --git a/gas/testsuite/gas/riscv/march-fail-rv32ef.d b/gas/testsuite/gas/riscv/march-fail-rv32ef.d
> > deleted file mode 100644
> > index d7b51c3c17d..00000000000
> > --- a/gas/testsuite/gas/riscv/march-fail-rv32ef.d
> > +++ /dev/null
> > @@ -1,3 +0,0 @@
> > -#as: -march=rv32ef
> > -#source: empty.s
> > -#error_output: march-fail-rv32ef.l
> > diff --git a/gas/testsuite/gas/riscv/march-fail-rv32ef.l b/gas/testsuite/gas/riscv/march-fail-rv32ef.l
> > deleted file mode 100644
> > index e6d93f28fa5..00000000000
> > --- a/gas/testsuite/gas/riscv/march-fail-rv32ef.l
> > +++ /dev/null
> > @@ -1,2 +0,0 @@
> > -.*Assembler messages:
> > -.*Error: .*rv32e does not support the `f' extension
> >
> > base-commit: 2b06e59de0675c2cb526af2de6803dae29703d15

      reply	other threads:[~2022-11-07  3:48 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-19 13:14 Tsukasa OI
2022-10-19 13:23 ` Kito Cheng
2022-11-05 11:49 ` [PING^1]Re: " Tsukasa OI
2022-11-07  3:48   ` Nelson Chu [this message]

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