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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Nelson Chu <nelson@rivosinc.com>
Cc: binutils@sourceware.org
Subject: [PING^1]Re: [PATCH] RISC-V: Remove RV32EF conflict
Date: Sat, 5 Nov 2022 20:49:55 +0900	[thread overview]
Message-ID: <39cd67c0-ec74-42f3-9805-519b9b43eaca@irq.a4lg.com> (raw)
In-Reply-To: <345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>

Ping.

c.f.: Original
<https://sourceware.org/pipermail/binutils/2022-October/123716.html>
c.f.: LGTM by Kito
<https://sourceware.org/pipermail/binutils/2022-October/123717.html>

Regards,
Tsukasa

On 2022/10/19 22:14, Tsukasa OI wrote:
> Despite that the RISC-V ISA Manual version 2.2 prohibited "RV32EF", later
> versions beginning with the version 20190608-Base-Ratified removed this
> restriction.  Because the 'E' extension is still a draft, the author chose
> to *just* remove the conflict (not checking the ISA version).
> 
> Note that, because RV32E is only used with a soft-float calling convention,
> there's no valid official ABI for RV32EF.  It means, even if we can assemble
> a program with -march=rv32ef -mabi=ilp32e, floating-point registers are kept
> in an unmanaged state (outside ABI management).
> 
> The purpose of this commit is to suppress unnecessary errors while parsing
> an ISA string and/or disassembling, not to allow hard-float with RVE.
> 
> bfd/ChangeLog:
> 
> 	* elfxx-riscv.c (riscv_parse_check_conflicts): Accept RV32EF
> 	because only older specifications disallowed it.
> 
> gas/ChangeLog:
> 
> 	* testsuite/gas/riscv/march-fail-rv32ef.d: Remove as not directly
> 	prohibited.
> 	* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
> ---
>  bfd/elfxx-riscv.c                           | 7 -------
>  gas/testsuite/gas/riscv/march-fail-rv32ef.d | 3 ---
>  gas/testsuite/gas/riscv/march-fail-rv32ef.l | 2 --
>  3 files changed, 12 deletions(-)
>  delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32ef.d
>  delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32ef.l
> 
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index c89b1e53e92..334a63f0873 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1870,13 +1870,6 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
>        rps->error_handler (_("rv%d does not support the `q' extension"), xlen);
>        no_conflict = false;
>      }
> -  if (riscv_lookup_subset (rps->subset_list, "e", &subset)
> -      && riscv_lookup_subset (rps->subset_list, "f", &subset))
> -    {
> -      rps->error_handler
> -        (_("rv32e does not support the `f' extension"));
> -      no_conflict = false;
> -    }
>    if (riscv_lookup_subset (rps->subset_list, "zfinx", &subset)
>        && riscv_lookup_subset (rps->subset_list, "f", &subset))
>      {
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32ef.d b/gas/testsuite/gas/riscv/march-fail-rv32ef.d
> deleted file mode 100644
> index d7b51c3c17d..00000000000
> --- a/gas/testsuite/gas/riscv/march-fail-rv32ef.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv32ef
> -#source: empty.s
> -#error_output: march-fail-rv32ef.l
> diff --git a/gas/testsuite/gas/riscv/march-fail-rv32ef.l b/gas/testsuite/gas/riscv/march-fail-rv32ef.l
> deleted file mode 100644
> index e6d93f28fa5..00000000000
> --- a/gas/testsuite/gas/riscv/march-fail-rv32ef.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*Assembler messages:
> -.*Error: .*rv32e does not support the `f' extension
> 
> base-commit: 2b06e59de0675c2cb526af2de6803dae29703d15

  parent reply	other threads:[~2022-11-05 11:50 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-19 13:14 Tsukasa OI
2022-10-19 13:23 ` Kito Cheng
2022-11-05 11:49 ` Tsukasa OI [this message]
2022-11-07  3:48   ` [PING^1]Re: " Nelson Chu

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