[PATCH] ppc/svp64: support svshape2 instruction

[PATCH] ppc/svp64: support svshape2 instruction

[Dmitry Selyutin]

https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svshape
https://libre-soc.org/openpower/sv/remap/#svshape2
https://libre-soc.org/openpower/isa/simplev/
---
 gas/testsuite/gas/ppc/svshape.s |  6 +++
 opcodes/ppc-opc.c               | 75 ++++++++++++++++++++++++++++++++-
 2 files changed, 80 insertions(+), 1 deletion(-)

diff --git a/gas/testsuite/gas/ppc/svshape.s b/gas/testsuite/gas/ppc/svshape.s
index c83373ba372..39d4579a200 100644
--- a/gas/testsuite/gas/ppc/svshape.s
+++ b/gas/testsuite/gas/ppc/svshape.s
@@ -3,3 +3,9 @@ svshape 1,32,1,0,0
 svshape 1,1,32,0,0
 svshape 1,1,1,15,0
 svshape 1,1,1,0,1
+svshape2 15,0,0,1,0,0
+svshape2 0,1,0,1,0,0
+svshape2 0,0,31,1,0,0
+svshape2 0,0,0,32,0,0
+svshape2 0,0,0,1,1,0
+svshape2 0,0,0,1,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 934b1bf4e85..fb7fb79cba4 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2719,6 +2719,67 @@ extract_thds (uint64_t insn,
 
   return value;
 }
+
+static uint64_t
+insert_SVrm (uint64_t insn,
+	     int64_t value,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     const char **errmsg)
+{
+  /*
+   * 0b1000 and 0b1001 values are reserved for svshape2.
+   * svshape is SVM-form; svshape2 is SVM2-form.
+   *
+   * svshape XO:
+   *   0000-011001
+   *   0001-011001
+   *   0010-011001
+   *   0011-011001
+   *   0100-011001
+   *   0101-011001
+   *   0110-011001
+   *   0111-011001
+   *   1010-011001
+   *   1011-011001
+   *   1100-011001
+   *   1101-011001
+   *   1110-011001
+   *   1111-011001
+   *
+   * svshape2 XO:
+   *   100--011001
+   *
+   * # 1.6.35 SVM-FORM
+   * |0     |6        |11      |16    |21    |25 |26    |31  |
+   * | PO   |  SVxd   |   SVyd | SVzd | SVrm |vf |   XO      |
+   *
+   * # 1.6.35.1 SVM2-FORM
+   * |0     |6     |10|11      |16    |21 |24|25 |26    |31  |
+   * | PO   | offs |yx|   rmm  | SVd  |XO |mm|sk |   XO      |
+   */
+  if ((value == 8) || (value == 9))
+    *errmsg = _("invalid SVrm value");
+
+  return insn | ((value & 0xf) << 7);
+}
+
+static int64_t
+extract_SVrm (uint64_t insn,
+	      ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	      int *invalid)
+{
+  int64_t value = (insn >> 21) & 0x1f;
+
+  /*
+   * We should never meet the condition below in practice.
+   * svshape2 opcode and mask should always be matched first.
+   */
+  if ((value == 8) || (value == 9))
+    *invalid = 1;
+
+  return value;
+}
+
 \f
 /* The operands table.
 
@@ -3110,6 +3171,7 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The L field in a D or X form instruction.  */
 #define L IMM20 + 1
+#define yx10 L
   { 0x1, 21, NULL, NULL, 0 },
 
   /* The optional L field in tlbie and tlbiel instructions.  */
@@ -3864,13 +3926,16 @@ const struct powerpc_operand powerpc_operands[] =
   { 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO },
 
 #define SVrm SVzd + 1
-  { 0xf, 7, NULL, NULL, 0 },
+  { 0xf, 7, insert_SVrm, extract_SVrm, 0 },
 
 #define mi1 SVrm + 1
   { 0x3, 17, NULL, NULL, 0 },
 
 #define mi2 mi1 + 1
   { 0x3, 15, NULL, NULL, 0 },
+
+#define SVo mi2 + 1
+  { 0xf, 22, NULL, NULL, 0 },
 };
 
 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4759,6 +4824,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
    | (((uint64_t)(xop)) & 0x3f))
 #define SVM_MASK	SVM (0x3f, 0x3f)
 
+/* An SVM2 form instruction. */
+#define SVM2(op, xop)				\
+  (OP (op)					\
+   | (((((uint64_t)(xop)) >> 6) & 0x7) << 8)	\
+   | (((uint64_t)(xop)) & 0x3f))
+#define SVM2_MASK	SVM2 (0x3f, 0x1ff)
+
 /* An SVRM form instruction. */
 #define SVRM(op, xop)				\
   (OP (op)					\
@@ -6843,6 +6915,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"svstep",	SVL(22,19,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, SVi, vf}},
 {"svstep.",	SVL(22,19,1),	SVL_MASK,	SVP64,	PPCVLE,	{RT, SVi, vf}},
 
+{"svshape2",	SVM2(22,281),	SVM2_MASK,	SVP64,	PPCVLE,	{SVo, yx10, rmm, SVd, sk, mm}},
 {"svshape",	SVM(22,25),	SVM_MASK,	SVP64,	PPCVLE,	{SVxd, SVyd, SVzd, SVrm, vf}},
 
 {"setvl",	SVL(22,27,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
-- 
2.37.2

Re: [PATCH] ppc/svp64: support svshape2 instruction

[Dmitry Selyutin]

On Thu, Sep 8, 2022 at 9:26 PM Dmitry Selyutin <ghostmansd@gmail.com> wrote:
> +   * 0b1000 and 0b1001 values are reserved for svshape2.
> +  { 0xf, 7, insert_SVrm, extract_SVrm, 0 },
>  const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
> @@ -4759,6 +4824,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
>     | (((uint64_t)(xop)) & 0x3f))
>  #define SVM_MASK       SVM (0x3f, 0x3f)
>
> +/* An SVM2 form instruction. */
> +#define SVM2(op, xop)                          \
> +  (OP (op)                                     \
> +   | (((((uint64_t)(xop)) >> 6) & 0x7) << 8)   \
> +   | (((uint64_t)(xop)) & 0x3f))
> +#define SVM2_MASK      SVM2 (0x3f, 0x1ff)
>
> +{"svshape2",   SVM2(22,281),   SVM2_MASK,      SVP64,  PPCVLE, {SVo, yx10, rmm, SVd, sk, mm}},
>  {"svshape",    SVM(22,25),     SVM_MASK,       SVP64,  PPCVLE, {SVxd, SVyd, SVzd, SVrm, vf}},

This is a tricky part. svshape2 shares some of its bits with svshape;
we reserve 0b1000 and 0b1001 values from svshape for svshape2.
I didn't find a clear way to express it other than custom callback and
powerpc_opcodes insertion order.
The order is significant; if svshape2 ends up after svshape, things
break, due to the fact that svshape opcode starts performing a loose
match.
Any ideas on how to refactor or improve it are more than desired.

-- 
Best regards,
Dmitry Selyutin

Re: [PATCH] ppc/svp64: support svshape2 instruction

[lkcl]

[-- Attachment #1: Type: text/plain, Size: 758 bytes --]

On September 8, 2022 7:34:32 PM GMT+01:00, Dmitry Selyutin <ghostmansd@gmail.com> wrote:

> This is a tricky part. svshape2 shares some of its bits with svshape;
> we reserve 0b1000 and 0b1001 values from svshape for svshape2.

(background):

in hardware all 16 combinations are sent to the exact same unit.
the slightly different Form (SVM2 vs SVM because the opcode
args are different bitwidths) is for the convenience of the
assembly writer.

(further background):

svshape is insanely powerful, the sort of thing i revered in
supercomputers from the 90s.  it provides Matrix "Structure
Packing" schedules, DCT/FFT, Parallel Reduction, it's pretty
mental.  all in-place: no more loop-unrolling, no more transpose
copying of regs.

l.

Re: [PATCH] ppc/svp64: support svshape2 instruction

[Dmitry Selyutin]

On Thu, Sep 8, 2022 at 9:34 PM Dmitry Selyutin <ghostmansd@gmail.com> wrote:
> On Thu, Sep 8, 2022 at 9:26 PM Dmitry Selyutin <ghostmansd@gmail.com> wrote:
> > +{"svshape2",   SVM2(22,281),   SVM2_MASK,      SVP64,  PPCVLE, {SVo, yx10, rmm, SVd, sk, mm}},
> >  {"svshape",    SVM(22,25),     SVM_MASK,       SVP64,  PPCVLE, {SVxd, SVyd, SVzd, SVrm, vf}},
> The order is significant; if svshape2 ends up after svshape, things
> break, due to the fact that svshape opcode starts performing a loose
> match.

I've checked sources a bit more; perhaps this is a good way, other
instructions use this trick too (e.g. isel).

-- 
Best regards,
Dmitry Selyutin

Re: [PATCH] ppc/svp64: support svshape2 instruction

[Jan Beulich]

On 08.09.2022 20:25, Dmitry Selyutin via Binutils wrote:
> https://libre-soc.org/openpower/sv/
> https://libre-soc.org/openpower/sv/remap/#svshape
> https://libre-soc.org/openpower/sv/remap/#svshape2
> https://libre-soc.org/openpower/isa/simplev/
> ---
>  gas/testsuite/gas/ppc/svshape.s |  6 +++
>  opcodes/ppc-opc.c               | 75 ++++++++++++++++++++++++++++++++-
>  2 files changed, 80 insertions(+), 1 deletion(-)

Just to state the obvious - svshape.d also wants updating.

> @@ -6843,6 +6915,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>  {"svstep",	SVL(22,19,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, SVi, vf}},
>  {"svstep.",	SVL(22,19,1),	SVL_MASK,	SVP64,	PPCVLE,	{RT, SVi, vf}},
>  
> +{"svshape2",	SVM2(22,281),	SVM2_MASK,	SVP64,	PPCVLE,	{SVo, yx10, rmm, SVd, sk, mm}},
>  {"svshape",	SVM(22,25),	SVM_MASK,	SVP64,	PPCVLE,	{SVxd, SVyd, SVzd, SVrm, vf}},
>  
>  {"setvl",	SVL(22,27,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},

The doc talks of 7 arguments, the first one being merely a 3-bit
one (offs) with the fourth bit there instead being a separate
"inv". Is the doc stale or the patch?

Jan

Re: [PATCH] ppc/svp64: support svshape2 instruction

[Dmitry Selyutin]

On Mon, Sep 12, 2022 at 9:24 AM Jan Beulich <jbeulich@suse.com> wrote:
> Just to state the obvious - svshape.d also wants updating.

Nice catch! It seems I've sent the work from the intermediate branch
or checked the wrong branch; should be fine now.

> The doc talks of 7 arguments, the first one being merely a 3-bit
> one (offs) with the fourth bit there instead being a separate
> "inv". Is the doc stale or the patch?

I've based the works on the actual code used by the simulator:
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isatables/fields.text

My bet is that the documentation is obsolete; but I'll leave this
question to Luke.

-- 
Best regards,
Dmitry Selyutin

Re: [PATCH] ppc/svp64: support svshape2 instruction

[lkcl]

On Mon, Sep 12, 2022 at 7:24 AM Jan Beulich <jbeulich@suse.com> wrote:

> > +{"svshape2", SVM2(22,281),   SVM2_MASK,      SVP64,  PPCVLE, {SVo, yx10, rmm, SVd, sk, mm}},
> The doc talks of 7 arguments, the first one being merely a 3-bit
> one (offs) with the fourth bit there instead being a separate
> "inv". Is the doc stale or the patch?

yep good catch, really appreciated jan, as Dmitry notes in a later message,
i did try adding that "inv" argument you found in
https://libre-soc.org/openpower/sv/remap/#svshape2

but backed it out fast when it reduced the range of the offset.
the offsets being 0-15 (as opposed to 0-7) is an accidental but
very useful compensator for some of the vectors otherwise being
unable to start on anything other than even-numbered boundaries.

l.