From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>
Cc: "binutils@sourceware.org" <binutils@sourceware.org>,
"hjl.tools@gmail.com" <hjl.tools@gmail.com>
Subject: RE: [PATCH v2] Support Intel AVX10.1
Date: Wed, 16 Aug 2023 08:21:10 +0000 [thread overview]
Message-ID: <SA1PR11MB59461E6A631A6D6965FBF15FEC15A@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <4c47b6af-ed3f-ec3f-4a28-cd6e052470f9@suse.com>
> > I have an open after digging into .arch directives corner cases when we choose
> > to set/clear bits for AVX512 in AVX10.1.
> >
> > Should directives like .noavx512f .avx10.1 open zmm registers?
>
> You mean the combination of the two, in that order? Yes, of course.
>
> > For directive
> > .noavx512fp16 .avx10.1, should we enable zmm registers for AVX512FP16 insts?
>
> And then yes here, too.
>
> In both cases what remains to be determined is how vector size is to
> be limited. I think that wants to be independent of the .avx10.<N>.
>
That also met my expectation. And it will make everything easy to
understand.
> >> Right, a boolean is fine initially, but with the spec explicitly allowing the 128-
> >> bits-only mode, I'm pretty sure we ought to support that rather sooner than
> >> later. After all, more artificial environments (emulators,
> >> virtualization) may expose feature combinations not ever seen on real
> >> hardware.
> >
> > After I think twice on that, I suppose maybe it is not that appropriate to put it
> > into i386_opcode_modifier since in AVX10, the vector width is depends on CPU.
> > I suppose i386_opcode_modifier is a feature for instructions but not CPU.
>
> I disagree. See the uses of EVex, for example. As said above, I think
> maximum vector width and ISA extensions want dealing with separately,
> and only the latter would generally qualify for Cpu* flags. Furthermore
> recall that the attribute wants widening sooner or later, and Cpu*
> flags are uniformly boolean. Only attributes may have numeric values.
After I checked code, I still miss the point here.
My concern is how to actually disable the zmm registers for AVX10/256
and ymm registers for theoretical AVX10/128. I suppose i386_opcode_modifier
is more related to building up the whole encoding. But each AVX10.X/256 is an
actual arch.
Adding a feature in i386_opcode_modifier can indicate what is the maximum
vector length the instruction is allowed on all archs but has nothing to do with
disabling zmm registers on an 256-bit only arch.
I might be wrong on the understanding on what to add in i386_opcode_modifier.
Please just correct if there is something wrong.
Thx,
Haochen
>
> Jan
next prev parent reply other threads:[~2023-08-16 8:21 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-27 7:15 [PATCH] " Haochen Jiang
2023-07-27 11:23 ` Jan Beulich
2023-07-28 2:50 ` Jiang, Haochen
2023-07-28 6:53 ` Jan Beulich
2023-08-01 2:18 ` Jiang, Haochen
2023-08-01 6:49 ` Jan Beulich
2023-08-04 7:45 ` Jiang, Haochen
2023-08-04 7:57 ` Jan Beulich
2023-08-14 6:45 ` [PATCH v2] " Haochen Jiang
2023-08-14 8:19 ` Jan Beulich
2023-08-14 8:46 ` Jiang, Haochen
2023-08-14 10:33 ` Jan Beulich
2023-08-14 10:35 ` Jan Beulich
2023-08-15 8:32 ` Jiang, Haochen
2023-08-15 14:10 ` Jan Beulich
2023-08-16 8:21 ` Jiang, Haochen [this message]
2023-08-16 8:59 ` Jan Beulich
2023-08-17 9:08 ` Jan Beulich
2023-08-18 6:53 ` Jan Beulich
2023-08-18 13:03 ` Jan Beulich
2023-08-23 2:20 ` Jiang, Haochen
2023-08-23 3:34 ` [RFC][PATCH v3] " Haochen Jiang
2023-08-23 7:17 ` Jan Beulich
2023-08-23 5:54 ` [PATCH v2] " Jan Beulich
2023-08-23 6:21 ` Jiang, Haochen
2023-08-23 6:24 ` Jan Beulich
2023-08-23 6:25 ` Jiang, Haochen
2023-08-23 6:39 ` Jan Beulich
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