From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Subject: RE: [PATCH v2] Support Intel AVX10.1
Date: Wed, 23 Aug 2023 02:20:58 +0000 [thread overview]
Message-ID: <SA1PR11MB59468DDFAC764A55725D94A1EC1CA@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <96638e6e-142f-b7f2-3a95-56e70e8d159f@suse.com>
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, August 18, 2023 9:03 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; binutils@sourceware.org
> Subject: Re: [PATCH v2] Support Intel AVX10.1
>
> On 14.08.2023 08:45, Haochen Jiang wrote:
> > @@ -1315,6 +1321,20 @@ output_i386_opcode (FILE *table, const char
> *name, char *str,
> > ident = mkident (name);
> > fprintf (table, " { MN_%s, 0x%0*llx%s, %u,",
> > ident, 2 * (int)length, opcode, end, i);
> > +
> > + j = strlen(ident);
> > + /* All AVX512F based instructions are usable for AVX10.1 except
> > + AVX512PF/ER/4FMAPS/4VNNIW/VP2INTERSECT. */ if (strstr
> > + (cpu_flags, "AVX512")
> > + && !strstr (cpu_flags, "AVX512PF")
> > + && !strstr (cpu_flags, "AVX512ER")
> > + && !strstr (cpu_flags, "4FMAPS")
> > + && !strstr (cpu_flags, "4VNNIW")
> > + && !strstr (cpu_flags, "VP2INTERSECT"))
> > + {
> > + cpu_flags = concat (cpu_flags, "|AVX10_1", NULL);
> > + k = 1;
> > + }
> > free (ident);
>
> While making a patch myself along the lines of what I had outlined, I came to
> realize that the above isn't enough. (I'm pretty sure I wouldn't have spotted
> this by merely reviewing your patch.) This may be a result of the spec being
> somewhat ambiguous when it comes to GFNI, VAES, and VPCLMULQDQ.
> There's a note there saying something about the respective EVEX encodings.
> But that still requires the VEX encodings connected to these three features to
> also become suitably available. While this works fine for GFNI, it doesn't for
> the other two: The 128-bit VEX encodings, which surely are available when the
> 256-bit ones are, would become impossible to use. The assembler would pick
> the (larger) EVEX forms instead. There are two ways to solve this that I can see
> right away:
> 1) AES becomes a dependency of VAES (and PCLMULQDQ one of
> VPCLMULQDQ)
> 2) We put in place extra templates.
> I'm wary of the first option as long as not at least informally supported by you
> (Intel). Hence I went with option 2 for now.
>
> I'm only done with the /512 patch, so I won't post right away. I'm still
> debating with myself whether to control maximum vector length via a new
> directive, or via a special form of .arch.
Hi Jan,
Do you think a command line option like -mavx10maxvl=256/512 with default 512
is ok for this scenario? I am working to revise the AVX10.1 patch like that.
Thx,
Haochen
>
> Jan
next prev parent reply other threads:[~2023-08-23 2:21 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-27 7:15 [PATCH] " Haochen Jiang
2023-07-27 11:23 ` Jan Beulich
2023-07-28 2:50 ` Jiang, Haochen
2023-07-28 6:53 ` Jan Beulich
2023-08-01 2:18 ` Jiang, Haochen
2023-08-01 6:49 ` Jan Beulich
2023-08-04 7:45 ` Jiang, Haochen
2023-08-04 7:57 ` Jan Beulich
2023-08-14 6:45 ` [PATCH v2] " Haochen Jiang
2023-08-14 8:19 ` Jan Beulich
2023-08-14 8:46 ` Jiang, Haochen
2023-08-14 10:33 ` Jan Beulich
2023-08-14 10:35 ` Jan Beulich
2023-08-15 8:32 ` Jiang, Haochen
2023-08-15 14:10 ` Jan Beulich
2023-08-16 8:21 ` Jiang, Haochen
2023-08-16 8:59 ` Jan Beulich
2023-08-17 9:08 ` Jan Beulich
2023-08-18 6:53 ` Jan Beulich
2023-08-18 13:03 ` Jan Beulich
2023-08-23 2:20 ` Jiang, Haochen [this message]
2023-08-23 3:34 ` [RFC][PATCH v3] " Haochen Jiang
2023-08-23 7:17 ` Jan Beulich
2023-08-23 5:54 ` [PATCH v2] " Jan Beulich
2023-08-23 6:21 ` Jiang, Haochen
2023-08-23 6:24 ` Jan Beulich
2023-08-23 6:25 ` Jiang, Haochen
2023-08-23 6:39 ` Jan Beulich
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