RE: [PATCH v3 6/9] Support APX NDD

["Cui, Lili" <lili.cui@intel.com>]

> On 26.03.2024 09:22, Cui, Lili wrote:
> >> On 22.03.2024 11:02, Jan Beulich wrote:
> >>> On 08.12.2023 15:12, Jan Beulich wrote:
> >>>> On 24.11.2023 08:02, Cui, Lili wrote:
> >>>>> +rol, 0xd0/0, APX_F,
> >>>>>
> >> +W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVex128|EVexMap4|NF,
> {
> >>>>> +Imm1,
> >>>>>
> >> +Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseInd
> >> ex,
> >>>>> +Reg8|Reg16|Reg32|Reg64 }
> >>>>>  rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1,
> >>>>>
> >>
> Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex
> >>  }
> >>>>> +rol, 0xc0/0, APX_F,
> >>>>>
> >> +W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVex128|EVexMap4|NF,
> {
> >>>>> +Imm8|Imm8S,
> >>>>>
> >> +Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseInd
> >> ex,
> >>>>> +Reg8|Reg16|Reg32|Reg64 }
> >>>>>  rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S,
> >>>>>
> >>
> Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex
> >>  }
> >>>>> +rol, 0xd2/0, APX_F,
> >>>>>
> >> +W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVex128|EVexMap4|NF,
> {
> >>>>> +ShiftCount,
> >>>>>
> >> +Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseInd
> >> ex,
> >>>>> +Reg8|Reg16|Reg32|Reg64 }
> >>>>>  rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount,
> >>>>>
> >>
> Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex
> >>  }
> >>>>> +rol, 0xd0/0, APX_F,
> >>>>>
> >> +W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVex128|EVexMap4|NF,
> {
> >>>>>
> >> +Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseInd
> >> ex,
> >>>>> +Reg8|Reg16|Reg32|Reg64 }
> >>>>
> >>>> Didn't we agree to avoid adding this (and its sibling) template,
> >>>> for the omitted shift count being ambiguous? Consider
> >>>>
> >>>>     rol %cl, %al
> >>>>
> >>>> Is this a rotate by %cl, or a 1-bit NDD rotate?
> >>>
> >>> Btw, while this comment was taken into account for the "normal"
> >>> shifts and rotates, SHLD / SHRD still have this odd extra form.
> >>
> >> I have to correct myself here: RCL and RCR had such an odd form
> >> retained, too (as, perhaps, a side effect of prematurely adding the non-NDD
> forms there).
> >>
> >
> > For RCL/RCR, we dropped the format of omitting $1.
> > rcl, 0xd0/2, APX_F,
> W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4,
> > { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> Reg8|Reg16|Reg32|Reg64
> > }
> 
> That's my point: This was supposed to be dropped, but is still there. Only rol/ror
> and the four shifts are where it was properly dropped. The rcl/rcr ones
> disappear in "x86: templatize shift/rotate insns" now.
> 
> > For example, when the register is %rcx, it will conflict with the following
> template.
> >
> > rcl, 0xd2/2, 0, W|Modrm|No_sSuf, { ShiftCount,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >
> > I'm confused if we really want to omit the %cl case. I'll confirm it later.
> 
> I'm confused by this. What are you talking about? Hmm, perhaps there was
> some confusion from me originally saying "had such an odd form retained".
> That wasn't specifically about it being %cl or $1 omitted, but more generally
> about insn forms with no explicit shift count (of whatever shape).
> 

Oh, got it, I dropped the NDD format for them, but promoted the RCL/ROR without explicit shift count. I see you corrected RCL/ROR and SHLD/SHRD in your patches. Thanks.

Lili.