From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: gdb-patches@sourceware.org, Binutils <binutils@sourceware.org>
Subject: Re: [PATCH v2 1/2] opcodes: Add non-enum disassembler options
Date: Tue, 6 Sep 2022 17:31:05 +0900 [thread overview]
Message-ID: <b8c012ce-6293-fe5a-4e5b-bc0678199cdc@irq.a4lg.com> (raw)
In-Reply-To: <70b4912d-99a0-8bb4-60e8-c0239aa23b7a@irq.a4lg.com>
Sorry, because of my misunderstandings, I thought I don't have any write
permission to the GDB part. Because that was not true (according to a
Binutils maintainer), I also pushed PATCH 2/2 myself.
Thanks,
Tsukasa
On 2022/09/06 11:36, Tsukasa OI via Gdb-patches wrote:
> PATCH v2 1/2 is committed as a combination of:
>
> - Changes from PATCH v1 1/2 (that is approved)
> - Obvious copy-editing on the commit message (no code changes)
>
> Under the "write after approval" access to the Binutils project. This
> is my very first commit by myself (as a new committer). Thanks, Nick!
>
> Technically, it's not impossible to push 2/2 myself but this is
> definitely not Binutils and GDB should go. Andrew, if you don't mind,
> could you push the PATCH v2 2/2 for me?
>
> Thanks,
> Tsukasa
>
> On 2022/09/04 17:03, Tsukasa OI wrote:
>> This is paired with "gdb: Add non-enum disassembler options".
>>
>> There is a portable mechanism for disassembler options and used on some
>> architectures:
>>
>> - ARC
>> - Arm
>> - MIPS
>> - PowerPC
>> - RISC-V
>> - S/390
>>
>> However, it only supports following forms:
>>
>> - [NAME]
>> - [NAME]=[ENUM_VALUE]
>>
>> Valid values for [ENUM_VALUE] must be predefined in
>> disasm_option_arg_t.values. For instance, for -M cpu=[CPU] in ARC
>> architecture, opcodes/arc-dis.c builds valid CPU model list from
>> include/elf/arc-cpu.def.
>>
>> In this commit, it adds following format:
>>
>> - [NAME]=[ARBITRARY_VALUE] (cannot contain "," though)
>>
>> This is identified by NULL value of disasm_option_arg_t.values
>> (normally, this is a non-NULL pointer to a NULL-terminated list).
>>
>> include/ChangeLog:
>>
>> * dis-asm.h (disasm_option_arg_t): Update comment of values
>> to allow non-enum disassembler options.
>>
>> opcodes/ChangeLog:
>>
>> * riscv-dis.c (print_riscv_disassembler_options): Support
>> non-enum disassembler options on printing disassembler help.
>> * arc-dis.c (print_arc_disassembler_options): Likewise.
>> * mips-dis.c (print_mips_disassembler_options): Likewise.
>> ---
>> include/dis-asm.h | 3 ++-
>> opcodes/arc-dis.c | 2 ++
>> opcodes/mips-dis.c | 2 ++
>> opcodes/riscv-dis.c | 2 ++
>> 4 files changed, 8 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/dis-asm.h b/include/dis-asm.h
>> index f1a83dc84e5..4921c040710 100644
>> --- a/include/dis-asm.h
>> +++ b/include/dis-asm.h
>> @@ -318,7 +318,8 @@ typedef struct
>> /* Option argument name to use in descriptions. */
>> const char *name;
>>
>> - /* Vector of acceptable option argument values, NULL-terminated. */
>> + /* Vector of acceptable option argument values, NULL-terminated.
>> + NULL if any values are accepted. */
>> const char **values;
>> } disasm_option_arg_t;
>>
>> diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
>> index 3490bad4f66..c8dc525f64d 100644
>> --- a/opcodes/arc-dis.c
>> +++ b/opcodes/arc-dis.c
>> @@ -1611,6 +1611,8 @@ print_arc_disassembler_options (FILE *stream)
>> for (i = 0; args[i].name != NULL; ++i)
>> {
>> size_t len = 3;
>> + if (args[i].values == NULL)
>> + continue;
>> fprintf (stream, _("\n\
>> For the options above, the following values are supported for \"%s\":\n "),
>> args[i].name);
>> diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
>> index 9db604ffb39..faeebccfc3b 100644
>> --- a/opcodes/mips-dis.c
>> +++ b/opcodes/mips-dis.c
>> @@ -2809,6 +2809,8 @@ with the -M switch (multiple options should be separated by commas):\n\n"));
>>
>> for (i = 0; args[i].name != NULL; i++)
>> {
>> + if (args[i].values == NULL)
>> + continue;
>> fprintf (stream, _("\n\
>> For the options above, the following values are supported for \"%s\":\n "),
>> args[i].name);
>> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
>> index 160cc40f865..7ae6e709290 100644
>> --- a/opcodes/riscv-dis.c
>> +++ b/opcodes/riscv-dis.c
>> @@ -1195,6 +1195,8 @@ with the -M switch (multiple options should be separated by commas):\n"));
>>
>> for (i = 0; args[i].name != NULL; i++)
>> {
>> + if (args[i].values == NULL)
>> + continue;
>> fprintf (stream, _("\n\
>> For the options above, the following values are supported for \"%s\":\n "),
>> args[i].name);
>
next prev parent reply other threads:[~2022-09-06 8:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-31 2:15 [PATCH 0/2] gdb, " Tsukasa OI
2022-08-31 2:15 ` [PATCH 1/2] " Tsukasa OI
2022-09-01 12:03 ` Nick Clifton
2022-08-31 2:15 ` [PATCH 2/2] gdb: " Tsukasa OI
2022-09-02 10:00 ` Andrew Burgess
2022-09-04 8:03 ` [PATCH v2 0/2] gdb, opcodes: " Tsukasa OI
2022-09-04 8:03 ` [PATCH v2 1/2] " Tsukasa OI
2022-09-06 2:36 ` Tsukasa OI
2022-09-06 8:31 ` Tsukasa OI [this message]
2022-09-04 8:03 ` [PATCH v2 2/2] gdb: " Tsukasa OI
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