From: Jan Beulich <jbeulich@suse.com>
To: "Cui, Lili" <lili.cui@intel.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Subject: Re: [PATCH 2/3] x86: Drop SwapSources
Date: Fri, 26 Apr 2024 12:37:00 +0200 [thread overview]
Message-ID: <c2d233bb-f9c6-4e29-b6a6-6d650fe5deab@suse.com> (raw)
In-Reply-To: <SJ0PR11MB56005B9657D8E178F91DB7339E162@SJ0PR11MB5600.namprd11.prod.outlook.com>
On 26.04.2024 10:14, Cui, Lili wrote:
>> On 24.04.2024 09:23, Cui, Lili wrote:
>>> --- a/gas/config/tc-i386.c
>>> +++ b/gas/config/tc-i386.c
>>> @@ -10434,6 +10434,14 @@ build_modrm_byte (void)
>>>
>>> switch (i.tm.opcode_modifier.vexvvvv)
>>> {
>>> + case VexVVVV_SRC2:
>>> + if (source != op)
>>> + {
>>> + v = source++;
>>> + break;
>>> + }
>>> + /* For XOP: vpshl* and vpsha*. */
>>> + /* Fall through. */
>>> case VexVVVV_SRC1:
>>
>> This falling-through is odd and hence needs a better comment (then also
>> covering vprot*, which afaict is similarly affected). The reason for this is the
>> XOP.W-controlled operand swapping, if I'm not mistaken? In which case
>> perhaps instead of the fall-through here the logic swapping the operands
>> should replace VexVVVV_SRC2 by VexVVVV_SRC1?
>>
>
> Yes, vprot* should be included, and it is related to XOP.W-controlled operand swapping, the comments says " /* Only the first two register operands need reversing, alongside flipping VEX.W. */ ", But there is actually a memory operand, not two register operands.
>
> I think VexVVVV_SRC2 makes more sense here, it matches the actual situation, we want to use vvvv to encode the first operand.
>
> Opcode table:
> vprot<xop>, 0x90 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexVVVV_Src2|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
>
> testcase:
> vprotb (%rax),%xmm12,%xmm15
> vprotb %xmm15,(%r12),%xmm0
VexVVVV_Src2 is appropriate for the latter, yes, but not for the former. That
uses VexVVVV_Src1 layout. Hence my suggestion to replace the attribute when
swapping operands.
Jan
next prev parent reply other threads:[~2024-04-26 10:37 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-24 7:23 [PATCH 0/3] x86: Optimize the encoder of the vvvv register Cui, Lili
2024-04-24 7:23 ` [PATCH 1/3] x86: Use vexvvvv to encode " Cui, Lili
2024-04-24 7:52 ` Jan Beulich
2024-04-25 13:14 ` Cui, Lili
2024-04-25 13:22 ` Jan Beulich
2024-04-26 5:33 ` Cui, Lili
2024-04-26 6:52 ` Jan Beulich
2024-04-24 7:23 ` [PATCH 2/3] x86: Drop SwapSources Cui, Lili
2024-04-24 8:07 ` Jan Beulich
2024-04-26 8:14 ` Cui, Lili
2024-04-26 10:37 ` Jan Beulich [this message]
2024-04-28 4:47 ` Cui, Lili
2024-04-29 6:40 ` Jan Beulich
2024-04-29 12:23 ` Cui, Lili
2024-04-29 13:08 ` Jan Beulich
2024-04-29 13:41 ` Cui, Lili
2024-04-29 13:49 ` Jan Beulich
2024-04-30 2:56 ` Cui, Lili
2024-04-30 6:18 ` Jan Beulich
2024-04-30 7:34 ` Cui, Lili
2024-04-30 9:22 ` Jan Beulich
2024-04-24 7:23 ` [PATCH 3/3] x86: Drop using extension_opcode to encode vvvv register Cui, Lili
2024-04-24 8:19 ` Jan Beulich
2024-04-24 8:27 ` Jan Beulich
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