[PATCH 0/4] x86: Cpu64 / CpuNo64 adjustments

[PATCH 0/4] x86: Cpu64 / CpuNo64 adjustments

[Jan Beulich]

Various aspects there want tidying. While I don't expect any conflicts /
collisions, if in doubt this goes on top of v2 of the alternative AVX10
series.

1: re-order update_code_flag()
2: make code size vs CPU arch checking consistent
3: don't play with cpu_arch_flags.cpu{,no}64
4: fold CpuLM and Cpu64

Jan

[PATCH 1/4] x86: re-order update_code_flag()

[Jan Beulich]

Do checks before updating state, and bail upon failure of either of the
checks. While moving the code, eliminate some redundancy.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2609,7 +2609,21 @@ add_prefix (unsigned int prefix)
 static void
 update_code_flag (int value, int check)
 {
-  PRINTF_LIKE ((*as_error));
+  PRINTF_LIKE ((*as_error)) = check ? as_fatal : as_bad;
+
+  if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
+    {
+      as_error (_("64bit mode not supported on `%s'."),
+		cpu_arch_name ? cpu_arch_name : default_arch);
+      return;
+    }
+
+  if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
+    {
+      as_error (_("32bit mode not supported on `%s'."),
+		cpu_arch_name ? cpu_arch_name : default_arch);
+      return;
+    }
 
   flag_code = (enum flag_code) value;
   if (flag_code == CODE_64BIT)
@@ -2622,24 +2636,7 @@ update_code_flag (int value, int check)
       cpu_arch_flags.bitfield.cpu64 = 0;
       cpu_arch_flags.bitfield.cpuno64 = 1;
     }
-  if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
-    {
-      if (check)
-	as_error = as_fatal;
-      else
-	as_error = as_bad;
-      (*as_error) (_("64bit mode not supported on `%s'."),
-		   cpu_arch_name ? cpu_arch_name : default_arch);
-    }
-  if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
-    {
-      if (check)
-	as_error = as_fatal;
-      else
-	as_error = as_bad;
-      (*as_error) (_("32bit mode not supported on `%s'."),
-		   cpu_arch_name ? cpu_arch_name : default_arch);
-    }
+
   stackop_size = '\0';
 }
 

[PATCH 2/4] x86: make code size vs CPU arch checking consistent

[Jan Beulich]

While update_code_flag() checks for LM / i386, set_cpu_arch() so far
didn't, allowing e.g. 64-bit code to be emitted after ".arch generic32".

Oddly enough a few of our testcases actually exhibit bad behavior (and
hence need minor adjustments).

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2928,6 +2928,24 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED
 	    {
 	      check_cpu_arch_compatible (string, cpu_arch[j].enable);
 
+	      if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpulm )
+		{
+		  as_bad (_("64bit mode not supported on `%s'."),
+			  cpu_arch[j].name);
+		  (void) restore_line_pointer (e);
+		  ignore_rest_of_line ();
+		  return;
+		}
+
+	      if (flag_code == CODE_32BIT && !cpu_arch[j].enable.bitfield.cpui386)
+		{
+		  as_bad (_("32bit mode not supported on `%s'."),
+			  cpu_arch[j].name);
+		  (void) restore_line_pointer (e);
+		  ignore_rest_of_line ();
+		  return;
+		}
+
 	      cpu_arch_name = cpu_arch[j].name;
 	      free (cpu_sub_arch_name);
 	      cpu_sub_arch_name = NULL;
--- a/gas/testsuite/gas/i386/287.s
+++ b/gas/testsuite/gas/i386/287.s
@@ -1,9 +1,9 @@
 # Check 287-only instructions.
 
 	.text
+	.code16
 	.arch i286
 	.arch .287
-	.code16
 _8087:
 	fnsetpm
 	frstpm
--- a/gas/testsuite/gas/i386/8087.s
+++ b/gas/testsuite/gas/i386/8087.s
@@ -1,9 +1,9 @@
 # Check 8087-only instructions.
 
 	.text
+	.code16
 	.arch i8086
 	.arch .8087
-	.code16
 _8087:
 	fdisi
 	feni
--- a/gas/testsuite/gas/i386/att-regs.s
+++ b/gas/testsuite/gas/i386/att-regs.s
@@ -1,8 +1,8 @@
 	.text
 	.att_syntax noprefix
 
-	.arch i286
 	.code16
+	.arch i286
 	mov	eax, ax			; add	al, (bx,si)
 	mov	rax, ax			; add	al, (bx,si)
 	mov	axl, ax			; add	al, (bx,si)
--- a/gas/testsuite/gas/i386/intel-regs.s
+++ b/gas/testsuite/gas/i386/intel-regs.s
@@ -3,8 +3,8 @@
 
 	mov	eax, tmm1
 
-	.arch i286
 	.code16
+	.arch i286
 	mov	ax, eax			; add	[bx+si], al
 	mov	ax, rax			; add	[bx+si], al
 	mov	ax, axl			; add	[bx+si], al
--- a/gas/testsuite/gas/i386/inval-16.l
+++ b/gas/testsuite/gas/i386/inval-16.l
@@ -10,7 +10,7 @@ GAS LISTING .*
 
 
 [ 	]*1[ 	]+\.text
-[ 	]*2[ 	]+\.arch i186; \.code16
+[ 	]*2[ 	]+\.code16; \.arch i186
 [ 	]*3[ 	]+vmovapd	%xmm0,%xmm1
 [ 	]*4[ 	]+vaddsd	%xmm4, %xmm5, %xmm6\{%k7\}
 [ 	]*5[ 	]+vfrczpd	%xmm7,%xmm7
--- a/gas/testsuite/gas/i386/inval-16.s
+++ b/gas/testsuite/gas/i386/inval-16.s
@@ -1,5 +1,5 @@
 	.text
-	.arch i186; .code16
+	.code16; .arch i186
 	vmovapd	%xmm0,%xmm1
 	vaddsd	%xmm4, %xmm5, %xmm6{%k7}
 	vfrczpd	%xmm7,%xmm7
--- a/gas/testsuite/gas/i386/nops-5.s
+++ b/gas/testsuite/gas/i386/nops-5.s
@@ -1,4 +1,5 @@
 	.text
+	.code32
 	.arch i386
 i386:
 	movsbl %al,%esi

[PATCH 3/4] x86: don't play with cpu_arch_flags.cpu{,no}64

[Jan Beulich]

A total four places exists where we set the two bits from flag_code, but
these values are never used. The two bits are evaluated only when coming
from insn templates.

Drop these assignments. Also make obvious that cpu_flags_check_cpu64()
is only ever used against insn templates.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1785,10 +1785,11 @@ cpu_flags_equal (const union i386_cpu_fl
 }
 
 static INLINE int
-cpu_flags_check_cpu64 (i386_cpu_attr a)
+cpu_flags_check_cpu64 (const insn_template *t)
 {
-  return !((flag_code == CODE_64BIT && a.bitfield.cpuno64)
-	   || (flag_code != CODE_64BIT && a.bitfield.cpu64));
+  return flag_code == CODE_64BIT
+	 ? !t->cpu.bitfield.cpuno64
+	 : !t->cpu.bitfield.cpu64;
 }
 
 static INLINE i386_cpu_flags
@@ -1883,7 +1884,7 @@ static int
 cpu_flags_match (const insn_template *t)
 {
   i386_cpu_flags x = cpu_flags_from_attr (t->cpu);
-  int match = cpu_flags_check_cpu64 (t->cpu) ? CPU_FLAGS_64BIT_MATCH : 0;
+  int match = cpu_flags_check_cpu64 (t) ? CPU_FLAGS_64BIT_MATCH : 0;
 
   x.bitfield.cpu64 = 0;
   x.bitfield.cpuno64 = 0;
@@ -2626,16 +2627,6 @@ update_code_flag (int value, int check)
     }
 
   flag_code = (enum flag_code) value;
-  if (flag_code == CODE_64BIT)
-    {
-      cpu_arch_flags.bitfield.cpu64 = 1;
-      cpu_arch_flags.bitfield.cpuno64 = 0;
-    }
-  else
-    {
-      cpu_arch_flags.bitfield.cpu64 = 0;
-      cpu_arch_flags.bitfield.cpuno64 = 1;
-    }
 
   stackop_size = '\0';
 }
@@ -2652,8 +2643,6 @@ set_16bit_gcc_code_flag (int new_code_fl
   flag_code = (enum flag_code) new_code_flag;
   if (flag_code != CODE_16BIT)
     abort ();
-  cpu_arch_flags.bitfield.cpu64 = 0;
-  cpu_arch_flags.bitfield.cpuno64 = 1;
   stackop_size = LONG_MNEM_SUFFIX;
 }
 
@@ -2895,16 +2884,6 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED
 	  free (cpu_sub_arch_name);
 	  cpu_sub_arch_name = NULL;
 	  cpu_arch_flags = cpu_unknown_flags;
-	  if (flag_code == CODE_64BIT)
-	    {
-	      cpu_arch_flags.bitfield.cpu64 = 1;
-	      cpu_arch_flags.bitfield.cpuno64 = 0;
-	    }
-	  else
-	    {
-	      cpu_arch_flags.bitfield.cpu64 = 0;
-	      cpu_arch_flags.bitfield.cpuno64 = 1;
-	    }
 	  cpu_arch_isa = PROCESSOR_UNKNOWN;
 	  cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable;
 	  if (!cpu_arch_tune_set)
@@ -2950,16 +2929,6 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED
 	      free (cpu_sub_arch_name);
 	      cpu_sub_arch_name = NULL;
 	      cpu_arch_flags = cpu_arch[j].enable;
-	      if (flag_code == CODE_64BIT)
-		{
-		  cpu_arch_flags.bitfield.cpu64 = 1;
-		  cpu_arch_flags.bitfield.cpuno64 = 0;
-		}
-	      else
-		{
-		  cpu_arch_flags.bitfield.cpu64 = 0;
-		  cpu_arch_flags.bitfield.cpuno64 = 1;
-		}
 	      cpu_arch_isa = cpu_arch[j].type;
 	      cpu_arch_isa_flags = cpu_arch[j].enable;
 	      if (!cpu_arch_tune_set)
@@ -5741,7 +5710,7 @@ parse_insn (const char *line, char *mnem
 	  && current_templates
 	  && current_templates->start->opcode_modifier.isprefix)
 	{
-	  if (!cpu_flags_check_cpu64 (current_templates->start->cpu))
+	  if (!cpu_flags_check_cpu64 (current_templates->start))
 	    {
 	      as_bad ((flag_code != CODE_64BIT
 		       ? _("`%s' is only supported in 64-bit mode")

[PATCH 4/4] x86: fold CpuLM and Cpu64

[Jan Beulich]

Now that CpuLM is used solely in cpu_arch_flags and cpu_arch[] while
Cpu64 is solely used in insn templates, they no longer need to be
treated different from other "ordinary" flags; the only "unusual" one
left if CpuNo64. Fold both, leaving just Cpu64.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2612,7 +2612,7 @@ update_code_flag (int value, int check)
 {
   PRINTF_LIKE ((*as_error)) = check ? as_fatal : as_bad;
 
-  if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
+  if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpu64 )
     {
       as_error (_("64bit mode not supported on `%s'."),
 		cpu_arch_name ? cpu_arch_name : default_arch);
@@ -2907,7 +2907,7 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED
 	    {
 	      check_cpu_arch_compatible (string, cpu_arch[j].enable);
 
-	      if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpulm )
+	      if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpu64 )
 		{
 		  as_bad (_("64bit mode not supported on `%s'."),
 			  cpu_arch[j].name);
@@ -13986,7 +13986,7 @@ static bool check_register (const reg_en
     }
 
   if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
-      && (!cpu_arch_flags.bitfield.cpulm
+      && (!cpu_arch_flags.bitfield.cpu64
 	  || r->reg_type.bitfield.class != RegCR
 	  || dot_insn ())
       && flag_code != CODE_64BIT)
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -262,7 +262,7 @@ static const dependency isa_dependencies
 };
 
 /* This array is populated as process_i386_initializers() walks cpu_flags[].  */
-static unsigned char isa_reverse_deps[Cpu64][Cpu64];
+static unsigned char isa_reverse_deps[CpuMax][CpuMax];
 
 typedef struct bitfield
 {
@@ -325,7 +325,6 @@ static bitfield cpu_flags[] =
   BITFIELD (LWP),
   BITFIELD (BMI),
   BITFIELD (TBM),
-  BITFIELD (LM),
   BITFIELD (Movbe),
   BITFIELD (CX16),
   BITFIELD (LAHF_SAHF),
@@ -726,7 +725,10 @@ add_isa_dependencies (bitfield *flags, c
       *strchr (str, ':') = '\0';
       isa = str;
     }
-  for (i = 0; i < Cpu64; ++i)
+  /* isa_dependencies[] prefers "LM" over "64".  */
+  else if (!strcmp (f, "LM"))
+    isa = "64";
+  for (i = 0; i < CpuMax; ++i)
     if (strcasecmp (flags[i].name, isa) == 0)
       {
 	flags[i].value = value;
@@ -872,10 +874,10 @@ process_i386_cpu_flag (FILE *table, char
       else
 	next = flag + 1;
 
-      /* First we turn on everything except for cpu64, cpuno64, and - if
+      /* First we turn on everything except for cpuno64 and - if
          present - the padding field.  */
       for (i = 0; i < ARRAY_SIZE (flags); i++)
-	if (flags[i].position < Cpu64)
+	if (flags[i].position < CpuNo64)
 	  flags[i].value = 1;
 
       /* Turn off selective bits.  */
@@ -1968,7 +1970,7 @@ process_i386_initializers (void)
 
   process_copyright (fp);
 
-  for (i = 0; i < Cpu64; i++)
+  for (i = 0; i < CpuMax; i++)
     process_i386_cpu_flag (fp, "0", cpu_flags[i].name, "", "  ", -1, i);
 
   for (i = 0; i < ARRAY_SIZE (isa_dependencies); i++)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -147,8 +147,6 @@ enum i386_cpu
   CpuVMFUNC,
   /* Intel MPX Instructions required  */
   CpuMPX,
-  /* 64bit support available, used by -march= in assembler.  */
-  CpuLM,
   /* RDRSEED instruction required.  */
   CpuRDSEED,
   /* Multi-presisionn add-carry instructions are required.  */
@@ -309,6 +307,8 @@ enum i386_cpu
   Cpu3dnow,
   /* 3dnow! Extensions support required */
   Cpu3dnowA,
+  /* 64bit support required  */
+  Cpu64,
   /* AVX support required */
   CpuAVX,
   /* HLE support required */
@@ -317,8 +317,6 @@ enum i386_cpu
   CpuAVX512F,
   /* Intel AVX-512 VL Instructions support required.  */
   CpuAVX512VL,
-  /* 64bit support required  */
-  Cpu64,
   /* Not supported in the 64bit mode  */
   CpuNo64,
 
@@ -349,12 +347,12 @@ enum i386_cpu
 		   cpu387:1, \
 		   cpu3dnow:1, \
 		   cpu3dnowa:1, \
+		   cpu64:1, \
 		   cpuavx:1, \
 		   cpuhle:1, \
 		   cpuavx512f:1, \
 		   cpuavx512vl:1, \
-      /* NOTE: These two fields need to remain last and in this order. */ \
-		   cpu64:1, \
+      /* NOTE: This field needs to remain last. */ \
 		   cpuno64:1
 
 typedef union i386_cpu_attr
@@ -435,7 +433,6 @@ typedef union i386_cpu_flags
       unsigned int cpuinvpcid:1;
       unsigned int cpuvmfunc:1;
       unsigned int cpumpx:1;
-      unsigned int cpulm:1;
       unsigned int cpurdseed:1;
       unsigned int cpuadx:1;
       unsigned int cpuprfchw:1;