public inbox for binutils@sourceware.org
 help / color / mirror / Atom feed
* [REVIEW ONLY 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension
@ 2022-11-29  1:16 Tsukasa OI
  2022-11-29  1:16 ` [REVIEW ONLY 1/1] " Tsukasa OI
  2022-11-29  2:06 ` [REVIEW ONLY v2 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension (encodings changed!) Tsukasa OI
  0 siblings, 2 replies; 10+ messages in thread
From: Tsukasa OI @ 2022-11-29  1:16 UTC (permalink / raw)
  To: Tsukasa OI; +Cc: binutils

*** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and not frozen RISC-V extension
and not intended to be merged for now.
The only intent to submit this patchset is to test new instructions for
your (possibly virtual) environment and early review for fast adoption
after ratification.


This patchset adds following unratified extension to GNU Binutils:

-   'ZiCondOps' (Integer Conditional Operations)
    version 1.0 in development

which adds 2 instructions ("czero.eqz" and "czero.nez").

This extension makes conditional arithmetic feature much simpler (fewer
instructions when no branches are allowed).  Note that constant timing
guarantee (data-independence / certain side-channel resistance) for this
extension is being discussed and may not be guaranteed.


This is based on the commit 91e173db8678 of the specification document:
<https://github.com/riscv/riscv-zicondops>




Tsukasa OI (1):
  UNRATIFIED RISC-V: Add 'ZiCondOps' extension

 bfd/elfxx-riscv.c                          |  5 +++++
 gas/testsuite/gas/riscv/zicondops-noarch.d |  3 +++
 gas/testsuite/gas/riscv/zicondops-noarch.l |  3 +++
 gas/testsuite/gas/riscv/zicondops.d        | 11 +++++++++++
 gas/testsuite/gas/riscv/zicondops.s        |  3 +++
 include/opcode/riscv-opc.h                 |  8 ++++++++
 include/opcode/riscv.h                     |  1 +
 opcodes/riscv-opc.c                        |  4 ++++
 8 files changed, 38 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.d
 create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.l
 create mode 100644 gas/testsuite/gas/riscv/zicondops.d
 create mode 100644 gas/testsuite/gas/riscv/zicondops.s


base-commit: cb44f89ce977b1ab2d4063f2487950bddfb75bc7
-- 
2.38.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
* [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension
  2022-11-29  1:16 [REVIEW ONLY 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension Tsukasa OI
@ 2022-11-29  1:16 ` Tsukasa OI
  2022-11-29  1:41   ` Palmer Dabbelt
  2022-11-29  2:06 ` [REVIEW ONLY v2 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension (encodings changed!) Tsukasa OI
  1 sibling, 1 reply; 10+ messages in thread
From: Tsukasa OI @ 2022-11-29  1:16 UTC (permalink / raw)
  To: Tsukasa OI; +Cc: binutils

From: Tsukasa OI <research_trasio@irq.a4lg.com>

[DO NOT MERGE]
Until 'ZiCondOps' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream.  This commit uses
version 1.0 as in the documentation.

This commit adds support for the latest draft of RISC-V Integer Conditional
Operations (ZiCondOps) extension consisting of 2 new instructions.

This is based on the early draft of ZiCondOps on GitHub:
<https://github.com/riscv/riscv-zicondops/commit/91e173db867875a6e0ab21c89d146f1a28f416e3>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'ZiCondOps'.
	(riscv_multi_subset_supports): Support new instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zicondops.s: New test for 'ZiCondOps'.
	* testsuite/gas/riscv/zicondops.d: Likewise.
	* testsuite/gas/riscv/zicondops-noarch.d: New test for
	architecture failure.
	* testsuite/gas/riscv/zicondops-noarch.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_CZERO_EQZ, MASK_CZERO_EQZ,
	MATCH_CZERO_NEZ, MASK_CZERO_NEZ): New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	class INSN_CLASS_ZICONDOPS.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add new instructions from the
	'ZiCondOps' extension.
---
 bfd/elfxx-riscv.c                          |  5 +++++
 gas/testsuite/gas/riscv/zicondops-noarch.d |  3 +++
 gas/testsuite/gas/riscv/zicondops-noarch.l |  3 +++
 gas/testsuite/gas/riscv/zicondops.d        | 11 +++++++++++
 gas/testsuite/gas/riscv/zicondops.s        |  3 +++
 include/opcode/riscv-opc.h                 |  8 ++++++++
 include/opcode/riscv.h                     |  1 +
 opcodes/riscv-opc.c                        |  4 ++++
 8 files changed, 38 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.d
 create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.l
 create mode 100644 gas/testsuite/gas/riscv/zicondops.d
 create mode 100644 gas/testsuite/gas/riscv/zicondops.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0bcf2fdcfa34..564fef205d01 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1168,6 +1168,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zicbom",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicbop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicboz",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zicondops",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zifencei",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
@@ -2318,6 +2319,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zicbop");
     case INSN_CLASS_ZICBOZ:
       return riscv_subset_supports (rps, "zicboz");
+    case INSN_CLASS_ZICONDOPS:
+      return riscv_subset_supports (rps, "zicondops");
     case INSN_CLASS_ZICSR:
       return riscv_subset_supports (rps, "zicsr");
     case INSN_CLASS_ZIFENCEI:
@@ -2467,6 +2470,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zicbop";
     case INSN_CLASS_ZICBOZ:
       return "zicboz";
+    case INSN_CLASS_ZICONDOPS:
+      return "zicondops";
     case INSN_CLASS_ZICSR:
       return "zicsr";
     case INSN_CLASS_ZIFENCEI:
diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.d b/gas/testsuite/gas/riscv/zicondops-noarch.d
new file mode 100644
index 000000000000..4f01b10f42df
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicondops-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: zicondops.s
+#error_output: zicondops-noarch.l
diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.l b/gas/testsuite/gas/riscv/zicondops-noarch.l
new file mode 100644
index 000000000000..b665d6022b98
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicondops-noarch.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `czero\.eqz a0,a1,a2', extension `zicondops' required
+.*: Error: unrecognized opcode `czero\.nez a3,a4,a5', extension `zicondops' required
diff --git a/gas/testsuite/gas/riscv/zicondops.d b/gas/testsuite/gas/riscv/zicondops.d
new file mode 100644
index 000000000000..9f417fa3b5ea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicondops.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_zicondops
+#source: zicondops.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+80c5a533[ 	]+czero\.eqz[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+80f736b3[ 	]+czero\.nez[ 	]+a3,a4,a5
diff --git a/gas/testsuite/gas/riscv/zicondops.s b/gas/testsuite/gas/riscv/zicondops.s
new file mode 100644
index 000000000000..dcf3d98ccd7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicondops.s
@@ -0,0 +1,3 @@
+target:
+	czero.eqz	a0, a1, a2
+	czero.nez	a3, a4, a5
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 06e3df0f5a63..ea38df13ce6d 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2113,6 +2113,11 @@
 #define MASK_CBO_INVAL 0xfff07fff
 #define MATCH_CBO_ZERO 0x40200f
 #define MASK_CBO_ZERO 0xfff07fff
+/* ZiCondOps instructions.  */
+#define MATCH_CZERO_EQZ 0x80002033
+#define MASK_CZERO_EQZ 0xfe00707f
+#define MATCH_CZERO_NEZ 0x80003033
+#define MASK_CZERO_NEZ 0xfe00707f
 /* Zawrs intructions.  */
 #define MATCH_WRS_NTO 0x00d00073
 #define MASK_WRS_NTO 0xffffffff
@@ -3115,6 +3120,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
 DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
 DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
 DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
+/* ZiCondOps instructions.  */
+DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
+DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
 /* Zawrs instructions.  */
 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index c3cbde600cb0..c482f6f4d9f2 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -375,6 +375,7 @@ enum riscv_insn_class
   INSN_CLASS_Q,
   INSN_CLASS_F_AND_C,
   INSN_CLASS_D_AND_C,
+  INSN_CLASS_ZICONDOPS,
   INSN_CLASS_ZICSR,
   INSN_CLASS_ZIFENCEI,
   INSN_CLASS_ZIHINTPAUSE,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0e691544f9bc..311df46daa2d 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -935,6 +935,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"cbo.inval",  0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
 {"cbo.zero",   0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
 
+/* ZiCondOps instructions. */
+{"czero.eqz",  0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 },
+{"czero.nez",  0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 },
+
 /* Zawrs instructions.  */
 {"wrs.nto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
 {"wrs.sto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },
-- 
2.38.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension
  2022-11-29  1:16 ` [REVIEW ONLY 1/1] " Tsukasa OI
@ 2022-11-29  1:41   ` Palmer Dabbelt
  2022-11-29  2:19     ` Tsukasa OI
  0 siblings, 1 reply; 10+ messages in thread
From: Palmer Dabbelt @ 2022-11-29  1:41 UTC (permalink / raw)
  To: binutils; +Cc: research_trasio, binutils

On Mon, 28 Nov 2022 17:16:56 PST (-0800), binutils@sourceware.org wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> [DO NOT MERGE]
> Until 'ZiCondOps' extension is frozen/ratified and final version number is
> determined, this patch should not be merged upstream.  This commit uses
> version 1.0 as in the documentation.
>
> This commit adds support for the latest draft of RISC-V Integer Conditional
> Operations (ZiCondOps) extension consisting of 2 new instructions.
>
> This is based on the early draft of ZiCondOps on GitHub:
> <https://github.com/riscv/riscv-zicondops/commit/91e173db867875a6e0ab21c89d146f1a28f416e3>
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'ZiCondOps'.
> 	(riscv_multi_subset_supports): Support new instruction class.
> 	(riscv_multi_subset_supports_ext): Likewise.
>
> gas/ChangeLog:
>
> 	* testsuite/gas/riscv/zicondops.s: New test for 'ZiCondOps'.
> 	* testsuite/gas/riscv/zicondops.d: Likewise.
> 	* testsuite/gas/riscv/zicondops-noarch.d: New test for
> 	architecture failure.
> 	* testsuite/gas/riscv/zicondops-noarch.l: Likewise.
>
> include/ChangeLog:
>
> 	* opcode/riscv-opc.h (MATCH_CZERO_EQZ, MASK_CZERO_EQZ,
> 	MATCH_CZERO_NEZ, MASK_CZERO_NEZ): New.
> 	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
> 	class INSN_CLASS_ZICONDOPS.
>
> opcodes/ChangeLog:
>
> 	* riscv-opc.c (riscv_opcodes): Add new instructions from the
> 	'ZiCondOps' extension.
> ---
>  bfd/elfxx-riscv.c                          |  5 +++++
>  gas/testsuite/gas/riscv/zicondops-noarch.d |  3 +++
>  gas/testsuite/gas/riscv/zicondops-noarch.l |  3 +++
>  gas/testsuite/gas/riscv/zicondops.d        | 11 +++++++++++
>  gas/testsuite/gas/riscv/zicondops.s        |  3 +++
>  include/opcode/riscv-opc.h                 |  8 ++++++++
>  include/opcode/riscv.h                     |  1 +
>  opcodes/riscv-opc.c                        |  4 ++++
>  8 files changed, 38 insertions(+)
>  create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.d
>  create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.l
>  create mode 100644 gas/testsuite/gas/riscv/zicondops.d
>  create mode 100644 gas/testsuite/gas/riscv/zicondops.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 0bcf2fdcfa34..564fef205d01 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1168,6 +1168,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
>    {"zicbom",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
>    {"zicbop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
>    {"zicboz",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
> +  {"zicondops",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
>    {"zicsr",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
>    {"zicsr",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
>    {"zifencei",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
> @@ -2318,6 +2319,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
>        return riscv_subset_supports (rps, "zicbop");
>      case INSN_CLASS_ZICBOZ:
>        return riscv_subset_supports (rps, "zicboz");
> +    case INSN_CLASS_ZICONDOPS:
> +      return riscv_subset_supports (rps, "zicondops");
>      case INSN_CLASS_ZICSR:
>        return riscv_subset_supports (rps, "zicsr");
>      case INSN_CLASS_ZIFENCEI:
> @@ -2467,6 +2470,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
>        return "zicbop";
>      case INSN_CLASS_ZICBOZ:
>        return "zicboz";
> +    case INSN_CLASS_ZICONDOPS:
> +      return "zicondops";
>      case INSN_CLASS_ZICSR:
>        return "zicsr";
>      case INSN_CLASS_ZIFENCEI:
> diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.d b/gas/testsuite/gas/riscv/zicondops-noarch.d
> new file mode 100644
> index 000000000000..4f01b10f42df
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicondops-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i
> +#source: zicondops.s
> +#error_output: zicondops-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.l b/gas/testsuite/gas/riscv/zicondops-noarch.l
> new file mode 100644
> index 000000000000..b665d6022b98
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicondops-noarch.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `czero\.eqz a0,a1,a2', extension `zicondops' required
> +.*: Error: unrecognized opcode `czero\.nez a3,a4,a5', extension `zicondops' required
> diff --git a/gas/testsuite/gas/riscv/zicondops.d b/gas/testsuite/gas/riscv/zicondops.d
> new file mode 100644
> index 000000000000..9f417fa3b5ea
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicondops.d
> @@ -0,0 +1,11 @@
> +#as: -march=rv32i_zicondops
> +#source: zicondops.s
> +#objdump: -d
> +
> +.*:[ 	]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ 	]+[0-9a-f]+:[ 	]+80c5a533[ 	]+czero\.eqz[ 	]+a0,a1,a2
> +[ 	]+[0-9a-f]+:[ 	]+80f736b3[ 	]+czero\.nez[ 	]+a3,a4,a5
> diff --git a/gas/testsuite/gas/riscv/zicondops.s b/gas/testsuite/gas/riscv/zicondops.s
> new file mode 100644
> index 000000000000..dcf3d98ccd7e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicondops.s
> @@ -0,0 +1,3 @@
> +target:
> +	czero.eqz	a0, a1, a2
> +	czero.nez	a3, a4, a5
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 06e3df0f5a63..ea38df13ce6d 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2113,6 +2113,11 @@
>  #define MASK_CBO_INVAL 0xfff07fff
>  #define MATCH_CBO_ZERO 0x40200f
>  #define MASK_CBO_ZERO 0xfff07fff
> +/* ZiCondOps instructions.  */
> +#define MATCH_CZERO_EQZ 0x80002033
> +#define MASK_CZERO_EQZ 0xfe00707f
> +#define MATCH_CZERO_NEZ 0x80003033
> +#define MASK_CZERO_NEZ 0xfe00707f
>  /* Zawrs intructions.  */
>  #define MATCH_WRS_NTO 0x00d00073
>  #define MASK_WRS_NTO 0xffffffff
> @@ -3115,6 +3120,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
>  DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
>  DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
>  DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
> +/* ZiCondOps instructions.  */
> +DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
> +DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
>  /* Zawrs instructions.  */
>  DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
>  DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index c3cbde600cb0..c482f6f4d9f2 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -375,6 +375,7 @@ enum riscv_insn_class
>    INSN_CLASS_Q,
>    INSN_CLASS_F_AND_C,
>    INSN_CLASS_D_AND_C,
> +  INSN_CLASS_ZICONDOPS,
>    INSN_CLASS_ZICSR,
>    INSN_CLASS_ZIFENCEI,
>    INSN_CLASS_ZIHINTPAUSE,
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 0e691544f9bc..311df46daa2d 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -935,6 +935,10 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"cbo.inval",  0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
>  {"cbo.zero",   0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
>
> +/* ZiCondOps instructions. */
> +{"czero.eqz",  0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 },
> +{"czero.nez",  0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 },
> +
>  /* Zawrs instructions.  */
>  {"wrs.nto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
>  {"wrs.sto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> # pending freeze

Thanks!

^ permalink raw reply	[flat|nested] 10+ messages in thread
* [REVIEW ONLY v2 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension (encodings changed!)
  2022-11-29  1:16 [REVIEW ONLY 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension Tsukasa OI
  2022-11-29  1:16 ` [REVIEW ONLY 1/1] " Tsukasa OI
@ 2022-11-29  2:06 ` Tsukasa OI
  2022-11-29  2:06   ` [REVIEW ONLY v2 1/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension Tsukasa OI
                     ` (2 more replies)
  1 sibling, 3 replies; 10+ messages in thread
From: Tsukasa OI @ 2022-11-29  2:06 UTC (permalink / raw)
  To: Tsukasa OI; +Cc: binutils

*** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and not frozen RISC-V extension
and not intended to be merged for now.
The only intent to submit this patchset is to test new instructions for
your (possibly virtual) environment and early review for fast adoption
after ratification.


Just two hours ago, the encodings of "czero.eqz" and "czero.nez"
instructions have changed in the commit 8c5faf4c6d73.

This PATCH v2 reflects this change.


This patchset adds following unratified extension to GNU Binutils:

-   'ZiCondOps' (Integer Conditional Operations)
    version 1.0 in development

which adds 2 instructions ("czero.eqz" and "czero.nez").

This extension makes conditional arithmetic feature much simpler (fewer
instructions when no branches are allowed).  Note that constant timing
guarantee (data-independence / certain side-channel resistance) for this
extension is being discussed and may not be guaranteed.


This is based on the commit 8c5faf4c6d73 of the specification document:
<https://github.com/riscv/riscv-zicondops>




Tsukasa OI (1):
  UNRATIFIED RISC-V: Add 'ZiCondOps' extension

 bfd/elfxx-riscv.c                          |  5 +++++
 gas/testsuite/gas/riscv/zicondops-noarch.d |  3 +++
 gas/testsuite/gas/riscv/zicondops-noarch.l |  3 +++
 gas/testsuite/gas/riscv/zicondops.d        | 11 +++++++++++
 gas/testsuite/gas/riscv/zicondops.s        |  3 +++
 include/opcode/riscv-opc.h                 |  8 ++++++++
 include/opcode/riscv.h                     |  1 +
 opcodes/riscv-opc.c                        |  4 ++++
 8 files changed, 38 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.d
 create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.l
 create mode 100644 gas/testsuite/gas/riscv/zicondops.d
 create mode 100644 gas/testsuite/gas/riscv/zicondops.s


base-commit: cb44f89ce977b1ab2d4063f2487950bddfb75bc7
-- 
2.38.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
* [REVIEW ONLY v2 1/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension
  2022-11-29  2:06 ` [REVIEW ONLY v2 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension (encodings changed!) Tsukasa OI
@ 2022-11-29  2:06   ` Tsukasa OI
  2022-11-29  2:40   ` [REVIEW ONLY v2 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension (encodings changed!) Tsukasa OI
  2022-12-01  3:20   ` [REVIEW ONLY v3 0/1] UNRATIFIED RISC-V: Add 'ZiCond' extension Tsukasa OI
  2 siblings, 0 replies; 10+ messages in thread
From: Tsukasa OI @ 2022-11-29  2:06 UTC (permalink / raw)
  To: Tsukasa OI; +Cc: binutils

From: Tsukasa OI <research_trasio@irq.a4lg.com>

[DO NOT MERGE]
Until 'ZiCondOps' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream.  This commit uses
version 1.0 as in the documentation.

This commit adds support for the latest draft of RISC-V Integer Conditional
Operations (ZiCondOps) extension consisting of 2 new instructions.

This is based on the early draft of ZiCondOps on GitHub:
<https://github.com/riscv/riscv-zicondops/commit/8c5faf4c6d73194add38c743b1ee97cf73227868>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'ZiCondOps'.
	(riscv_multi_subset_supports): Support new instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zicondops.s: New test for 'ZiCondOps'.
	* testsuite/gas/riscv/zicondops.d: Likewise.
	* testsuite/gas/riscv/zicondops-noarch.d: New test for
	architecture failure.
	* testsuite/gas/riscv/zicondops-noarch.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_CZERO_EQZ, MASK_CZERO_EQZ,
	MATCH_CZERO_NEZ, MASK_CZERO_NEZ): New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	class INSN_CLASS_ZICONDOPS.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add new instructions from the
	'ZiCondOps' extension.
---
 bfd/elfxx-riscv.c                          |  5 +++++
 gas/testsuite/gas/riscv/zicondops-noarch.d |  3 +++
 gas/testsuite/gas/riscv/zicondops-noarch.l |  3 +++
 gas/testsuite/gas/riscv/zicondops.d        | 11 +++++++++++
 gas/testsuite/gas/riscv/zicondops.s        |  3 +++
 include/opcode/riscv-opc.h                 |  8 ++++++++
 include/opcode/riscv.h                     |  1 +
 opcodes/riscv-opc.c                        |  4 ++++
 8 files changed, 38 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.d
 create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.l
 create mode 100644 gas/testsuite/gas/riscv/zicondops.d
 create mode 100644 gas/testsuite/gas/riscv/zicondops.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0bcf2fdcfa34..564fef205d01 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1168,6 +1168,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zicbom",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicbop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicboz",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zicondops",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zifencei",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
@@ -2318,6 +2319,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zicbop");
     case INSN_CLASS_ZICBOZ:
       return riscv_subset_supports (rps, "zicboz");
+    case INSN_CLASS_ZICONDOPS:
+      return riscv_subset_supports (rps, "zicondops");
     case INSN_CLASS_ZICSR:
       return riscv_subset_supports (rps, "zicsr");
     case INSN_CLASS_ZIFENCEI:
@@ -2467,6 +2470,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zicbop";
     case INSN_CLASS_ZICBOZ:
       return "zicboz";
+    case INSN_CLASS_ZICONDOPS:
+      return "zicondops";
     case INSN_CLASS_ZICSR:
       return "zicsr";
     case INSN_CLASS_ZIFENCEI:
diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.d b/gas/testsuite/gas/riscv/zicondops-noarch.d
new file mode 100644
index 000000000000..4f01b10f42df
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicondops-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: zicondops.s
+#error_output: zicondops-noarch.l
diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.l b/gas/testsuite/gas/riscv/zicondops-noarch.l
new file mode 100644
index 000000000000..b665d6022b98
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicondops-noarch.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `czero\.eqz a0,a1,a2', extension `zicondops' required
+.*: Error: unrecognized opcode `czero\.nez a3,a4,a5', extension `zicondops' required
diff --git a/gas/testsuite/gas/riscv/zicondops.d b/gas/testsuite/gas/riscv/zicondops.d
new file mode 100644
index 000000000000..16feba95c4d3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicondops.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_zicondops
+#source: zicondops.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+06c5d533[ 	]+czero\.eqz[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+06f776b3[ 	]+czero\.nez[ 	]+a3,a4,a5
diff --git a/gas/testsuite/gas/riscv/zicondops.s b/gas/testsuite/gas/riscv/zicondops.s
new file mode 100644
index 000000000000..dcf3d98ccd7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicondops.s
@@ -0,0 +1,3 @@
+target:
+	czero.eqz	a0, a1, a2
+	czero.nez	a3, a4, a5
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 06e3df0f5a63..0115539931fe 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2113,6 +2113,11 @@
 #define MASK_CBO_INVAL 0xfff07fff
 #define MATCH_CBO_ZERO 0x40200f
 #define MASK_CBO_ZERO 0xfff07fff
+/* ZiCondOps instructions.  */
+#define MATCH_CZERO_EQZ 0x6005033
+#define MASK_CZERO_EQZ 0xfe00707f
+#define MATCH_CZERO_NEZ 0x6007033
+#define MASK_CZERO_NEZ 0xfe00707f
 /* Zawrs intructions.  */
 #define MATCH_WRS_NTO 0x00d00073
 #define MASK_WRS_NTO 0xffffffff
@@ -3115,6 +3120,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
 DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
 DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
 DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
+/* ZiCondOps instructions.  */
+DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
+DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
 /* Zawrs instructions.  */
 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index c3cbde600cb0..c482f6f4d9f2 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -375,6 +375,7 @@ enum riscv_insn_class
   INSN_CLASS_Q,
   INSN_CLASS_F_AND_C,
   INSN_CLASS_D_AND_C,
+  INSN_CLASS_ZICONDOPS,
   INSN_CLASS_ZICSR,
   INSN_CLASS_ZIFENCEI,
   INSN_CLASS_ZIHINTPAUSE,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0e691544f9bc..311df46daa2d 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -935,6 +935,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"cbo.inval",  0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
 {"cbo.zero",   0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
 
+/* ZiCondOps instructions. */
+{"czero.eqz",  0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 },
+{"czero.nez",  0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 },
+
 /* Zawrs instructions.  */
 {"wrs.nto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
 {"wrs.sto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },
-- 
2.38.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension
  2022-11-29  1:41   ` Palmer Dabbelt
@ 2022-11-29  2:19     ` Tsukasa OI
  2022-11-29  2:38       ` Palmer Dabbelt
  0 siblings, 1 reply; 10+ messages in thread
From: Tsukasa OI @ 2022-11-29  2:19 UTC (permalink / raw)
  To: Palmer Dabbelt, binutils

On 2022/11/29 10:41, Palmer Dabbelt wrote:
> On Mon, 28 Nov 2022 17:16:56 PST (-0800), binutils@sourceware.org wrote:
>> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>>
>> [DO NOT MERGE]
>> Until 'ZiCondOps' extension is frozen/ratified and final version
>> number is
>> determined, this patch should not be merged upstream.  This commit uses
>> version 1.0 as in the documentation.
>>
>> This commit adds support for the latest draft of RISC-V Integer
>> Conditional
>> Operations (ZiCondOps) extension consisting of 2 new instructions.
>>
>> This is based on the early draft of ZiCondOps on GitHub:
>> <https://github.com/riscv/riscv-zicondops/commit/91e173db867875a6e0ab21c89d146f1a28f416e3>
>>
>> bfd/ChangeLog:
>>
>>     * elfxx-riscv.c (riscv_supported_std_z_ext): Add 'ZiCondOps'.
>>     (riscv_multi_subset_supports): Support new instruction class.
>>     (riscv_multi_subset_supports_ext): Likewise.
>>
>> gas/ChangeLog:
>>
>>     * testsuite/gas/riscv/zicondops.s: New test for 'ZiCondOps'.
>>     * testsuite/gas/riscv/zicondops.d: Likewise.
>>     * testsuite/gas/riscv/zicondops-noarch.d: New test for
>>     architecture failure.
>>     * testsuite/gas/riscv/zicondops-noarch.l: Likewise.
>>
>> include/ChangeLog:
>>
>>     * opcode/riscv-opc.h (MATCH_CZERO_EQZ, MASK_CZERO_EQZ,
>>     MATCH_CZERO_NEZ, MASK_CZERO_NEZ): New.
>>     * opcode/riscv.h (enum riscv_insn_class): Add new instruction
>>     class INSN_CLASS_ZICONDOPS.
>>
>> opcodes/ChangeLog:
>>
>>     * riscv-opc.c (riscv_opcodes): Add new instructions from the
>>     'ZiCondOps' extension.
>> ---
>>  bfd/elfxx-riscv.c                          |  5 +++++
>>  gas/testsuite/gas/riscv/zicondops-noarch.d |  3 +++
>>  gas/testsuite/gas/riscv/zicondops-noarch.l |  3 +++
>>  gas/testsuite/gas/riscv/zicondops.d        | 11 +++++++++++
>>  gas/testsuite/gas/riscv/zicondops.s        |  3 +++
>>  include/opcode/riscv-opc.h                 |  8 ++++++++
>>  include/opcode/riscv.h                     |  1 +
>>  opcodes/riscv-opc.c                        |  4 ++++
>>  8 files changed, 38 insertions(+)
>>  create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.d
>>  create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.l
>>  create mode 100644 gas/testsuite/gas/riscv/zicondops.d
>>  create mode 100644 gas/testsuite/gas/riscv/zicondops.s
>>
>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> index 0bcf2fdcfa34..564fef205d01 100644
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -1168,6 +1168,7 @@ static struct riscv_supported_ext
>> riscv_supported_std_z_ext[] =
>>    {"zicbom",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 },
>>    {"zicbop",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 },
>>    {"zicboz",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 },
>> +  {"zicondops",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 },
>>    {"zicsr",        ISA_SPEC_CLASS_20191213,    2, 0,  0 },
>>    {"zicsr",        ISA_SPEC_CLASS_20190608,    2, 0,  0 },
>>    {"zifencei",        ISA_SPEC_CLASS_20191213,    2, 0,  0 },
>> @@ -2318,6 +2319,8 @@ riscv_multi_subset_supports
>> (riscv_parse_subset_t *rps,
>>        return riscv_subset_supports (rps, "zicbop");
>>      case INSN_CLASS_ZICBOZ:
>>        return riscv_subset_supports (rps, "zicboz");
>> +    case INSN_CLASS_ZICONDOPS:
>> +      return riscv_subset_supports (rps, "zicondops");
>>      case INSN_CLASS_ZICSR:
>>        return riscv_subset_supports (rps, "zicsr");
>>      case INSN_CLASS_ZIFENCEI:
>> @@ -2467,6 +2470,8 @@ riscv_multi_subset_supports_ext
>> (riscv_parse_subset_t *rps,
>>        return "zicbop";
>>      case INSN_CLASS_ZICBOZ:
>>        return "zicboz";
>> +    case INSN_CLASS_ZICONDOPS:
>> +      return "zicondops";
>>      case INSN_CLASS_ZICSR:
>>        return "zicsr";
>>      case INSN_CLASS_ZIFENCEI:
>> diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.d
>> b/gas/testsuite/gas/riscv/zicondops-noarch.d
>> new file mode 100644
>> index 000000000000..4f01b10f42df
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zicondops-noarch.d
>> @@ -0,0 +1,3 @@
>> +#as: -march=rv32i
>> +#source: zicondops.s
>> +#error_output: zicondops-noarch.l
>> diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.l
>> b/gas/testsuite/gas/riscv/zicondops-noarch.l
>> new file mode 100644
>> index 000000000000..b665d6022b98
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zicondops-noarch.l
>> @@ -0,0 +1,3 @@
>> +.*: Assembler messages:
>> +.*: Error: unrecognized opcode `czero\.eqz a0,a1,a2', extension
>> `zicondops' required
>> +.*: Error: unrecognized opcode `czero\.nez a3,a4,a5', extension
>> `zicondops' required
>> diff --git a/gas/testsuite/gas/riscv/zicondops.d
>> b/gas/testsuite/gas/riscv/zicondops.d
>> new file mode 100644
>> index 000000000000..9f417fa3b5ea
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zicondops.d
>> @@ -0,0 +1,11 @@
>> +#as: -march=rv32i_zicondops
>> +#source: zicondops.s
>> +#objdump: -d
>> +
>> +.*:[     ]+file format .*
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[     ]+[0-9a-f]+:[     ]+80c5a533[     ]+czero\.eqz[     ]+a0,a1,a2
>> +[     ]+[0-9a-f]+:[     ]+80f736b3[     ]+czero\.nez[     ]+a3,a4,a5
>> diff --git a/gas/testsuite/gas/riscv/zicondops.s
>> b/gas/testsuite/gas/riscv/zicondops.s
>> new file mode 100644
>> index 000000000000..dcf3d98ccd7e
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zicondops.s
>> @@ -0,0 +1,3 @@
>> +target:
>> +    czero.eqz    a0, a1, a2
>> +    czero.nez    a3, a4, a5
>> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> index 06e3df0f5a63..ea38df13ce6d 100644
>> --- a/include/opcode/riscv-opc.h
>> +++ b/include/opcode/riscv-opc.h
>> @@ -2113,6 +2113,11 @@
>>  #define MASK_CBO_INVAL 0xfff07fff
>>  #define MATCH_CBO_ZERO 0x40200f
>>  #define MASK_CBO_ZERO 0xfff07fff
>> +/* ZiCondOps instructions.  */
>> +#define MATCH_CZERO_EQZ 0x80002033
>> +#define MASK_CZERO_EQZ 0xfe00707f
>> +#define MATCH_CZERO_NEZ 0x80003033
>> +#define MASK_CZERO_NEZ 0xfe00707f
>>  /* Zawrs intructions.  */
>>  #define MATCH_WRS_NTO 0x00d00073
>>  #define MASK_WRS_NTO 0xffffffff
>> @@ -3115,6 +3120,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN,
>> MASK_CBO_CLEAN);
>>  DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
>>  DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
>>  DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
>> +/* ZiCondOps instructions.  */
>> +DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
>> +DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
>>  /* Zawrs instructions.  */
>>  DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
>>  DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
>> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
>> index c3cbde600cb0..c482f6f4d9f2 100644
>> --- a/include/opcode/riscv.h
>> +++ b/include/opcode/riscv.h
>> @@ -375,6 +375,7 @@ enum riscv_insn_class
>>    INSN_CLASS_Q,
>>    INSN_CLASS_F_AND_C,
>>    INSN_CLASS_D_AND_C,
>> +  INSN_CLASS_ZICONDOPS,
>>    INSN_CLASS_ZICSR,
>>    INSN_CLASS_ZIFENCEI,
>>    INSN_CLASS_ZIHINTPAUSE,
>> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
>> index 0e691544f9bc..311df46daa2d 100644
>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -935,6 +935,10 @@ const struct riscv_opcode riscv_opcodes[] =
>>  {"cbo.inval",  0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL,
>> MASK_CBO_INVAL, match_opcode, 0 },
>>  {"cbo.zero",   0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO,
>> MASK_CBO_ZERO, match_opcode, 0 },
>>
>> +/* ZiCondOps instructions. */
>> +{"czero.eqz",  0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_EQZ,
>> MASK_CZERO_EQZ, match_opcode, 0 },
>> +{"czero.nez",  0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_NEZ,
>> MASK_CZERO_NEZ, match_opcode, 0 },
>> +
>>  /* Zawrs instructions.  */
>>  {"wrs.nto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO,
>> match_opcode, 0 },
>>  {"wrs.sto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO,
>> match_opcode, 0 },
> 
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> # pending freeze
> 
> Thanks!
> 

Thanks for reviewing this but I found that the encodings of those
instruction have changed just a few hours ago.  I will notify that I've
submitted REVIEW ONLY v2 patchset for this.

<https://sourceware.org/pipermail/binutils/2022-November/124768.html>

Thanks,
Tsukasa

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension
  2022-11-29  2:19     ` Tsukasa OI
@ 2022-11-29  2:38       ` Palmer Dabbelt
  0 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2022-11-29  2:38 UTC (permalink / raw)
  To: research_trasio; +Cc: binutils

On Mon, 28 Nov 2022 18:19:31 PST (-0800), research_trasio@irq.a4lg.com wrote:
> On 2022/11/29 10:41, Palmer Dabbelt wrote:
>> On Mon, 28 Nov 2022 17:16:56 PST (-0800), binutils@sourceware.org wrote:
>>> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>>>
>>> [DO NOT MERGE]
>>> Until 'ZiCondOps' extension is frozen/ratified and final version
>>> number is
>>> determined, this patch should not be merged upstream.  This commit uses
>>> version 1.0 as in the documentation.
>>>
>>> This commit adds support for the latest draft of RISC-V Integer
>>> Conditional
>>> Operations (ZiCondOps) extension consisting of 2 new instructions.
>>>
>>> This is based on the early draft of ZiCondOps on GitHub:
>>> <https://github.com/riscv/riscv-zicondops/commit/91e173db867875a6e0ab21c89d146f1a28f416e3>
>>>
>>> bfd/ChangeLog:
>>>
>>>     * elfxx-riscv.c (riscv_supported_std_z_ext): Add 'ZiCondOps'.
>>>     (riscv_multi_subset_supports): Support new instruction class.
>>>     (riscv_multi_subset_supports_ext): Likewise.
>>>
>>> gas/ChangeLog:
>>>
>>>     * testsuite/gas/riscv/zicondops.s: New test for 'ZiCondOps'.
>>>     * testsuite/gas/riscv/zicondops.d: Likewise.
>>>     * testsuite/gas/riscv/zicondops-noarch.d: New test for
>>>     architecture failure.
>>>     * testsuite/gas/riscv/zicondops-noarch.l: Likewise.
>>>
>>> include/ChangeLog:
>>>
>>>     * opcode/riscv-opc.h (MATCH_CZERO_EQZ, MASK_CZERO_EQZ,
>>>     MATCH_CZERO_NEZ, MASK_CZERO_NEZ): New.
>>>     * opcode/riscv.h (enum riscv_insn_class): Add new instruction
>>>     class INSN_CLASS_ZICONDOPS.
>>>
>>> opcodes/ChangeLog:
>>>
>>>     * riscv-opc.c (riscv_opcodes): Add new instructions from the
>>>     'ZiCondOps' extension.
>>> ---
>>>  bfd/elfxx-riscv.c                          |  5 +++++
>>>  gas/testsuite/gas/riscv/zicondops-noarch.d |  3 +++
>>>  gas/testsuite/gas/riscv/zicondops-noarch.l |  3 +++
>>>  gas/testsuite/gas/riscv/zicondops.d        | 11 +++++++++++
>>>  gas/testsuite/gas/riscv/zicondops.s        |  3 +++
>>>  include/opcode/riscv-opc.h                 |  8 ++++++++
>>>  include/opcode/riscv.h                     |  1 +
>>>  opcodes/riscv-opc.c                        |  4 ++++
>>>  8 files changed, 38 insertions(+)
>>>  create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.d
>>>  create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.l
>>>  create mode 100644 gas/testsuite/gas/riscv/zicondops.d
>>>  create mode 100644 gas/testsuite/gas/riscv/zicondops.s
>>>
>>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>>> index 0bcf2fdcfa34..564fef205d01 100644
>>> --- a/bfd/elfxx-riscv.c
>>> +++ b/bfd/elfxx-riscv.c
>>> @@ -1168,6 +1168,7 @@ static struct riscv_supported_ext
>>> riscv_supported_std_z_ext[] =
>>>    {"zicbom",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 },
>>>    {"zicbop",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 },
>>>    {"zicboz",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 },
>>> +  {"zicondops",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 },
>>>    {"zicsr",        ISA_SPEC_CLASS_20191213,    2, 0,  0 },
>>>    {"zicsr",        ISA_SPEC_CLASS_20190608,    2, 0,  0 },
>>>    {"zifencei",        ISA_SPEC_CLASS_20191213,    2, 0,  0 },
>>> @@ -2318,6 +2319,8 @@ riscv_multi_subset_supports
>>> (riscv_parse_subset_t *rps,
>>>        return riscv_subset_supports (rps, "zicbop");
>>>      case INSN_CLASS_ZICBOZ:
>>>        return riscv_subset_supports (rps, "zicboz");
>>> +    case INSN_CLASS_ZICONDOPS:
>>> +      return riscv_subset_supports (rps, "zicondops");
>>>      case INSN_CLASS_ZICSR:
>>>        return riscv_subset_supports (rps, "zicsr");
>>>      case INSN_CLASS_ZIFENCEI:
>>> @@ -2467,6 +2470,8 @@ riscv_multi_subset_supports_ext
>>> (riscv_parse_subset_t *rps,
>>>        return "zicbop";
>>>      case INSN_CLASS_ZICBOZ:
>>>        return "zicboz";
>>> +    case INSN_CLASS_ZICONDOPS:
>>> +      return "zicondops";
>>>      case INSN_CLASS_ZICSR:
>>>        return "zicsr";
>>>      case INSN_CLASS_ZIFENCEI:
>>> diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.d
>>> b/gas/testsuite/gas/riscv/zicondops-noarch.d
>>> new file mode 100644
>>> index 000000000000..4f01b10f42df
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/riscv/zicondops-noarch.d
>>> @@ -0,0 +1,3 @@
>>> +#as: -march=rv32i
>>> +#source: zicondops.s
>>> +#error_output: zicondops-noarch.l
>>> diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.l
>>> b/gas/testsuite/gas/riscv/zicondops-noarch.l
>>> new file mode 100644
>>> index 000000000000..b665d6022b98
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/riscv/zicondops-noarch.l
>>> @@ -0,0 +1,3 @@
>>> +.*: Assembler messages:
>>> +.*: Error: unrecognized opcode `czero\.eqz a0,a1,a2', extension
>>> `zicondops' required
>>> +.*: Error: unrecognized opcode `czero\.nez a3,a4,a5', extension
>>> `zicondops' required
>>> diff --git a/gas/testsuite/gas/riscv/zicondops.d
>>> b/gas/testsuite/gas/riscv/zicondops.d
>>> new file mode 100644
>>> index 000000000000..9f417fa3b5ea
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/riscv/zicondops.d
>>> @@ -0,0 +1,11 @@
>>> +#as: -march=rv32i_zicondops
>>> +#source: zicondops.s
>>> +#objdump: -d
>>> +
>>> +.*:[     ]+file format .*
>>> +
>>> +Disassembly of section .text:
>>> +
>>> +0+000 <target>:
>>> +[     ]+[0-9a-f]+:[     ]+80c5a533[     ]+czero\.eqz[     ]+a0,a1,a2
>>> +[     ]+[0-9a-f]+:[     ]+80f736b3[     ]+czero\.nez[     ]+a3,a4,a5
>>> diff --git a/gas/testsuite/gas/riscv/zicondops.s
>>> b/gas/testsuite/gas/riscv/zicondops.s
>>> new file mode 100644
>>> index 000000000000..dcf3d98ccd7e
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/riscv/zicondops.s
>>> @@ -0,0 +1,3 @@
>>> +target:
>>> +    czero.eqz    a0, a1, a2
>>> +    czero.nez    a3, a4, a5
>>> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>>> index 06e3df0f5a63..ea38df13ce6d 100644
>>> --- a/include/opcode/riscv-opc.h
>>> +++ b/include/opcode/riscv-opc.h
>>> @@ -2113,6 +2113,11 @@
>>>  #define MASK_CBO_INVAL 0xfff07fff
>>>  #define MATCH_CBO_ZERO 0x40200f
>>>  #define MASK_CBO_ZERO 0xfff07fff
>>> +/* ZiCondOps instructions.  */
>>> +#define MATCH_CZERO_EQZ 0x80002033
>>> +#define MASK_CZERO_EQZ 0xfe00707f
>>> +#define MATCH_CZERO_NEZ 0x80003033
>>> +#define MASK_CZERO_NEZ 0xfe00707f
>>>  /* Zawrs intructions.  */
>>>  #define MATCH_WRS_NTO 0x00d00073
>>>  #define MASK_WRS_NTO 0xffffffff
>>> @@ -3115,6 +3120,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN,
>>> MASK_CBO_CLEAN);
>>>  DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
>>>  DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
>>>  DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
>>> +/* ZiCondOps instructions.  */
>>> +DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
>>> +DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
>>>  /* Zawrs instructions.  */
>>>  DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
>>>  DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
>>> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
>>> index c3cbde600cb0..c482f6f4d9f2 100644
>>> --- a/include/opcode/riscv.h
>>> +++ b/include/opcode/riscv.h
>>> @@ -375,6 +375,7 @@ enum riscv_insn_class
>>>    INSN_CLASS_Q,
>>>    INSN_CLASS_F_AND_C,
>>>    INSN_CLASS_D_AND_C,
>>> +  INSN_CLASS_ZICONDOPS,
>>>    INSN_CLASS_ZICSR,
>>>    INSN_CLASS_ZIFENCEI,
>>>    INSN_CLASS_ZIHINTPAUSE,
>>> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
>>> index 0e691544f9bc..311df46daa2d 100644
>>> --- a/opcodes/riscv-opc.c
>>> +++ b/opcodes/riscv-opc.c
>>> @@ -935,6 +935,10 @@ const struct riscv_opcode riscv_opcodes[] =
>>>  {"cbo.inval",  0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL,
>>> MASK_CBO_INVAL, match_opcode, 0 },
>>>  {"cbo.zero",   0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO,
>>> MASK_CBO_ZERO, match_opcode, 0 },
>>>
>>> +/* ZiCondOps instructions. */
>>> +{"czero.eqz",  0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_EQZ,
>>> MASK_CZERO_EQZ, match_opcode, 0 },
>>> +{"czero.nez",  0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_NEZ,
>>> MASK_CZERO_NEZ, match_opcode, 0 },
>>> +
>>>  /* Zawrs instructions.  */
>>>  {"wrs.nto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO,
>>> match_opcode, 0 },
>>>  {"wrs.sto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO,
>>> match_opcode, 0 },
>>
>> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> # pending freeze
>>
>> Thanks!
>>
>
> Thanks for reviewing this but I found that the encodings of those
> instruction have changed just a few hours ago.  I will notify that I've
> submitted REVIEW ONLY v2 patchset for this.
>
> <https://sourceware.org/pipermail/binutils/2022-November/124768.html>

Thanks.  That kind of stuff tends to move around a lot before the opcode 
folks commit to an allocation, so it's probably best waiting until that 
happens before trying too hard to track the encodings -- otherwise 
you're likely to just loose your mind ;)

>
> Thanks,
> Tsukasa

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [REVIEW ONLY v2 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension (encodings changed!)
  2022-11-29  2:06 ` [REVIEW ONLY v2 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension (encodings changed!) Tsukasa OI
  2022-11-29  2:06   ` [REVIEW ONLY v2 1/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension Tsukasa OI
@ 2022-11-29  2:40   ` Tsukasa OI
  2022-12-01  3:20   ` [REVIEW ONLY v3 0/1] UNRATIFIED RISC-V: Add 'ZiCond' extension Tsukasa OI
  2 siblings, 0 replies; 10+ messages in thread
From: Tsukasa OI @ 2022-11-29  2:40 UTC (permalink / raw)
  To: Tsukasa OI, Binutils

IMPORTANT NOTE:

I just received an e-mail from Andrew.
Considering his statements...

1.  Actual encodings will change **again** and
2.  The extension name is going to be 'Zicond', not 'Zicondops'.

I'll submit PATCH v3 after both are reflected.

Regards,
Tsukasa

On 2022/11/29 11:06, Tsukasa OI wrote:
> *** WAIT FOR SPECIFICATION FREEZE ***
> This is an implementation for unratified and not frozen RISC-V extension
> and not intended to be merged for now.
> The only intent to submit this patchset is to test new instructions for
> your (possibly virtual) environment and early review for fast adoption
> after ratification.
> 
> 
> Just two hours ago, the encodings of "czero.eqz" and "czero.nez"
> instructions have changed in the commit 8c5faf4c6d73.
> 
> This PATCH v2 reflects this change.
> 
> 
> This patchset adds following unratified extension to GNU Binutils:
> 
> -   'ZiCondOps' (Integer Conditional Operations)
>     version 1.0 in development
> 
> which adds 2 instructions ("czero.eqz" and "czero.nez").
> 
> This extension makes conditional arithmetic feature much simpler (fewer
> instructions when no branches are allowed).  Note that constant timing
> guarantee (data-independence / certain side-channel resistance) for this
> extension is being discussed and may not be guaranteed.
> 
> 
> This is based on the commit 8c5faf4c6d73 of the specification document:
> <https://github.com/riscv/riscv-zicondops>
> 
> 
> 
> 
> Tsukasa OI (1):
>   UNRATIFIED RISC-V: Add 'ZiCondOps' extension
> 
>  bfd/elfxx-riscv.c                          |  5 +++++
>  gas/testsuite/gas/riscv/zicondops-noarch.d |  3 +++
>  gas/testsuite/gas/riscv/zicondops-noarch.l |  3 +++
>  gas/testsuite/gas/riscv/zicondops.d        | 11 +++++++++++
>  gas/testsuite/gas/riscv/zicondops.s        |  3 +++
>  include/opcode/riscv-opc.h                 |  8 ++++++++
>  include/opcode/riscv.h                     |  1 +
>  opcodes/riscv-opc.c                        |  4 ++++
>  8 files changed, 38 insertions(+)
>  create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.d
>  create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.l
>  create mode 100644 gas/testsuite/gas/riscv/zicondops.d
>  create mode 100644 gas/testsuite/gas/riscv/zicondops.s
> 
> 
> base-commit: cb44f89ce977b1ab2d4063f2487950bddfb75bc7

^ permalink raw reply	[flat|nested] 10+ messages in thread
* [REVIEW ONLY v3 0/1] UNRATIFIED RISC-V: Add 'ZiCond' extension
  2022-11-29  2:06 ` [REVIEW ONLY v2 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension (encodings changed!) Tsukasa OI
  2022-11-29  2:06   ` [REVIEW ONLY v2 1/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension Tsukasa OI
  2022-11-29  2:40   ` [REVIEW ONLY v2 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension (encodings changed!) Tsukasa OI
@ 2022-12-01  3:20   ` Tsukasa OI
  2022-12-01  3:20     ` [REVIEW ONLY v3 1/1] " Tsukasa OI
  2 siblings, 1 reply; 10+ messages in thread
From: Tsukasa OI @ 2022-12-01  3:20 UTC (permalink / raw)
  To: Tsukasa OI; +Cc: binutils

*** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and not frozen RISC-V extension
and not intended to be merged for now.
The only intent to submit this patchset is to test new instructions for
your (possibly virtual) environment and early review for fast adoption
after ratification.


PATCH v3 reflects recent change of the extension name (from 'ZiCondOps' to
'ZiCond') and encoding (all v1, v2 and v3 has different encodings).


This patchset adds following unratified extension to GNU Binutils:

-   'ZiCond' (Integer Conditional Operations)
    version 1.0 in development

which adds 2 instructions ("czero.eqz" and "czero.nez").

This extension makes conditional arithmetic feature much simpler (fewer
instructions when no branches are allowed).  Note that constant timing
guarantee (data-independence / certain side-channel resistance) for this
extension is being discussed and may not be guaranteed.


This is based on the commit 394e24376939 of the specification document:
<https://github.com/riscv/riscv-zicondops>




Tsukasa OI (1):
  UNRATIFIED RISC-V: Add 'ZiCond' extension

 bfd/elfxx-riscv.c                       |  5 +++++
 gas/testsuite/gas/riscv/zicond-noarch.d |  3 +++
 gas/testsuite/gas/riscv/zicond-noarch.l |  3 +++
 gas/testsuite/gas/riscv/zicond.d        | 11 +++++++++++
 gas/testsuite/gas/riscv/zicond.s        |  3 +++
 include/opcode/riscv-opc.h              |  8 ++++++++
 include/opcode/riscv.h                  |  1 +
 opcodes/riscv-opc.c                     |  4 ++++
 8 files changed, 38 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zicond-noarch.d
 create mode 100644 gas/testsuite/gas/riscv/zicond-noarch.l
 create mode 100644 gas/testsuite/gas/riscv/zicond.d
 create mode 100644 gas/testsuite/gas/riscv/zicond.s


base-commit: 8a1c55cdfb2d17208cacfc6c34af4693d6956693
-- 
2.38.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
* [REVIEW ONLY v3 1/1] UNRATIFIED RISC-V: Add 'ZiCond' extension
  2022-12-01  3:20   ` [REVIEW ONLY v3 0/1] UNRATIFIED RISC-V: Add 'ZiCond' extension Tsukasa OI
@ 2022-12-01  3:20     ` Tsukasa OI
  0 siblings, 0 replies; 10+ messages in thread
From: Tsukasa OI @ 2022-12-01  3:20 UTC (permalink / raw)
  To: Tsukasa OI; +Cc: binutils

From: Tsukasa OI <research_trasio@irq.a4lg.com>

[DO NOT MERGE]
Until 'ZiCond' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream.  This commit uses
version 1.0 as in the documentation.

This commit adds support for the latest draft of RISC-V Integer Conditional
(ZiCond) extension consisting of 2 new instructions.

This is based on the early draft of ZiCond on GitHub:
<https://github.com/riscv/riscv-zicondops/commit/394e243769390025893b1a855071f5fffc659f36>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'ZiCond'.
	(riscv_multi_subset_supports): Support new instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zicond.s: New test for 'ZiCond'.
	* testsuite/gas/riscv/zicond.d: Likewise.
	* testsuite/gas/riscv/zicond-noarch.d: New test for
	architecture failure.
	* testsuite/gas/riscv/zicond-noarch.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_CZERO_EQZ, MASK_CZERO_EQZ,
	MATCH_CZERO_NEZ, MASK_CZERO_NEZ): New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	class INSN_CLASS_ZICOND.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add new instructions from the
	'ZiCond' extension.
---
 bfd/elfxx-riscv.c                       |  5 +++++
 gas/testsuite/gas/riscv/zicond-noarch.d |  3 +++
 gas/testsuite/gas/riscv/zicond-noarch.l |  3 +++
 gas/testsuite/gas/riscv/zicond.d        | 11 +++++++++++
 gas/testsuite/gas/riscv/zicond.s        |  3 +++
 include/opcode/riscv-opc.h              |  8 ++++++++
 include/opcode/riscv.h                  |  1 +
 opcodes/riscv-opc.c                     |  4 ++++
 8 files changed, 38 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zicond-noarch.d
 create mode 100644 gas/testsuite/gas/riscv/zicond-noarch.l
 create mode 100644 gas/testsuite/gas/riscv/zicond.d
 create mode 100644 gas/testsuite/gas/riscv/zicond.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0bcf2fdcfa34..3ecfc6353bdb 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1168,6 +1168,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zicbom",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicbop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicboz",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zicond",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zicsr",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zifencei",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
@@ -2318,6 +2319,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zicbop");
     case INSN_CLASS_ZICBOZ:
       return riscv_subset_supports (rps, "zicboz");
+    case INSN_CLASS_ZICOND:
+      return riscv_subset_supports (rps, "zicond");
     case INSN_CLASS_ZICSR:
       return riscv_subset_supports (rps, "zicsr");
     case INSN_CLASS_ZIFENCEI:
@@ -2467,6 +2470,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zicbop";
     case INSN_CLASS_ZICBOZ:
       return "zicboz";
+    case INSN_CLASS_ZICOND:
+      return "zicond";
     case INSN_CLASS_ZICSR:
       return "zicsr";
     case INSN_CLASS_ZIFENCEI:
diff --git a/gas/testsuite/gas/riscv/zicond-noarch.d b/gas/testsuite/gas/riscv/zicond-noarch.d
new file mode 100644
index 000000000000..f087315b4b1d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicond-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: zicond.s
+#error_output: zicond-noarch.l
diff --git a/gas/testsuite/gas/riscv/zicond-noarch.l b/gas/testsuite/gas/riscv/zicond-noarch.l
new file mode 100644
index 000000000000..c1aabf1b3856
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicond-noarch.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `czero\.eqz a0,a1,a2', extension `zicond' required
+.*: Error: unrecognized opcode `czero\.nez a3,a4,a5', extension `zicond' required
diff --git a/gas/testsuite/gas/riscv/zicond.d b/gas/testsuite/gas/riscv/zicond.d
new file mode 100644
index 000000000000..1d61e0797b98
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicond.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_zicond
+#source: zicond.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+0ec5d533[ 	]+czero\.eqz[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ef776b3[ 	]+czero\.nez[ 	]+a3,a4,a5
diff --git a/gas/testsuite/gas/riscv/zicond.s b/gas/testsuite/gas/riscv/zicond.s
new file mode 100644
index 000000000000..dcf3d98ccd7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicond.s
@@ -0,0 +1,3 @@
+target:
+	czero.eqz	a0, a1, a2
+	czero.nez	a3, a4, a5
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 06e3df0f5a63..558a227720f5 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2113,6 +2113,11 @@
 #define MASK_CBO_INVAL 0xfff07fff
 #define MATCH_CBO_ZERO 0x40200f
 #define MASK_CBO_ZERO 0xfff07fff
+/* ZiCond instructions.  */
+#define MATCH_CZERO_EQZ 0xe005033
+#define MASK_CZERO_EQZ 0xfe00707f
+#define MATCH_CZERO_NEZ 0xe007033
+#define MASK_CZERO_NEZ 0xfe00707f
 /* Zawrs intructions.  */
 #define MATCH_WRS_NTO 0x00d00073
 #define MASK_WRS_NTO 0xffffffff
@@ -3115,6 +3120,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
 DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
 DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
 DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
+/* ZiCond instructions.  */
+DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
+DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
 /* Zawrs instructions.  */
 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index c3cbde600cb0..ac1bb25c2075 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -375,6 +375,7 @@ enum riscv_insn_class
   INSN_CLASS_Q,
   INSN_CLASS_F_AND_C,
   INSN_CLASS_D_AND_C,
+  INSN_CLASS_ZICOND,
   INSN_CLASS_ZICSR,
   INSN_CLASS_ZIFENCEI,
   INSN_CLASS_ZIHINTPAUSE,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0e691544f9bc..7a40a2837b29 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -935,6 +935,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"cbo.inval",  0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
 {"cbo.zero",   0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
 
+/* ZiCond instructions. */
+{"czero.eqz",  0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 },
+{"czero.nez",  0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 },
+
 /* Zawrs instructions.  */
 {"wrs.nto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
 {"wrs.sto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },
-- 
2.38.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-12-01  3:20 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-29  1:16 [REVIEW ONLY 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension Tsukasa OI
2022-11-29  1:16 ` [REVIEW ONLY 1/1] " Tsukasa OI
2022-11-29  1:41   ` Palmer Dabbelt
2022-11-29  2:19     ` Tsukasa OI
2022-11-29  2:38       ` Palmer Dabbelt
2022-11-29  2:06 ` [REVIEW ONLY v2 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension (encodings changed!) Tsukasa OI
2022-11-29  2:06   ` [REVIEW ONLY v2 1/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension Tsukasa OI
2022-11-29  2:40   ` [REVIEW ONLY v2 0/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension (encodings changed!) Tsukasa OI
2022-12-01  3:20   ` [REVIEW ONLY v3 0/1] UNRATIFIED RISC-V: Add 'ZiCond' extension Tsukasa OI
2022-12-01  3:20     ` [REVIEW ONLY v3 1/1] " Tsukasa OI

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).