* [PATCH 0/2] RISC-V: Zfinx-related improvements (testcases and fmv.[sdq]) - SPLITTED @ 2022-09-28 7:20 Tsukasa OI 2022-09-28 7:20 ` [PATCH 1/2] RISC-V: Reorganize and enhance 'Zfinx' tests Tsukasa OI 2022-09-28 7:20 ` [PATCH 2/2] RISC-V: Relax "fmv.[sdq]" requirements Tsukasa OI 0 siblings, 2 replies; 7+ messages in thread From: Tsukasa OI @ 2022-09-28 7:20 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Hello, GitHub tracker: <https://github.com/a4lg/binutils-gdb/wiki/riscv_float_combined_1> A part of my combined 'Zfinx' fixes, in specific, register pair implementation (original PATCH 3/3) is being rewritten. The original PATCH 3/3 has following issues and being rewritten based on the framework to provide common framework to handle aligned register pairs for both 'Z[dq]inx' and 'Zpsfoperand' (a part of 'P'-extension proposal). It also have found following issues: (1) Lack of 'Zhinxmin' + 'Z[dq]inx' support (2) Insufficient test coverage (3) Possibly better handling to improve maintainability Original 'Zfinx' fixes: <https://sourceware.org/pipermail/binutils/2022-September/122715.html> New 'Zfinx' fixes branch (in development): <https://github.com/a4lg/binutils-gdb/tree/riscv-float-combined> Meanwhile, could someone at least approve the remaining part? PATCH 1/2 (formerly PATCH 1/3): Enhance Zfinx/Zdinx/Zqinx testcases Jiawei's 'Zhinx' testcases are great and extending the idea to 'Z[fdq]inx' would be also great. PATCH 2/2 (formerly PATCH 2/3): Relax Requirements to fmv.[sdq] instructions Note that fmv.h instruction is already available on both 'Zhinx' and 'Zfh'. Likewise, we should relax requirements to "fmv.[sdq]". For instance, "fmv.d" is now only a part of 'D' but the specification allows both 'D' and 'Zdinx' and it has unique benefits as described in the mail above. I fully explained why this is good to apply previously (see the mail above) and I didn't hear any objections here. I sincerely request the comment, review or approval (even rejection is acceptable as long as it doesn't take much time). It's already February when the first version is submitted to this mailing list and I would like to hear something new (Palmer added Reviewed-by lines to my early versions but I'm not confident enough that they were approval). Thanks, Tsukasa Tsukasa OI (2): RISC-V: Reorganize and enhance 'Zfinx' tests RISC-V: Relax "fmv.[sdq]" requirements gas/testsuite/gas/riscv/zdinx.d | 30 +++++++++--- gas/testsuite/gas/riscv/zdinx.s | 46 ++++++++++++----- gas/testsuite/gas/riscv/zfinx.d | 27 ++++++++-- gas/testsuite/gas/riscv/zfinx.s | 42 +++++++++++----- gas/testsuite/gas/riscv/zqinx.d | 87 +++++++++++++++++++-------------- gas/testsuite/gas/riscv/zqinx.s | 87 ++++++++++++++++++++------------- opcodes/riscv-opc.c | 6 +-- 7 files changed, 216 insertions(+), 109 deletions(-) base-commit: 26681d1c3c43469ca90ca39105278bc1601d4225 -- 2.34.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] RISC-V: Reorganize and enhance 'Zfinx' tests 2022-09-28 7:20 [PATCH 0/2] RISC-V: Zfinx-related improvements (testcases and fmv.[sdq]) - SPLITTED Tsukasa OI @ 2022-09-28 7:20 ` Tsukasa OI 2022-09-30 7:52 ` jiawei 2022-09-30 14:57 ` Nelson Chu 2022-09-28 7:20 ` [PATCH 2/2] RISC-V: Relax "fmv.[sdq]" requirements Tsukasa OI 1 sibling, 2 replies; 7+ messages in thread From: Tsukasa OI @ 2022-09-28 7:20 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils, jiawei This commit adds certain test cases for 'Zfinx'/'Zdinx'/'Zqinx' extensions and reorganizes them, fixing coding style while improving coverage. This is partially based on jiawei's 'Zhinx' testcases. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Use different registers for better encode space testing. Make indentation consistent. Add tests for instruction with rounding mode. Change march to minimum required extensions. Remove source line. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Likewise. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.s: Likewise. Also use even-numbered registers to use valid register pairs. * testsuite/gas/riscv/zqinx.d: Likewise. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: jiawei <jiawei@iscas.ac.cn> --- gas/testsuite/gas/riscv/zdinx.d | 29 ++++++++--- gas/testsuite/gas/riscv/zdinx.s | 45 ++++++++++++----- gas/testsuite/gas/riscv/zfinx.d | 26 ++++++++-- gas/testsuite/gas/riscv/zfinx.s | 41 +++++++++++----- gas/testsuite/gas/riscv/zqinx.d | 86 +++++++++++++++++++-------------- gas/testsuite/gas/riscv/zqinx.s | 86 ++++++++++++++++++++------------- 6 files changed, 207 insertions(+), 106 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index 3e4c1a73388..d41c39b0304 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -1,5 +1,4 @@ -#as: -march=rv64ima_zdinx -#source: zdinx.s +#as: -march=rv64i_zdinx #objdump: -dr .*:[ ]+file format .* @@ -8,26 +7,42 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c58553[ ]+fadd.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac58553[ ]+fsub.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+12c58553[ ]+fmul.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+1ac58553[ ]+fdiv.d[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+5a058553[ ]+fsqrt.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58543[ ]+fmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854f[ ]+fnmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58547[ ]+fmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854b[ ]+fnmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2058553[ ]+fcvt.w.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2158553[ ]+fcvt.wu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2258553[ ]+fcvt.l.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2358553[ ]+fcvt.lu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2258553[ ]+fcvt.d.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2358553[ ]+fcvt.d.lu[ ]+a0,a1,rne +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40158553[ ]+fcvt.s.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.d[ ]+a0,a1,a2 @@ -36,6 +51,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index c427d982aaf..be9a47fa404 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -1,33 +1,52 @@ target: fadd.d a0, a1, a2 + fadd.d a0, a1, a2, rne fsub.d a0, a1, a2 + fsub.d a0, a1, a2, rne fmul.d a0, a1, a2 + fmul.d a0, a1, a2, rne fdiv.d a0, a1, a2 - fsqrt.d a0, a0 + fdiv.d a0, a1, a2, rne + fsqrt.d a0, a1 + fsqrt.d a0, a1, rne fmin.d a0, a1, a2 fmax.d a0, a1, a2 - fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3, rne fnmadd.d a0, a1, a2, a3 - fmsub.d a0, a1, a2, a3 + fnmadd.d a0, a1, a2, a3, rne + fmsub.d a0, a1, a2, a3 + fmsub.d a0, a1, a2, a3, rne fnmsub.d a0, a1, a2, a3 + fnmsub.d a0, a1, a2, a3, rne + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rne fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rne fcvt.l.d a0, a1 + fcvt.l.d a0, a1, rne fcvt.lu.d a0, a1 - fcvt.s.d a0, a1 - fcvt.d.s a0, a1 + fcvt.lu.d a0, a1, rne fcvt.d.w a0, a1 fcvt.d.wu a0, a1 fcvt.d.l a0, a1 + fcvt.d.l a0, a1, rne fcvt.d.lu a0, a1 - fsgnj.d a0, a1, a2 + fcvt.d.lu a0, a1, rne + + fcvt.d.s a0, a1 + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rne + + fsgnj.d a0, a1, a2 fsgnjn.d a0, a1, a2 fsgnjx.d a0, a1, a2 - feq.d a0, a1, a2 - flt.d a0, a1, a2 - fle.d a0, a1, a2 - fgt.d a0, a1, a2 - fge.d a0, a1, a2 - fneg.d a0, a0 - fabs.d a0, a0 + feq.d a0, a1, a2 + flt.d a0, a1, a2 + fle.d a0, a1, a2 + fgt.d a0, a1, a2 + fge.d a0, a1, a2 + fneg.d a0, a1 + fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index d5499aa9131..3e99b766f5b 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -1,5 +1,4 @@ -#as: -march=rv64ima_zfinx -#source: zfinx.s +#as: -march=rv64i_zfinx #objdump: -dr .*:[ ]+file format .* @@ -8,24 +7,41 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+00c58553[ ]+fadd.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+08c58553[ ]+fsub.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+10c58553[ ]+fmul.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+18c58553[ ]+fdiv.s[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+58058553[ ]+fsqrt.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58543[ ]+fmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54f[ ]+fnmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854f[ ]+fnmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f547[ ]+fmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58547[ ]+fmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54b[ ]+fnmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854b[ ]+fnmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c005f553[ ]+fcvt.w.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0058553[ ]+fcvt.w.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c015f553[ ]+fcvt.wu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0158553[ ]+fcvt.wu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c025f553[ ]+fcvt.l.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0258553[ ]+fcvt.l.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c035f553[ ]+fcvt.lu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0358553[ ]+fcvt.lu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d005f553[ ]+fcvt.s.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0058553[ ]+fcvt.s.w[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d015f553[ ]+fcvt.s.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0158553[ ]+fcvt.s.wu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d025f553[ ]+fcvt.s.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0258553[ ]+fcvt.s.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d035f553[ ]+fcvt.s.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0358553[ ]+fcvt.s.lu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+20c58553[ ]+fsgnj.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c59553[ ]+fsgnjn.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c5a553[ ]+fsgnjx.s[ ]+a0,a1,a2 @@ -34,6 +50,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index af50490fadf..6687f3187ef 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -1,31 +1,50 @@ target: fadd.s a0, a1, a2 + fadd.s a0, a1, a2, rne fsub.s a0, a1, a2 + fsub.s a0, a1, a2, rne fmul.s a0, a1, a2 + fmul.s a0, a1, a2, rne fdiv.s a0, a1, a2 - fsqrt.s a0, a0 + fdiv.s a0, a1, a2, rne + fsqrt.s a0, a1 + fsqrt.s a0, a1, rne fmin.s a0, a1, a2 fmax.s a0, a1, a2 - fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3, rne fnmadd.s a0, a1, a2, a3 - fmsub.s a0, a1, a2, a3 + fnmadd.s a0, a1, a2, a3, rne + fmsub.s a0, a1, a2, a3 + fmsub.s a0, a1, a2, a3, rne fnmsub.s a0, a1, a2, a3 + fnmsub.s a0, a1, a2, a3, rne + fcvt.w.s a0, a1 + fcvt.w.s a0, a1, rne fcvt.wu.s a0, a1 + fcvt.wu.s a0, a1, rne fcvt.l.s a0, a1 + fcvt.l.s a0, a1, rne fcvt.lu.s a0, a1 + fcvt.lu.s a0, a1, rne fcvt.s.w a0, a1 + fcvt.s.w a0, a1, rne fcvt.s.wu a0, a1 + fcvt.s.wu a0, a1, rne fcvt.s.l a0, a1 + fcvt.s.l a0, a1, rne fcvt.s.lu a0, a1 - fsgnj.s a0, a1, a2 + fcvt.s.lu a0, a1, rne + + fsgnj.s a0, a1, a2 fsgnjn.s a0, a1, a2 fsgnjx.s a0, a1, a2 - feq.s a0, a1, a2 - flt.s a0, a1, a2 - fle.s a0, a1, a2 - fgt.s a0, a1, a2 - fge.s a0, a1, a2 - fneg.s a0, a0 - fabs.s a0, a0 + feq.s a0, a1, a2 + flt.s a0, a1, a2 + fle.s a0, a1, a2 + fgt.s a0, a1, a2 + fge.s a0, a1, a2 + fneg.s a0, a1 + fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index c1a09201206..224bc827ad0 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -1,5 +1,4 @@ -#as: -march=rv64ima_zqinx -#source: zqinx.s +#as: -march=rv64i_zqinx #objdump: -dr .*:[ ]+file format .* @@ -7,37 +6,52 @@ Disassembly of section .text: 0+000 <target>: -[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index ba5179dc727..e4244a4277d 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -1,35 +1,53 @@ target: - fadd.q a0, a1, a2 - fsub.q a0, a1, a2 - fmul.q a0, a1, a2 - fdiv.q a0, a1, a2 - fsqrt.q a0, a0 - fmin.q a0, a1, a2 - fmax.q a0, a1, a2 - fmadd.q a0, a1, a2, a3 - fnmadd.q a0, a1, a2, a3 - fmsub.q a0, a1, a2, a3 - fnmsub.q a0, a1, a2, a3 - fcvt.w.q a0, a1 - fcvt.wu.q a0, a1 - fcvt.l.q a0, a1 - fcvt.lu.q a0, a1 - fcvt.s.q a0, a1 - fcvt.d.q a0, a1 - fcvt.q.s a0, a1 - fcvt.q.d a0, a1 - fcvt.q.w a0, a1 - fcvt.q.wu a0, a1 - fcvt.q.l a0, a1 - fcvt.q.lu a0, a1 - fsgnj.q a0, a1, a2 - fsgnjn.q a0, a1, a2 - fsgnjx.q a0, a1, a2 - feq.q a0, a1, a2 - flt.q a0, a1, a2 - fle.q a0, a1, a2 - fgt.q a0, a1, a2 - fge.q a0, a1, a2 - fneg.q a0, a0 - fabs.q a0, a0 - fclass.q a0, a1 + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rne + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rne + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rne + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rne + fsqrt.q a0, a2 + fsqrt.q a0, a2, rne + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rne + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rne + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rne + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rne + + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rne + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rne + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rne + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rne + fcvt.q.w a0, a2 + fcvt.q.wu a0, a2 + fcvt.q.l a0, a2 + fcvt.q.lu a0, a2 + + fcvt.q.s a0, a2 + fcvt.q.d a0, a2 + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rne + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rne + + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + feq.q a0, a2, a4 + flt.q a0, a2, a4 + fle.q a0, a2, a4 + fgt.q a0, a2, a4 + fge.q a0, a2, a4 + fneg.q a0, a2 + fabs.q a0, a2 + fclass.q a0, a2 -- 2.34.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] RISC-V: Reorganize and enhance 'Zfinx' tests 2022-09-28 7:20 ` [PATCH 1/2] RISC-V: Reorganize and enhance 'Zfinx' tests Tsukasa OI @ 2022-09-30 7:52 ` jiawei 2022-09-30 14:57 ` Nelson Chu 1 sibling, 0 replies; 7+ messages in thread From: jiawei @ 2022-09-30 7:52 UTC (permalink / raw) To: Tsukasa OI; +Cc: Nelson Chu, Kito Cheng, Palmer Dabbelt, binutils LGTM, thanks for your works. > -----原始邮件----- > 发件人: "Tsukasa OI" <research_trasio@irq.a4lg.com> > 发送时间: 2022-09-28 15:20:28 (星期三) > 收件人: "Tsukasa OI" <research_trasio@irq.a4lg.com>, "Nelson Chu" <nelson@rivosinc.com>, "Kito Cheng" <kito.cheng@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com> > 抄送: binutils@sourceware.org, jiawei <jiawei@iscas.ac.cn> > 主题: [PATCH 1/2] RISC-V: Reorganize and enhance 'Zfinx' tests > > This commit adds certain test cases for 'Zfinx'/'Zdinx'/'Zqinx' extensions > and reorganizes them, fixing coding style while improving coverage. > This is partially based on jiawei's 'Zhinx' testcases. > > gas/ChangeLog: > > * testsuite/gas/riscv/zfinx.s: Use different registers for > better encode space testing. Make indentation consistent. > Add tests for instruction with rounding mode. Change march > to minimum required extensions. Remove source line. > * testsuite/gas/riscv/zfinx.d: Likewise. > * testsuite/gas/riscv/zdinx.s: Likewise. > * testsuite/gas/riscv/zdinx.d: Likewise. > * testsuite/gas/riscv/zqinx.s: Likewise. > Also use even-numbered registers to use valid register pairs. > * testsuite/gas/riscv/zqinx.d: Likewise. > > Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> > Signed-off-by: jiawei <jiawei@iscas.ac.cn> > --- > gas/testsuite/gas/riscv/zdinx.d | 29 ++++++++--- > gas/testsuite/gas/riscv/zdinx.s | 45 ++++++++++++----- > gas/testsuite/gas/riscv/zfinx.d | 26 ++++++++-- > gas/testsuite/gas/riscv/zfinx.s | 41 +++++++++++----- > gas/testsuite/gas/riscv/zqinx.d | 86 +++++++++++++++++++-------------- > gas/testsuite/gas/riscv/zqinx.s | 86 ++++++++++++++++++++------------- > 6 files changed, 207 insertions(+), 106 deletions(-) > > diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d > index 3e4c1a73388..d41c39b0304 100644 > --- a/gas/testsuite/gas/riscv/zdinx.d > +++ b/gas/testsuite/gas/riscv/zdinx.d > @@ -1,5 +1,4 @@ > -#as: -march=rv64ima_zdinx > -#source: zdinx.s > +#as: -march=rv64i_zdinx > #objdump: -dr > > .*:[ ]+file format .* > @@ -8,26 +7,42 @@ Disassembly of section .text: > > 0+000 <target>: > [ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.d[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c58553[ ]+fadd.d[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+0ac58553[ ]+fsub.d[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+12c58553[ ]+fmul.d[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+1ac58553[ ]+fdiv.d[ ]+a0,a1,a2,rne > +[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+5a058553[ ]+fsqrt.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+6ac58543[ ]+fmadd.d[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.d[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+6ac5854f[ ]+fnmadd.d[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.d[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+6ac58547[ ]+fmsub.d[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.d[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+6ac5854b[ ]+fnmsub.d[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c2058553[ ]+fcvt.w.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c2158553[ ]+fcvt.wu.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c2258553[ ]+fcvt.l.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c2358553[ ]+fcvt.lu.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d2258553[ ]+fcvt.d.l[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d2358553[ ]+fcvt.d.lu[ ]+a0,a1,rne > +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+40158553[ ]+fcvt.s.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.d[ ]+a0,a1,a2 > @@ -36,6 +51,6 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s > index c427d982aaf..be9a47fa404 100644 > --- a/gas/testsuite/gas/riscv/zdinx.s > +++ b/gas/testsuite/gas/riscv/zdinx.s > @@ -1,33 +1,52 @@ > target: > fadd.d a0, a1, a2 > + fadd.d a0, a1, a2, rne > fsub.d a0, a1, a2 > + fsub.d a0, a1, a2, rne > fmul.d a0, a1, a2 > + fmul.d a0, a1, a2, rne > fdiv.d a0, a1, a2 > - fsqrt.d a0, a0 > + fdiv.d a0, a1, a2, rne > + fsqrt.d a0, a1 > + fsqrt.d a0, a1, rne > fmin.d a0, a1, a2 > fmax.d a0, a1, a2 > - fmadd.d a0, a1, a2, a3 > + fmadd.d a0, a1, a2, a3 > + fmadd.d a0, a1, a2, a3, rne > fnmadd.d a0, a1, a2, a3 > - fmsub.d a0, a1, a2, a3 > + fnmadd.d a0, a1, a2, a3, rne > + fmsub.d a0, a1, a2, a3 > + fmsub.d a0, a1, a2, a3, rne > fnmsub.d a0, a1, a2, a3 > + fnmsub.d a0, a1, a2, a3, rne > + > fcvt.w.d a0, a1 > + fcvt.w.d a0, a1, rne > fcvt.wu.d a0, a1 > + fcvt.wu.d a0, a1, rne > fcvt.l.d a0, a1 > + fcvt.l.d a0, a1, rne > fcvt.lu.d a0, a1 > - fcvt.s.d a0, a1 > - fcvt.d.s a0, a1 > + fcvt.lu.d a0, a1, rne > fcvt.d.w a0, a1 > fcvt.d.wu a0, a1 > fcvt.d.l a0, a1 > + fcvt.d.l a0, a1, rne > fcvt.d.lu a0, a1 > - fsgnj.d a0, a1, a2 > + fcvt.d.lu a0, a1, rne > + > + fcvt.d.s a0, a1 > + fcvt.s.d a0, a1 > + fcvt.s.d a0, a1, rne > + > + fsgnj.d a0, a1, a2 > fsgnjn.d a0, a1, a2 > fsgnjx.d a0, a1, a2 > - feq.d a0, a1, a2 > - flt.d a0, a1, a2 > - fle.d a0, a1, a2 > - fgt.d a0, a1, a2 > - fge.d a0, a1, a2 > - fneg.d a0, a0 > - fabs.d a0, a0 > + feq.d a0, a1, a2 > + flt.d a0, a1, a2 > + fle.d a0, a1, a2 > + fgt.d a0, a1, a2 > + fge.d a0, a1, a2 > + fneg.d a0, a1 > + fabs.d a0, a1 > fclass.d a0, a1 > diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d > index d5499aa9131..3e99b766f5b 100644 > --- a/gas/testsuite/gas/riscv/zfinx.d > +++ b/gas/testsuite/gas/riscv/zfinx.d > @@ -1,5 +1,4 @@ > -#as: -march=rv64ima_zfinx > -#source: zfinx.s > +#as: -march=rv64i_zfinx > #objdump: -dr > > .*:[ ]+file format .* > @@ -8,24 +7,41 @@ Disassembly of section .text: > > 0+000 <target>: > [ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd.s[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+00c58553[ ]+fadd.s[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+08c58553[ ]+fsub.s[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+10c58553[ ]+fmul.s[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+18c58553[ ]+fdiv.s[ ]+a0,a1,a2,rne > +[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+58058553[ ]+fsqrt.s[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+68c58543[ ]+fmadd.s[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+68c5f54f[ ]+fnmadd.s[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+68c5854f[ ]+fnmadd.s[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+68c5f547[ ]+fmsub.s[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+68c58547[ ]+fmsub.s[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+68c5f54b[ ]+fnmsub.s[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+68c5854b[ ]+fnmsub.s[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+c005f553[ ]+fcvt.w.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c0058553[ ]+fcvt.w.s[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c015f553[ ]+fcvt.wu.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c0158553[ ]+fcvt.wu.s[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c025f553[ ]+fcvt.l.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c0258553[ ]+fcvt.l.s[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c035f553[ ]+fcvt.lu.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c0358553[ ]+fcvt.lu.s[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d005f553[ ]+fcvt.s.w[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d0058553[ ]+fcvt.s.w[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d015f553[ ]+fcvt.s.wu[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d0158553[ ]+fcvt.s.wu[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d025f553[ ]+fcvt.s.l[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d0258553[ ]+fcvt.s.l[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d035f553[ ]+fcvt.s.lu[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d0358553[ ]+fcvt.s.lu[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+20c58553[ ]+fsgnj.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+20c59553[ ]+fsgnjn.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+20c5a553[ ]+fsgnjx.s[ ]+a0,a1,a2 > @@ -34,6 +50,6 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s > index af50490fadf..6687f3187ef 100644 > --- a/gas/testsuite/gas/riscv/zfinx.s > +++ b/gas/testsuite/gas/riscv/zfinx.s > @@ -1,31 +1,50 @@ > target: > fadd.s a0, a1, a2 > + fadd.s a0, a1, a2, rne > fsub.s a0, a1, a2 > + fsub.s a0, a1, a2, rne > fmul.s a0, a1, a2 > + fmul.s a0, a1, a2, rne > fdiv.s a0, a1, a2 > - fsqrt.s a0, a0 > + fdiv.s a0, a1, a2, rne > + fsqrt.s a0, a1 > + fsqrt.s a0, a1, rne > fmin.s a0, a1, a2 > fmax.s a0, a1, a2 > - fmadd.s a0, a1, a2, a3 > + fmadd.s a0, a1, a2, a3 > + fmadd.s a0, a1, a2, a3, rne > fnmadd.s a0, a1, a2, a3 > - fmsub.s a0, a1, a2, a3 > + fnmadd.s a0, a1, a2, a3, rne > + fmsub.s a0, a1, a2, a3 > + fmsub.s a0, a1, a2, a3, rne > fnmsub.s a0, a1, a2, a3 > + fnmsub.s a0, a1, a2, a3, rne > + > fcvt.w.s a0, a1 > + fcvt.w.s a0, a1, rne > fcvt.wu.s a0, a1 > + fcvt.wu.s a0, a1, rne > fcvt.l.s a0, a1 > + fcvt.l.s a0, a1, rne > fcvt.lu.s a0, a1 > + fcvt.lu.s a0, a1, rne > fcvt.s.w a0, a1 > + fcvt.s.w a0, a1, rne > fcvt.s.wu a0, a1 > + fcvt.s.wu a0, a1, rne > fcvt.s.l a0, a1 > + fcvt.s.l a0, a1, rne > fcvt.s.lu a0, a1 > - fsgnj.s a0, a1, a2 > + fcvt.s.lu a0, a1, rne > + > + fsgnj.s a0, a1, a2 > fsgnjn.s a0, a1, a2 > fsgnjx.s a0, a1, a2 > - feq.s a0, a1, a2 > - flt.s a0, a1, a2 > - fle.s a0, a1, a2 > - fgt.s a0, a1, a2 > - fge.s a0, a1, a2 > - fneg.s a0, a0 > - fabs.s a0, a0 > + feq.s a0, a1, a2 > + flt.s a0, a1, a2 > + fle.s a0, a1, a2 > + fgt.s a0, a1, a2 > + fge.s a0, a1, a2 > + fneg.s a0, a1 > + fabs.s a0, a1 > fclass.s a0, a1 > diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d > index c1a09201206..224bc827ad0 100644 > --- a/gas/testsuite/gas/riscv/zqinx.d > +++ b/gas/testsuite/gas/riscv/zqinx.d > @@ -1,5 +1,4 @@ > -#as: -march=rv64ima_zqinx > -#source: zqinx.s > +#as: -march=rv64i_zqinx > #objdump: -dr > > .*:[ ]+file format .* > @@ -7,37 +6,52 @@ > Disassembly of section .text: > > 0+000 <target>: > -[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne > +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne > +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne > +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne > +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne > +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne > +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne > +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne > +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 > diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s > index ba5179dc727..e4244a4277d 100644 > --- a/gas/testsuite/gas/riscv/zqinx.s > +++ b/gas/testsuite/gas/riscv/zqinx.s > @@ -1,35 +1,53 @@ > target: > - fadd.q a0, a1, a2 > - fsub.q a0, a1, a2 > - fmul.q a0, a1, a2 > - fdiv.q a0, a1, a2 > - fsqrt.q a0, a0 > - fmin.q a0, a1, a2 > - fmax.q a0, a1, a2 > - fmadd.q a0, a1, a2, a3 > - fnmadd.q a0, a1, a2, a3 > - fmsub.q a0, a1, a2, a3 > - fnmsub.q a0, a1, a2, a3 > - fcvt.w.q a0, a1 > - fcvt.wu.q a0, a1 > - fcvt.l.q a0, a1 > - fcvt.lu.q a0, a1 > - fcvt.s.q a0, a1 > - fcvt.d.q a0, a1 > - fcvt.q.s a0, a1 > - fcvt.q.d a0, a1 > - fcvt.q.w a0, a1 > - fcvt.q.wu a0, a1 > - fcvt.q.l a0, a1 > - fcvt.q.lu a0, a1 > - fsgnj.q a0, a1, a2 > - fsgnjn.q a0, a1, a2 > - fsgnjx.q a0, a1, a2 > - feq.q a0, a1, a2 > - flt.q a0, a1, a2 > - fle.q a0, a1, a2 > - fgt.q a0, a1, a2 > - fge.q a0, a1, a2 > - fneg.q a0, a0 > - fabs.q a0, a0 > - fclass.q a0, a1 > + fadd.q a0, a2, a4 > + fadd.q a0, a2, a4, rne > + fsub.q a0, a2, a4 > + fsub.q a0, a2, a4, rne > + fmul.q a0, a2, a4 > + fmul.q a0, a2, a4, rne > + fdiv.q a0, a2, a4 > + fdiv.q a0, a2, a4, rne > + fsqrt.q a0, a2 > + fsqrt.q a0, a2, rne > + fmin.q a0, a2, a4 > + fmax.q a0, a2, a4 > + fmadd.q a0, a2, a4, a6 > + fmadd.q a0, a2, a4, a6, rne > + fnmadd.q a0, a2, a4, a6 > + fnmadd.q a0, a2, a4, a6, rne > + fmsub.q a0, a2, a4, a6 > + fmsub.q a0, a2, a4, a6, rne > + fnmsub.q a0, a2, a4, a6 > + fnmsub.q a0, a2, a4, a6, rne > + > + fcvt.w.q a0, a2 > + fcvt.w.q a0, a2, rne > + fcvt.wu.q a0, a2 > + fcvt.wu.q a0, a2, rne > + fcvt.l.q a0, a2 > + fcvt.l.q a0, a2, rne > + fcvt.lu.q a0, a2 > + fcvt.lu.q a0, a2, rne > + fcvt.q.w a0, a2 > + fcvt.q.wu a0, a2 > + fcvt.q.l a0, a2 > + fcvt.q.lu a0, a2 > + > + fcvt.q.s a0, a2 > + fcvt.q.d a0, a2 > + fcvt.s.q a0, a2 > + fcvt.s.q a0, a2, rne > + fcvt.d.q a0, a2 > + fcvt.d.q a0, a2, rne > + > + fsgnj.q a0, a2, a4 > + fsgnjn.q a0, a2, a4 > + fsgnjx.q a0, a2, a4 > + feq.q a0, a2, a4 > + flt.q a0, a2, a4 > + fle.q a0, a2, a4 > + fgt.q a0, a2, a4 > + fge.q a0, a2, a4 > + fneg.q a0, a2 > + fabs.q a0, a2 > + fclass.q a0, a2 > -- > 2.34.1 </target></target></target></jiawei@iscas.ac.cn></research_trasio@irq.a4lg.com></jiawei@iscas.ac.cn></palmer@dabbelt.com></kito.cheng@sifive.com></nelson@rivosinc.com></research_trasio@irq.a4lg.com></research_trasio@irq.a4lg.com> ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] RISC-V: Reorganize and enhance 'Zfinx' tests 2022-09-28 7:20 ` [PATCH 1/2] RISC-V: Reorganize and enhance 'Zfinx' tests Tsukasa OI 2022-09-30 7:52 ` jiawei @ 2022-09-30 14:57 ` Nelson Chu 1 sibling, 0 replies; 7+ messages in thread From: Nelson Chu @ 2022-09-30 14:57 UTC (permalink / raw) To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils, jiawei OK, please commit, thanks. Nelson On Wed, Sep 28, 2022 at 3:20 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > > This commit adds certain test cases for 'Zfinx'/'Zdinx'/'Zqinx' extensions > and reorganizes them, fixing coding style while improving coverage. > This is partially based on jiawei's 'Zhinx' testcases. > > gas/ChangeLog: > > * testsuite/gas/riscv/zfinx.s: Use different registers for > better encode space testing. Make indentation consistent. > Add tests for instruction with rounding mode. Change march > to minimum required extensions. Remove source line. > * testsuite/gas/riscv/zfinx.d: Likewise. > * testsuite/gas/riscv/zdinx.s: Likewise. > * testsuite/gas/riscv/zdinx.d: Likewise. > * testsuite/gas/riscv/zqinx.s: Likewise. > Also use even-numbered registers to use valid register pairs. > * testsuite/gas/riscv/zqinx.d: Likewise. > > Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> > Signed-off-by: jiawei <jiawei@iscas.ac.cn> > --- > gas/testsuite/gas/riscv/zdinx.d | 29 ++++++++--- > gas/testsuite/gas/riscv/zdinx.s | 45 ++++++++++++----- > gas/testsuite/gas/riscv/zfinx.d | 26 ++++++++-- > gas/testsuite/gas/riscv/zfinx.s | 41 +++++++++++----- > gas/testsuite/gas/riscv/zqinx.d | 86 +++++++++++++++++++-------------- > gas/testsuite/gas/riscv/zqinx.s | 86 ++++++++++++++++++++------------- > 6 files changed, 207 insertions(+), 106 deletions(-) > > diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d > index 3e4c1a73388..d41c39b0304 100644 > --- a/gas/testsuite/gas/riscv/zdinx.d > +++ b/gas/testsuite/gas/riscv/zdinx.d > @@ -1,5 +1,4 @@ > -#as: -march=rv64ima_zdinx > -#source: zdinx.s > +#as: -march=rv64i_zdinx > #objdump: -dr > > .*:[ ]+file format .* > @@ -8,26 +7,42 @@ Disassembly of section .text: > > 0+000 <target>: > [ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.d[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c58553[ ]+fadd.d[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+0ac58553[ ]+fsub.d[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+12c58553[ ]+fmul.d[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+1ac58553[ ]+fdiv.d[ ]+a0,a1,a2,rne > +[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+5a058553[ ]+fsqrt.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+6ac58543[ ]+fmadd.d[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.d[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+6ac5854f[ ]+fnmadd.d[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.d[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+6ac58547[ ]+fmsub.d[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.d[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+6ac5854b[ ]+fnmsub.d[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c2058553[ ]+fcvt.w.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c2158553[ ]+fcvt.wu.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c2258553[ ]+fcvt.l.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c2358553[ ]+fcvt.lu.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d2258553[ ]+fcvt.d.l[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d2358553[ ]+fcvt.d.lu[ ]+a0,a1,rne > +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+40158553[ ]+fcvt.s.d[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.d[ ]+a0,a1,a2 > @@ -36,6 +51,6 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s > index c427d982aaf..be9a47fa404 100644 > --- a/gas/testsuite/gas/riscv/zdinx.s > +++ b/gas/testsuite/gas/riscv/zdinx.s > @@ -1,33 +1,52 @@ > target: > fadd.d a0, a1, a2 > + fadd.d a0, a1, a2, rne > fsub.d a0, a1, a2 > + fsub.d a0, a1, a2, rne > fmul.d a0, a1, a2 > + fmul.d a0, a1, a2, rne > fdiv.d a0, a1, a2 > - fsqrt.d a0, a0 > + fdiv.d a0, a1, a2, rne > + fsqrt.d a0, a1 > + fsqrt.d a0, a1, rne > fmin.d a0, a1, a2 > fmax.d a0, a1, a2 > - fmadd.d a0, a1, a2, a3 > + fmadd.d a0, a1, a2, a3 > + fmadd.d a0, a1, a2, a3, rne > fnmadd.d a0, a1, a2, a3 > - fmsub.d a0, a1, a2, a3 > + fnmadd.d a0, a1, a2, a3, rne > + fmsub.d a0, a1, a2, a3 > + fmsub.d a0, a1, a2, a3, rne > fnmsub.d a0, a1, a2, a3 > + fnmsub.d a0, a1, a2, a3, rne > + > fcvt.w.d a0, a1 > + fcvt.w.d a0, a1, rne > fcvt.wu.d a0, a1 > + fcvt.wu.d a0, a1, rne > fcvt.l.d a0, a1 > + fcvt.l.d a0, a1, rne > fcvt.lu.d a0, a1 > - fcvt.s.d a0, a1 > - fcvt.d.s a0, a1 > + fcvt.lu.d a0, a1, rne > fcvt.d.w a0, a1 > fcvt.d.wu a0, a1 > fcvt.d.l a0, a1 > + fcvt.d.l a0, a1, rne > fcvt.d.lu a0, a1 > - fsgnj.d a0, a1, a2 > + fcvt.d.lu a0, a1, rne > + > + fcvt.d.s a0, a1 > + fcvt.s.d a0, a1 > + fcvt.s.d a0, a1, rne > + > + fsgnj.d a0, a1, a2 > fsgnjn.d a0, a1, a2 > fsgnjx.d a0, a1, a2 > - feq.d a0, a1, a2 > - flt.d a0, a1, a2 > - fle.d a0, a1, a2 > - fgt.d a0, a1, a2 > - fge.d a0, a1, a2 > - fneg.d a0, a0 > - fabs.d a0, a0 > + feq.d a0, a1, a2 > + flt.d a0, a1, a2 > + fle.d a0, a1, a2 > + fgt.d a0, a1, a2 > + fge.d a0, a1, a2 > + fneg.d a0, a1 > + fabs.d a0, a1 > fclass.d a0, a1 > diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d > index d5499aa9131..3e99b766f5b 100644 > --- a/gas/testsuite/gas/riscv/zfinx.d > +++ b/gas/testsuite/gas/riscv/zfinx.d > @@ -1,5 +1,4 @@ > -#as: -march=rv64ima_zfinx > -#source: zfinx.s > +#as: -march=rv64i_zfinx > #objdump: -dr > > .*:[ ]+file format .* > @@ -8,24 +7,41 @@ Disassembly of section .text: > > 0+000 <target>: > [ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd.s[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+00c58553[ ]+fadd.s[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+08c58553[ ]+fsub.s[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+10c58553[ ]+fmul.s[ ]+a0,a1,a2,rne > [ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+18c58553[ ]+fdiv.s[ ]+a0,a1,a2,rne > +[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+58058553[ ]+fsqrt.s[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+68c58543[ ]+fmadd.s[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+68c5f54f[ ]+fnmadd.s[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+68c5854f[ ]+fnmadd.s[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+68c5f547[ ]+fmsub.s[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+68c58547[ ]+fmsub.s[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+68c5f54b[ ]+fnmsub.s[ ]+a0,a1,a2,a3 > +[ ]+[0-9a-f]+:[ ]+68c5854b[ ]+fnmsub.s[ ]+a0,a1,a2,a3,rne > [ ]+[0-9a-f]+:[ ]+c005f553[ ]+fcvt.w.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c0058553[ ]+fcvt.w.s[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c015f553[ ]+fcvt.wu.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c0158553[ ]+fcvt.wu.s[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c025f553[ ]+fcvt.l.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c0258553[ ]+fcvt.l.s[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+c035f553[ ]+fcvt.lu.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+c0358553[ ]+fcvt.lu.s[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d005f553[ ]+fcvt.s.w[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d0058553[ ]+fcvt.s.w[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d015f553[ ]+fcvt.s.wu[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d0158553[ ]+fcvt.s.wu[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d025f553[ ]+fcvt.s.l[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d0258553[ ]+fcvt.s.l[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+d035f553[ ]+fcvt.s.lu[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d0358553[ ]+fcvt.s.lu[ ]+a0,a1,rne > [ ]+[0-9a-f]+:[ ]+20c58553[ ]+fsgnj.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+20c59553[ ]+fsgnjn.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+20c5a553[ ]+fsgnjx.s[ ]+a0,a1,a2 > @@ -34,6 +50,6 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s > index af50490fadf..6687f3187ef 100644 > --- a/gas/testsuite/gas/riscv/zfinx.s > +++ b/gas/testsuite/gas/riscv/zfinx.s > @@ -1,31 +1,50 @@ > target: > fadd.s a0, a1, a2 > + fadd.s a0, a1, a2, rne > fsub.s a0, a1, a2 > + fsub.s a0, a1, a2, rne > fmul.s a0, a1, a2 > + fmul.s a0, a1, a2, rne > fdiv.s a0, a1, a2 > - fsqrt.s a0, a0 > + fdiv.s a0, a1, a2, rne > + fsqrt.s a0, a1 > + fsqrt.s a0, a1, rne > fmin.s a0, a1, a2 > fmax.s a0, a1, a2 > - fmadd.s a0, a1, a2, a3 > + fmadd.s a0, a1, a2, a3 > + fmadd.s a0, a1, a2, a3, rne > fnmadd.s a0, a1, a2, a3 > - fmsub.s a0, a1, a2, a3 > + fnmadd.s a0, a1, a2, a3, rne > + fmsub.s a0, a1, a2, a3 > + fmsub.s a0, a1, a2, a3, rne > fnmsub.s a0, a1, a2, a3 > + fnmsub.s a0, a1, a2, a3, rne > + > fcvt.w.s a0, a1 > + fcvt.w.s a0, a1, rne > fcvt.wu.s a0, a1 > + fcvt.wu.s a0, a1, rne > fcvt.l.s a0, a1 > + fcvt.l.s a0, a1, rne > fcvt.lu.s a0, a1 > + fcvt.lu.s a0, a1, rne > fcvt.s.w a0, a1 > + fcvt.s.w a0, a1, rne > fcvt.s.wu a0, a1 > + fcvt.s.wu a0, a1, rne > fcvt.s.l a0, a1 > + fcvt.s.l a0, a1, rne > fcvt.s.lu a0, a1 > - fsgnj.s a0, a1, a2 > + fcvt.s.lu a0, a1, rne > + > + fsgnj.s a0, a1, a2 > fsgnjn.s a0, a1, a2 > fsgnjx.s a0, a1, a2 > - feq.s a0, a1, a2 > - flt.s a0, a1, a2 > - fle.s a0, a1, a2 > - fgt.s a0, a1, a2 > - fge.s a0, a1, a2 > - fneg.s a0, a0 > - fabs.s a0, a0 > + feq.s a0, a1, a2 > + flt.s a0, a1, a2 > + fle.s a0, a1, a2 > + fgt.s a0, a1, a2 > + fge.s a0, a1, a2 > + fneg.s a0, a1 > + fabs.s a0, a1 > fclass.s a0, a1 > diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d > index c1a09201206..224bc827ad0 100644 > --- a/gas/testsuite/gas/riscv/zqinx.d > +++ b/gas/testsuite/gas/riscv/zqinx.d > @@ -1,5 +1,4 @@ > -#as: -march=rv64ima_zqinx > -#source: zqinx.s > +#as: -march=rv64i_zqinx > #objdump: -dr > > .*:[ ]+file format .* > @@ -7,37 +6,52 @@ > Disassembly of section .text: > > 0+000 <target>: > -[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne > +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne > +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne > +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne > +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne > +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne > +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne > +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne > +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne > +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 > diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s > index ba5179dc727..e4244a4277d 100644 > --- a/gas/testsuite/gas/riscv/zqinx.s > +++ b/gas/testsuite/gas/riscv/zqinx.s > @@ -1,35 +1,53 @@ > target: > - fadd.q a0, a1, a2 > - fsub.q a0, a1, a2 > - fmul.q a0, a1, a2 > - fdiv.q a0, a1, a2 > - fsqrt.q a0, a0 > - fmin.q a0, a1, a2 > - fmax.q a0, a1, a2 > - fmadd.q a0, a1, a2, a3 > - fnmadd.q a0, a1, a2, a3 > - fmsub.q a0, a1, a2, a3 > - fnmsub.q a0, a1, a2, a3 > - fcvt.w.q a0, a1 > - fcvt.wu.q a0, a1 > - fcvt.l.q a0, a1 > - fcvt.lu.q a0, a1 > - fcvt.s.q a0, a1 > - fcvt.d.q a0, a1 > - fcvt.q.s a0, a1 > - fcvt.q.d a0, a1 > - fcvt.q.w a0, a1 > - fcvt.q.wu a0, a1 > - fcvt.q.l a0, a1 > - fcvt.q.lu a0, a1 > - fsgnj.q a0, a1, a2 > - fsgnjn.q a0, a1, a2 > - fsgnjx.q a0, a1, a2 > - feq.q a0, a1, a2 > - flt.q a0, a1, a2 > - fle.q a0, a1, a2 > - fgt.q a0, a1, a2 > - fge.q a0, a1, a2 > - fneg.q a0, a0 > - fabs.q a0, a0 > - fclass.q a0, a1 > + fadd.q a0, a2, a4 > + fadd.q a0, a2, a4, rne > + fsub.q a0, a2, a4 > + fsub.q a0, a2, a4, rne > + fmul.q a0, a2, a4 > + fmul.q a0, a2, a4, rne > + fdiv.q a0, a2, a4 > + fdiv.q a0, a2, a4, rne > + fsqrt.q a0, a2 > + fsqrt.q a0, a2, rne > + fmin.q a0, a2, a4 > + fmax.q a0, a2, a4 > + fmadd.q a0, a2, a4, a6 > + fmadd.q a0, a2, a4, a6, rne > + fnmadd.q a0, a2, a4, a6 > + fnmadd.q a0, a2, a4, a6, rne > + fmsub.q a0, a2, a4, a6 > + fmsub.q a0, a2, a4, a6, rne > + fnmsub.q a0, a2, a4, a6 > + fnmsub.q a0, a2, a4, a6, rne > + > + fcvt.w.q a0, a2 > + fcvt.w.q a0, a2, rne > + fcvt.wu.q a0, a2 > + fcvt.wu.q a0, a2, rne > + fcvt.l.q a0, a2 > + fcvt.l.q a0, a2, rne > + fcvt.lu.q a0, a2 > + fcvt.lu.q a0, a2, rne > + fcvt.q.w a0, a2 > + fcvt.q.wu a0, a2 > + fcvt.q.l a0, a2 > + fcvt.q.lu a0, a2 > + > + fcvt.q.s a0, a2 > + fcvt.q.d a0, a2 > + fcvt.s.q a0, a2 > + fcvt.s.q a0, a2, rne > + fcvt.d.q a0, a2 > + fcvt.d.q a0, a2, rne > + > + fsgnj.q a0, a2, a4 > + fsgnjn.q a0, a2, a4 > + fsgnjx.q a0, a2, a4 > + feq.q a0, a2, a4 > + flt.q a0, a2, a4 > + fle.q a0, a2, a4 > + fgt.q a0, a2, a4 > + fge.q a0, a2, a4 > + fneg.q a0, a2 > + fabs.q a0, a2 > + fclass.q a0, a2 > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] RISC-V: Relax "fmv.[sdq]" requirements 2022-09-28 7:20 [PATCH 0/2] RISC-V: Zfinx-related improvements (testcases and fmv.[sdq]) - SPLITTED Tsukasa OI 2022-09-28 7:20 ` [PATCH 1/2] RISC-V: Reorganize and enhance 'Zfinx' tests Tsukasa OI @ 2022-09-28 7:20 ` Tsukasa OI 2022-09-30 15:06 ` Nelson Chu 1 sibling, 1 reply; 7+ messages in thread From: Tsukasa OI @ 2022-09-28 7:20 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils This commit relaxes requirements to "fmv.s" instructions from 'F' to ('F' or 'Zfinx'). The same applies to "fmv.d" and "fmv.q". Note that 'Zhinx' extension already contains "fmv.h" instruction (as well as 'Zfh'). gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Add "fmv.s" instruction. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Add "fmv.d" instruction. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.d: Add "fmv.q" instruction. * testsuite/gas/riscv/zqinx.s: Likewise. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Relax requirements to "fmv.[sdq]" instructions to support those in 'Zfinx'/'Zdinx'/'Zqinx'. --- gas/testsuite/gas/riscv/zdinx.d | 1 + gas/testsuite/gas/riscv/zdinx.s | 1 + gas/testsuite/gas/riscv/zfinx.d | 1 + gas/testsuite/gas/riscv/zfinx.s | 1 + gas/testsuite/gas/riscv/zqinx.d | 1 + gas/testsuite/gas/riscv/zqinx.s | 1 + opcodes/riscv-opc.c | 6 +++--- 7 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index d41c39b0304..18d3fa3c41c 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -51,6 +51,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index be9a47fa404..3cff27e1458 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -47,6 +47,7 @@ target: fle.d a0, a1, a2 fgt.d a0, a1, a2 fge.d a0, a1, a2 + fmv.d a0, a1 fneg.d a0, a1 fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index 3e99b766f5b..4fde02a7d68 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -50,6 +50,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index 6687f3187ef..327d0228c17 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -45,6 +45,7 @@ target: fle.s a0, a1, a2 fgt.s a0, a1, a2 fge.s a0, a1, a2 + fmv.s a0, a1 fneg.s a0, a1 fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index 224bc827ad0..28142654ca1 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -52,6 +52,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 [ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 [ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index e4244a4277d..84d045feb4d 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -48,6 +48,7 @@ target: fle.q a0, a2, a4 fgt.q a0, a2, a4 fge.q a0, a2, a4 + fmv.q a0, a2 fneg.q a0, a2 fabs.q a0, a2 fclass.q a0, a2 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 83fcc68c375..4d582de1f70 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -695,7 +695,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, -{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, @@ -753,7 +753,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, @@ -810,7 +810,7 @@ const struct riscv_opcode riscv_opcodes[] = {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] RISC-V: Relax "fmv.[sdq]" requirements 2022-09-28 7:20 ` [PATCH 2/2] RISC-V: Relax "fmv.[sdq]" requirements Tsukasa OI @ 2022-09-30 15:06 ` Nelson Chu 2022-09-30 15:39 ` Tsukasa OI 0 siblings, 1 reply; 7+ messages in thread From: Nelson Chu @ 2022-09-30 15:06 UTC (permalink / raw) To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils I think the patch was approved by Palmer before, he just mentioned some general issues, including the ISA spec doesn't define zqinx. So please commit. Thanks Nelson On Wed, Sep 28, 2022 at 3:20 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > > This commit relaxes requirements to "fmv.s" instructions from 'F' to ('F' > or 'Zfinx'). The same applies to "fmv.d" and "fmv.q". Note that 'Zhinx' > extension already contains "fmv.h" instruction (as well as 'Zfh'). > > gas/ChangeLog: > > * testsuite/gas/riscv/zfinx.s: Add "fmv.s" instruction. > * testsuite/gas/riscv/zfinx.d: Likewise. > * testsuite/gas/riscv/zdinx.s: Add "fmv.d" instruction. > * testsuite/gas/riscv/zdinx.d: Likewise. > * testsuite/gas/riscv/zqinx.d: Add "fmv.q" instruction. > * testsuite/gas/riscv/zqinx.s: Likewise. > > opcodes/ChangeLog: > > * riscv-opc.c (riscv_opcodes): Relax requirements to "fmv.[sdq]" > instructions to support those in 'Zfinx'/'Zdinx'/'Zqinx'. > --- > gas/testsuite/gas/riscv/zdinx.d | 1 + > gas/testsuite/gas/riscv/zdinx.s | 1 + > gas/testsuite/gas/riscv/zfinx.d | 1 + > gas/testsuite/gas/riscv/zfinx.s | 1 + > gas/testsuite/gas/riscv/zqinx.d | 1 + > gas/testsuite/gas/riscv/zqinx.s | 1 + > opcodes/riscv-opc.c | 6 +++--- > 7 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d > index d41c39b0304..18d3fa3c41c 100644 > --- a/gas/testsuite/gas/riscv/zdinx.d > +++ b/gas/testsuite/gas/riscv/zdinx.d > @@ -51,6 +51,7 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 > +[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s > index be9a47fa404..3cff27e1458 100644 > --- a/gas/testsuite/gas/riscv/zdinx.s > +++ b/gas/testsuite/gas/riscv/zdinx.s > @@ -47,6 +47,7 @@ target: > fle.d a0, a1, a2 > fgt.d a0, a1, a2 > fge.d a0, a1, a2 > + fmv.d a0, a1 > fneg.d a0, a1 > fabs.d a0, a1 > fclass.d a0, a1 > diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d > index 3e99b766f5b..4fde02a7d68 100644 > --- a/gas/testsuite/gas/riscv/zfinx.d > +++ b/gas/testsuite/gas/riscv/zfinx.d > @@ -50,6 +50,7 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 > +[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s > index 6687f3187ef..327d0228c17 100644 > --- a/gas/testsuite/gas/riscv/zfinx.s > +++ b/gas/testsuite/gas/riscv/zfinx.s > @@ -45,6 +45,7 @@ target: > fle.s a0, a1, a2 > fgt.s a0, a1, a2 > fge.s a0, a1, a2 > + fmv.s a0, a1 > fneg.s a0, a1 > fabs.s a0, a1 > fclass.s a0, a1 > diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d > index 224bc827ad0..28142654ca1 100644 > --- a/gas/testsuite/gas/riscv/zqinx.d > +++ b/gas/testsuite/gas/riscv/zqinx.d > @@ -52,6 +52,7 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 > [ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 > [ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 > [ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 > [ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 > [ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 > diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s > index e4244a4277d..84d045feb4d 100644 > --- a/gas/testsuite/gas/riscv/zqinx.s > +++ b/gas/testsuite/gas/riscv/zqinx.s > @@ -48,6 +48,7 @@ target: > fle.q a0, a2, a4 > fgt.q a0, a2, a4 > fge.q a0, a2, a4 > + fmv.q a0, a2 > fneg.q a0, a2 > fabs.q a0, a2 > fclass.q a0, a2 > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 83fcc68c375..4d582de1f70 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -695,7 +695,7 @@ const struct riscv_opcode riscv_opcodes[] = > {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, > {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, > {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, > -{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, > +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, > {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, > {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, > {"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, > @@ -753,7 +753,7 @@ const struct riscv_opcode riscv_opcodes[] = > {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, > {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, > {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, > -{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, > +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, > {"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, > {"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, > {"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, > @@ -810,7 +810,7 @@ const struct riscv_opcode riscv_opcodes[] = > {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, > {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, > {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, > -{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, > +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, > {"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, > {"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, > {"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] RISC-V: Relax "fmv.[sdq]" requirements 2022-09-30 15:06 ` Nelson Chu @ 2022-09-30 15:39 ` Tsukasa OI 0 siblings, 0 replies; 7+ messages in thread From: Tsukasa OI @ 2022-09-30 15:39 UTC (permalink / raw) To: Nelson Chu; +Cc: Kito Cheng, Palmer Dabbelt, binutils On 2022/10/01 0:06, Nelson Chu wrote: > I think the patch was approved by Palmer before, he just mentioned > some general issues, including the ISA spec doesn't define zqinx. So > please commit. > > Thanks > Nelson Thanks a lot! For register pair validation, it is found to be good to have a common framework for both 'Z[dq]inx' and 'Zpsfoperand' (a part of 'P' extension proposal). I'll submit a RFC PATCH of common framework tomorrow. > > On Wed, Sep 28, 2022 at 3:20 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: >> >> This commit relaxes requirements to "fmv.s" instructions from 'F' to ('F' >> or 'Zfinx'). The same applies to "fmv.d" and "fmv.q". Note that 'Zhinx' >> extension already contains "fmv.h" instruction (as well as 'Zfh'). >> >> gas/ChangeLog: >> >> * testsuite/gas/riscv/zfinx.s: Add "fmv.s" instruction. >> * testsuite/gas/riscv/zfinx.d: Likewise. >> * testsuite/gas/riscv/zdinx.s: Add "fmv.d" instruction. >> * testsuite/gas/riscv/zdinx.d: Likewise. >> * testsuite/gas/riscv/zqinx.d: Add "fmv.q" instruction. >> * testsuite/gas/riscv/zqinx.s: Likewise. >> >> opcodes/ChangeLog: >> >> * riscv-opc.c (riscv_opcodes): Relax requirements to "fmv.[sdq]" >> instructions to support those in 'Zfinx'/'Zdinx'/'Zqinx'. >> --- >> gas/testsuite/gas/riscv/zdinx.d | 1 + >> gas/testsuite/gas/riscv/zdinx.s | 1 + >> gas/testsuite/gas/riscv/zfinx.d | 1 + >> gas/testsuite/gas/riscv/zfinx.s | 1 + >> gas/testsuite/gas/riscv/zqinx.d | 1 + >> gas/testsuite/gas/riscv/zqinx.s | 1 + >> opcodes/riscv-opc.c | 6 +++--- >> 7 files changed, 9 insertions(+), 3 deletions(-) >> >> diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d >> index d41c39b0304..18d3fa3c41c 100644 >> --- a/gas/testsuite/gas/riscv/zdinx.d >> +++ b/gas/testsuite/gas/riscv/zdinx.d >> @@ -51,6 +51,7 @@ Disassembly of section .text: >> [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 >> [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 >> [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 >> +[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 >> diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s >> index be9a47fa404..3cff27e1458 100644 >> --- a/gas/testsuite/gas/riscv/zdinx.s >> +++ b/gas/testsuite/gas/riscv/zdinx.s >> @@ -47,6 +47,7 @@ target: >> fle.d a0, a1, a2 >> fgt.d a0, a1, a2 >> fge.d a0, a1, a2 >> + fmv.d a0, a1 >> fneg.d a0, a1 >> fabs.d a0, a1 >> fclass.d a0, a1 >> diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d >> index 3e99b766f5b..4fde02a7d68 100644 >> --- a/gas/testsuite/gas/riscv/zfinx.d >> +++ b/gas/testsuite/gas/riscv/zfinx.d >> @@ -50,6 +50,7 @@ Disassembly of section .text: >> [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 >> [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 >> [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 >> +[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 >> diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s >> index 6687f3187ef..327d0228c17 100644 >> --- a/gas/testsuite/gas/riscv/zfinx.s >> +++ b/gas/testsuite/gas/riscv/zfinx.s >> @@ -45,6 +45,7 @@ target: >> fle.s a0, a1, a2 >> fgt.s a0, a1, a2 >> fge.s a0, a1, a2 >> + fmv.s a0, a1 >> fneg.s a0, a1 >> fabs.s a0, a1 >> fclass.s a0, a1 >> diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d >> index 224bc827ad0..28142654ca1 100644 >> --- a/gas/testsuite/gas/riscv/zqinx.d >> +++ b/gas/testsuite/gas/riscv/zqinx.d >> @@ -52,6 +52,7 @@ Disassembly of section .text: >> [ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 >> [ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 >> [ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 >> +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 >> [ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 >> [ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 >> [ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 >> diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s >> index e4244a4277d..84d045feb4d 100644 >> --- a/gas/testsuite/gas/riscv/zqinx.s >> +++ b/gas/testsuite/gas/riscv/zqinx.s >> @@ -48,6 +48,7 @@ target: >> fle.q a0, a2, a4 >> fgt.q a0, a2, a4 >> fge.q a0, a2, a4 >> + fmv.q a0, a2 >> fneg.q a0, a2 >> fabs.q a0, a2 >> fclass.q a0, a2 >> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c >> index 83fcc68c375..4d582de1f70 100644 >> --- a/opcodes/riscv-opc.c >> +++ b/opcodes/riscv-opc.c >> @@ -695,7 +695,7 @@ const struct riscv_opcode riscv_opcodes[] = >> {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, >> {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, >> {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, >> -{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, >> +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, >> @@ -753,7 +753,7 @@ const struct riscv_opcode riscv_opcodes[] = >> {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, >> {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, >> {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, >> -{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, >> +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, >> @@ -810,7 +810,7 @@ const struct riscv_opcode riscv_opcodes[] = >> {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, >> {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, >> {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, >> -{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, >> +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, >> -- >> 2.34.1 >> > ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-09-30 15:39 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-09-28 7:20 [PATCH 0/2] RISC-V: Zfinx-related improvements (testcases and fmv.[sdq]) - SPLITTED Tsukasa OI 2022-09-28 7:20 ` [PATCH 1/2] RISC-V: Reorganize and enhance 'Zfinx' tests Tsukasa OI 2022-09-30 7:52 ` jiawei 2022-09-30 14:57 ` Nelson Chu 2022-09-28 7:20 ` [PATCH 2/2] RISC-V: Relax "fmv.[sdq]" requirements Tsukasa OI 2022-09-30 15:06 ` Nelson Chu 2022-09-30 15:39 ` Tsukasa OI
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).