[PATCH 0/2] x86-64: immediate insn operand fixes

[PATCH 0/2] x86-64: immediate insn operand fixes

[Jan Beulich]

While looking into fixing PR gas/30856, I noticed another issue
in neighboring code. Hence two fixes.

1: fix suffix-less PUSH of symbol address
2: REX.W overrides DATA_PREFIX

Jan

[PATCH 1/2] x86-64: fix suffix-less PUSH of symbol address

[Jan Beulich]

PR gas/30856

In 5cc007751cdb ("x86: further adjust extend-to-32bit-address
conditions") I neglected the case of PUSH, which is the only insn
allowing (proper) symbol addresses to be used as immediates (not
displacements, like CALL/JMP) in the absence of any register operands.
Since it defaults to 64-bit operand size, guessing an L suffix is wrong
there.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6214,7 +6214,12 @@ optimize_imm (void)
     }
   else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
     guess_suffix = WORD_MNEM_SUFFIX;
-  else if (flag_code != CODE_64BIT || !(i.prefix[REX_PREFIX] & REX_W))
+  else if (flag_code != CODE_64BIT
+	   || (!(i.prefix[REX_PREFIX] & REX_W)
+	       /* A more generic (but also more involved) way of dealing
+		  with the special case(s) would be to go look for
+		  DefaultSize attributes on any of the templates.  */
+	       && current_templates->start->mnem_off != MN_push))
     guess_suffix = LONG_MNEM_SUFFIX;
 
   for (op = i.operands; --op >= 0;)
--- a/gas/testsuite/gas/i386/immed64.d
+++ b/gas/testsuite/gas/i386/immed64.d
@@ -24,6 +24,12 @@ Disassembly of section \.text:
 [ 	]*[0-9a-fA-F]+:[ 	]+48 b8 04 00 00 00 00 00 00 00[ 	]+movabsq? +\$0x4,%rax
 [ 	]*[0-9a-fA-F]+:[ 	]+48 b8 08 00 00 00 00 00 00 00[ 	]+movabsq? +\$0x8,%rax
 [ 	]*[0-9a-fA-F]+:[ 	]+48 b8 00 00 00 00 00 00 00 00[ 	]+movabsq? +\$0x0,%rax
+[ 	]*[0-9a-fA-F]+:[ 	]+6a 04[ 	]+pushq? +\$0x4
+[ 	]*[0-9a-fA-F]+:[ 	]+68 08 00 00 00[ 	]+pushq? +\$0x8
+[ 	]*[0-9a-fA-F]+:[ 	]+66 6a 04[ 	]+pushw +\$0x4
+[ 	]*[0-9a-fA-F]+:[ 	]+66 68 08 00[ 	]+pushw +\$0x8
+[ 	]*[0-9a-fA-F]+:[ 	]+6a 04[ 	]+pushq? +\$0x4
+[ 	]*[0-9a-fA-F]+:[ 	]+68 08 00 00 00[ 	]+pushq? +\$0x8
 [ 	]*[0-9a-fA-F]+:[ 	]+04 04[ 	]+addb? +\$0x4,%al
 [ 	]*[0-9a-fA-F]+:[ 	]+04 08[ 	]+addb? +\$0x8,%al
 [ 	]*[0-9a-fA-F]+:[ 	]+04 00[ 	]+addb? +\$0x0,%al
--- a/gas/testsuite/gas/i386/immed64.s
+++ b/gas/testsuite/gas/i386/immed64.s
@@ -19,6 +19,12 @@ _start:
 	movabsq	$early, %rax
 	movabsq	$late, %rax
 	movabsq	$xtrn, %rax
+	pushq	$early
+	pushq	$late
+	pushw	$early
+	pushw	$late
+	push	$early
+	push	$late
 	addb	$early, %al
 	addb	$late, %al
 	addb	$xtrn, %al

[PATCH 2/2] x86-64: REX.W overrides DATA_PREFIX

[Jan Beulich]

REX.W needs to be respected when immediate size and relocation type are
determined.
---
Looks like similar issues exist in displacement processing, but that'll
want to be dealt with separately.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6212,7 +6212,8 @@ optimize_imm (void)
 	    break;
 	  }
     }
-  else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
+  else if ((flag_code == CODE_16BIT)
+	    ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W)))
     guess_suffix = WORD_MNEM_SUFFIX;
   else if (flag_code != CODE_64BIT
 	   || (!(i.prefix[REX_PREFIX] & REX_W)
@@ -8186,7 +8187,8 @@ update_imm (unsigned int j)
 	       || operand_type_equal (&overlap, &imm16_32)
 	       || operand_type_equal (&overlap, &imm16_32s))
 	{
-	  if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
+	  if ((flag_code == CODE_16BIT)
+	      ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W)))
 	    overlap = imm16;
 	  else
 	    overlap = imm32s;
@@ -10426,6 +10428,7 @@ output_imm (fragS *insn_start_frag, offs
 	      if (i.types[n].bitfield.imm32s
 		  && (i.suffix == QWORD_MNEM_SUFFIX
 		      || (!i.suffix && i.tm.opcode_modifier.no_lsuf)
+		      || (i.prefix[REX_PREFIX] & REX_W)
 		      || dot_insn ()))
 		sign = 1;
 	      else