Re: P.S. Follow up to my last post

[Palmer Dabbelt <palmer@dabbelt.com>]

On Fri, 25 Aug 2023 07:12:39 PDT (-0700), jacob@jacob.remcomp.fr wrote:
> OF COURSE « march » is mentioned. But -march=rv64gc_zbb is NOT.
>
> Where please give me a link) that option is mentioned?
>
> It is NOT mentioned in
>
> https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html

The "-march" argument is documented int the "-march" section of the 
argument documentation, specifically:

    -march=ISA-string
	Generate code for given RISC-V ISA (e.g. ‘rv64im’). ISA strings 
	must be lower-case. Examples include ‘rv64i’, ‘rv32g’, ‘rv32e’, 
	and ‘rv32imaf’.
        
        When -march= is not specified, use the setting from -mcpu.
        
	If both -march and -mcpu= are not specified, the default for 
	this argument is system dependent, users who want a specific 
	architecture extensions should specify one explicitly.

Pretty much every port has a "-march" argument to control the subtarget 
to generate code for.  It's true that the GCC docs for RISC-V's -march 
should be improved (there's even an unfinished patch out to do it, 
you're more than welcome to finish it), but the argument itself is 
definately documented.

Those are all GCC problems, though.  I suppose we could improve the 
binutils -march documentation as well, it'd essentially just be a 
duplicate of the GCC docs (aside from some quirks like Zihintpause).

> The idea that the compiler could figure out the processor it is running on it is completely far fetched isn’t it?
>
> Jacob
>
>
>
>> Le 25 août 2023 à 15:07, jacob navia <jacob@jacob.remcomp.fr> a écrit :
>> 
>> OK, there is no bug, I didn’t expect anything else.
>> 
>> SO:
>> 
>> To use all the instruction of the processor he/she is running on, the user should:
>> 
>> 1)Be aware that gcc doesn’t see crucial instructions of the processor by verifying its assembler output.
>> 
>> 2) Be aware that there is an (undocumented) option -march… that will enable the assembler and the compiler to generate all the instructions of the current processor.
>> 
>> Well, there is NO BUG!
>> 
>> This is by design then.
>> 
>> Thank you very much.
>> 
>> Jacob
>> 
>> 
>> 
>>> Le 25 août 2023 à 14:00, Jan Beulich <jbeulich@suse.com> a écrit :
>>> 
>>> On 25.08.2023 13:52, jacob navia wrote:
>>>> The lack of the Ebb instructions is CRUCIAL for performance when accessing tables / arrays!
>>>> This instructions allow to combine an addition and a shift by 1, 2 or 3, to access tables of shorts, ints or doubles.
>>>> This speeds up the access to tables enormously and would allow gcc to generate much better code.
>>> 
>>> Since you're writing to binutils@, you may want to also mention what gas
>>> bug you think you see. So far (also in the other mail) you've talked of
>>> only gcc. If you meant to say that like in gcc you need to enable use of
>>> the instructions in gas, then yes, that's the way the RISC-V assembler
>>> works (like e.g. also the PPC one, but unlike e.g. the x86 one).
>>> 
>>> Jan
>>