Re: [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding

[Palmer Dabbelt <palmer@dabbelt.com>]

On Fri, 16 Dec 2022 10:59:53 PST (-0800), christoph.muellner@vrull.eu wrote:
> On Fri, Dec 16, 2022 at 7:56 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
>> On Fri, 16 Dec 2022 10:51:33 PST (-0800), christoph.muellner@vrull.eu
>> wrote:
>> > From: Christoph Müllner <christoph.muellner@vrull.eu>
>> >
>> > A recent change in the XTheadFmv spec fixed an encoding bug in the
>> > document. This patch changes the code to follow this bugfix.
>> >
>> > Spec patch can be found here:
>> >   https://github.com/T-head-Semi/thead-extension-spec/pull/11
>>
>> There's not much info in there.  Was this just a bug in the ISA manual?
>> In other words, does the existing hardware (I know of at least C906s and
>> C910s in the wild) behave the new way already?  In that case
>>
>
> Yes, this was just a bug in the ISA manual, which slipped through the
> review.
> The manual now matches the implementation.

OK, thanks!

>
>
>
>>
>> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>>
>> but if the hardware has the old behavior then we'll need to do something
>> more complicated to avoid breaking compatibility.
>>
>> >
>> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
>> > ---
>> >  gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
>> >  include/opcode/riscv-opc.h            | 4 ++--
>> >  2 files changed, 4 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d
>> b/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > index f2bbe010beb..af8ce0c8ee0 100644
>> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > @@ -7,5 +7,5 @@
>> >  Disassembly of section .text:
>> >
>> >  0+000 <target>:
>> > -[    ]+[0-9a-f]+:[   ]+6005950b[     ]+th.fmv.hw.x[  ]+a0,fa1
>> > -[    ]+[0-9a-f]+:[   ]+5005158b[     ]+th.fmv.x.hw[  ]+a1,fa0
>> > +[    ]+[0-9a-f]+:[   ]+5005950b[     ]+th.fmv.hw.x[  ]+a0,fa1
>> > +[    ]+[0-9a-f]+:[   ]+6005158b[     ]+th.fmv.x.hw[  ]+a1,fa0
>> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> > index 06e3df0f5a6..5420bfac91b 100644
>> > --- a/include/opcode/riscv-opc.h
>> > +++ b/include/opcode/riscv-opc.h
>> > @@ -2209,9 +2209,9 @@
>> >  #define MATCH_TH_FSURW 0x5000700b
>> >  #define MASK_TH_FSURW 0xf800707f
>> >  /* Vendor-specific (T-Head) XTheadFmv instructions. */
>> > -#define MATCH_TH_FMV_HW_X 0x6000100b
>> > +#define MATCH_TH_FMV_HW_X 0x5000100b
>> >  #define MASK_TH_FMV_HW_X 0xfff0707f
>> > -#define MATCH_TH_FMV_X_HW 0x5000100b
>> > +#define MATCH_TH_FMV_X_HW 0x6000100b
>> >  #define MASK_TH_FMV_X_HW 0xfff0707f
>> >  /* Vendor-specific (T-Head) XTheadInt instructions. */
>> >  #define MATCH_TH_IPOP 0x0050000b
>>