* [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding
@ 2022-12-16 18:51 Christoph Muellner
2022-12-16 18:56 ` Palmer Dabbelt
0 siblings, 1 reply; 7+ messages in thread
From: Christoph Muellner @ 2022-12-16 18:51 UTC (permalink / raw)
To: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Tsukasa OI, Philipp Tomsich, Cooper Qu, Lifang Xia,
Yunhai Shang, Zhiwei Liu
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
A recent change in the XTheadFmv spec fixed an encoding bug in the
document. This patch changes the code to follow this bugfix.
Spec patch can be found here:
https://github.com/T-head-Semi/thead-extension-spec/pull/11
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
include/opcode/riscv-opc.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d b/gas/testsuite/gas/riscv/x-thead-fmv.d
index f2bbe010beb..af8ce0c8ee0 100644
--- a/gas/testsuite/gas/riscv/x-thead-fmv.d
+++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
@@ -7,5 +7,5 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
-[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
+[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
+[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 06e3df0f5a6..5420bfac91b 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2209,9 +2209,9 @@
#define MATCH_TH_FSURW 0x5000700b
#define MASK_TH_FSURW 0xf800707f
/* Vendor-specific (T-Head) XTheadFmv instructions. */
-#define MATCH_TH_FMV_HW_X 0x6000100b
+#define MATCH_TH_FMV_HW_X 0x5000100b
#define MASK_TH_FMV_HW_X 0xfff0707f
-#define MATCH_TH_FMV_X_HW 0x5000100b
+#define MATCH_TH_FMV_X_HW 0x6000100b
#define MASK_TH_FMV_X_HW 0xfff0707f
/* Vendor-specific (T-Head) XTheadInt instructions. */
#define MATCH_TH_IPOP 0x0050000b
--
2.38.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding
2022-12-16 18:51 [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding Christoph Muellner
@ 2022-12-16 18:56 ` Palmer Dabbelt
2022-12-16 18:59 ` Christoph Müllner
0 siblings, 1 reply; 7+ messages in thread
From: Palmer Dabbelt @ 2022-12-16 18:56 UTC (permalink / raw)
To: christoph.muellner
Cc: binutils, nelson, Andrew Waterman, Jim Wilson, research_trasio,
philipp.tomsich, cooper.qu, lifang_xia, yunhai, zhiwei_liu,
christoph.muellner
On Fri, 16 Dec 2022 10:51:33 PST (-0800), christoph.muellner@vrull.eu wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> A recent change in the XTheadFmv spec fixed an encoding bug in the
> document. This patch changes the code to follow this bugfix.
>
> Spec patch can be found here:
> https://github.com/T-head-Semi/thead-extension-spec/pull/11
There's not much info in there. Was this just a bug in the ISA manual?
In other words, does the existing hardware (I know of at least C906s and
C910s in the wild) behave the new way already? In that case
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
but if the hardware has the old behavior then we'll need to do something
more complicated to avoid breaking compatibility.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
> include/opcode/riscv-opc.h | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d b/gas/testsuite/gas/riscv/x-thead-fmv.d
> index f2bbe010beb..af8ce0c8ee0 100644
> --- a/gas/testsuite/gas/riscv/x-thead-fmv.d
> +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
> @@ -7,5 +7,5 @@
> Disassembly of section .text:
>
> 0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
> -[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> +[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
> +[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 06e3df0f5a6..5420bfac91b 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2209,9 +2209,9 @@
> #define MATCH_TH_FSURW 0x5000700b
> #define MASK_TH_FSURW 0xf800707f
> /* Vendor-specific (T-Head) XTheadFmv instructions. */
> -#define MATCH_TH_FMV_HW_X 0x6000100b
> +#define MATCH_TH_FMV_HW_X 0x5000100b
> #define MASK_TH_FMV_HW_X 0xfff0707f
> -#define MATCH_TH_FMV_X_HW 0x5000100b
> +#define MATCH_TH_FMV_X_HW 0x6000100b
> #define MASK_TH_FMV_X_HW 0xfff0707f
> /* Vendor-specific (T-Head) XTheadInt instructions. */
> #define MATCH_TH_IPOP 0x0050000b
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding
2022-12-16 18:56 ` Palmer Dabbelt
@ 2022-12-16 18:59 ` Christoph Müllner
2022-12-16 19:00 ` Palmer Dabbelt
0 siblings, 1 reply; 7+ messages in thread
From: Christoph Müllner @ 2022-12-16 18:59 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: binutils, nelson, Andrew Waterman, Jim Wilson, research_trasio,
philipp.tomsich, cooper.qu, lifang_xia, yunhai, zhiwei_liu
[-- Attachment #1: Type: text/plain, Size: 2579 bytes --]
On Fri, Dec 16, 2022 at 7:56 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> On Fri, 16 Dec 2022 10:51:33 PST (-0800), christoph.muellner@vrull.eu
> wrote:
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > A recent change in the XTheadFmv spec fixed an encoding bug in the
> > document. This patch changes the code to follow this bugfix.
> >
> > Spec patch can be found here:
> > https://github.com/T-head-Semi/thead-extension-spec/pull/11
>
> There's not much info in there. Was this just a bug in the ISA manual?
> In other words, does the existing hardware (I know of at least C906s and
> C910s in the wild) behave the new way already? In that case
>
Yes, this was just a bug in the ISA manual, which slipped through the
review.
The manual now matches the implementation.
>
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> but if the hardware has the old behavior then we'll need to do something
> more complicated to avoid breaking compatibility.
>
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> > gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
> > include/opcode/riscv-opc.h | 4 ++--
> > 2 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d
> b/gas/testsuite/gas/riscv/x-thead-fmv.d
> > index f2bbe010beb..af8ce0c8ee0 100644
> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.d
> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
> > @@ -7,5 +7,5 @@
> > Disassembly of section .text:
> >
> > 0+000 <target>:
> > -[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
> > -[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> > +[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
> > +[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> > index 06e3df0f5a6..5420bfac91b 100644
> > --- a/include/opcode/riscv-opc.h
> > +++ b/include/opcode/riscv-opc.h
> > @@ -2209,9 +2209,9 @@
> > #define MATCH_TH_FSURW 0x5000700b
> > #define MASK_TH_FSURW 0xf800707f
> > /* Vendor-specific (T-Head) XTheadFmv instructions. */
> > -#define MATCH_TH_FMV_HW_X 0x6000100b
> > +#define MATCH_TH_FMV_HW_X 0x5000100b
> > #define MASK_TH_FMV_HW_X 0xfff0707f
> > -#define MATCH_TH_FMV_X_HW 0x5000100b
> > +#define MATCH_TH_FMV_X_HW 0x6000100b
> > #define MASK_TH_FMV_X_HW 0xfff0707f
> > /* Vendor-specific (T-Head) XTheadInt instructions. */
> > #define MATCH_TH_IPOP 0x0050000b
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding
2022-12-16 18:59 ` Christoph Müllner
@ 2022-12-16 19:00 ` Palmer Dabbelt
2022-12-22 1:50 ` [Offline] " Nelson Chu
0 siblings, 1 reply; 7+ messages in thread
From: Palmer Dabbelt @ 2022-12-16 19:00 UTC (permalink / raw)
To: christoph.muellner
Cc: binutils, nelson, Andrew Waterman, Jim Wilson, research_trasio,
philipp.tomsich, cooper.qu, lifang_xia, yunhai, zhiwei_liu
On Fri, 16 Dec 2022 10:59:53 PST (-0800), christoph.muellner@vrull.eu wrote:
> On Fri, Dec 16, 2022 at 7:56 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
>> On Fri, 16 Dec 2022 10:51:33 PST (-0800), christoph.muellner@vrull.eu
>> wrote:
>> > From: Christoph Müllner <christoph.muellner@vrull.eu>
>> >
>> > A recent change in the XTheadFmv spec fixed an encoding bug in the
>> > document. This patch changes the code to follow this bugfix.
>> >
>> > Spec patch can be found here:
>> > https://github.com/T-head-Semi/thead-extension-spec/pull/11
>>
>> There's not much info in there. Was this just a bug in the ISA manual?
>> In other words, does the existing hardware (I know of at least C906s and
>> C910s in the wild) behave the new way already? In that case
>>
>
> Yes, this was just a bug in the ISA manual, which slipped through the
> review.
> The manual now matches the implementation.
OK, thanks!
>
>
>
>>
>> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>>
>> but if the hardware has the old behavior then we'll need to do something
>> more complicated to avoid breaking compatibility.
>>
>> >
>> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
>> > ---
>> > gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
>> > include/opcode/riscv-opc.h | 4 ++--
>> > 2 files changed, 4 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d
>> b/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > index f2bbe010beb..af8ce0c8ee0 100644
>> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > @@ -7,5 +7,5 @@
>> > Disassembly of section .text:
>> >
>> > 0+000 <target>:
>> > -[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
>> > -[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
>> > +[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
>> > +[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
>> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> > index 06e3df0f5a6..5420bfac91b 100644
>> > --- a/include/opcode/riscv-opc.h
>> > +++ b/include/opcode/riscv-opc.h
>> > @@ -2209,9 +2209,9 @@
>> > #define MATCH_TH_FSURW 0x5000700b
>> > #define MASK_TH_FSURW 0xf800707f
>> > /* Vendor-specific (T-Head) XTheadFmv instructions. */
>> > -#define MATCH_TH_FMV_HW_X 0x6000100b
>> > +#define MATCH_TH_FMV_HW_X 0x5000100b
>> > #define MASK_TH_FMV_HW_X 0xfff0707f
>> > -#define MATCH_TH_FMV_X_HW 0x5000100b
>> > +#define MATCH_TH_FMV_X_HW 0x6000100b
>> > #define MASK_TH_FMV_X_HW 0xfff0707f
>> > /* Vendor-specific (T-Head) XTheadInt instructions. */
>> > #define MATCH_TH_IPOP 0x0050000b
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Offline] Re: [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding
2022-12-16 19:00 ` Palmer Dabbelt
@ 2022-12-22 1:50 ` Nelson Chu
2022-12-27 19:45 ` Philipp Tomsich
0 siblings, 1 reply; 7+ messages in thread
From: Nelson Chu @ 2022-12-22 1:50 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Christoph Müllner, Binutils, Andrew Waterman,
Philipp Tomsich, Lifang Xia
Do we expect this in the 2.40 release? I haven't seen this in master for now.
Thanks
Nelson
On Sat, Dec 17, 2022 at 3:00 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Fri, 16 Dec 2022 10:59:53 PST (-0800), christoph.muellner@vrull.eu wrote:
> > On Fri, Dec 16, 2022 at 7:56 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> >
> >> On Fri, 16 Dec 2022 10:51:33 PST (-0800), christoph.muellner@vrull.eu
> >> wrote:
> >> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >> >
> >> > A recent change in the XTheadFmv spec fixed an encoding bug in the
> >> > document. This patch changes the code to follow this bugfix.
> >> >
> >> > Spec patch can be found here:
> >> > https://github.com/T-head-Semi/thead-extension-spec/pull/11
> >>
> >> There's not much info in there. Was this just a bug in the ISA manual?
> >> In other words, does the existing hardware (I know of at least C906s and
> >> C910s in the wild) behave the new way already? In that case
> >>
> >
> > Yes, this was just a bug in the ISA manual, which slipped through the
> > review.
> > The manual now matches the implementation.
>
> OK, thanks!
>
> >
> >
> >
> >>
> >> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
> >>
> >> but if the hardware has the old behavior then we'll need to do something
> >> more complicated to avoid breaking compatibility.
> >>
> >> >
> >> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> >> > ---
> >> > gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
> >> > include/opcode/riscv-opc.h | 4 ++--
> >> > 2 files changed, 4 insertions(+), 4 deletions(-)
> >> >
> >> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d
> >> b/gas/testsuite/gas/riscv/x-thead-fmv.d
> >> > index f2bbe010beb..af8ce0c8ee0 100644
> >> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.d
> >> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
> >> > @@ -7,5 +7,5 @@
> >> > Disassembly of section .text:
> >> >
> >> > 0+000 <target>:
> >> > -[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
> >> > -[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> >> > +[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
> >> > +[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> >> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> >> > index 06e3df0f5a6..5420bfac91b 100644
> >> > --- a/include/opcode/riscv-opc.h
> >> > +++ b/include/opcode/riscv-opc.h
> >> > @@ -2209,9 +2209,9 @@
> >> > #define MATCH_TH_FSURW 0x5000700b
> >> > #define MASK_TH_FSURW 0xf800707f
> >> > /* Vendor-specific (T-Head) XTheadFmv instructions. */
> >> > -#define MATCH_TH_FMV_HW_X 0x6000100b
> >> > +#define MATCH_TH_FMV_HW_X 0x5000100b
> >> > #define MASK_TH_FMV_HW_X 0xfff0707f
> >> > -#define MATCH_TH_FMV_X_HW 0x5000100b
> >> > +#define MATCH_TH_FMV_X_HW 0x6000100b
> >> > #define MASK_TH_FMV_X_HW 0xfff0707f
> >> > /* Vendor-specific (T-Head) XTheadInt instructions. */
> >> > #define MATCH_TH_IPOP 0x0050000b
> >>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Offline] Re: [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding
2022-12-22 1:50 ` [Offline] " Nelson Chu
@ 2022-12-27 19:45 ` Philipp Tomsich
2022-12-28 1:08 ` Nelson Chu
0 siblings, 1 reply; 7+ messages in thread
From: Philipp Tomsich @ 2022-12-27 19:45 UTC (permalink / raw)
To: Nelson Chu
Cc: Palmer Dabbelt, Christoph Müllner, Binutils,
Andrew Waterman, Lifang Xia
[-- Attachment #1: Type: text/plain, Size: 3463 bytes --]
Nelson,
I had missed the OK on this one as I had been traveling for RISC-V Summit
and now took care of it.
Applied to master, thanks!
Philipp.
On Thu, 22 Dec 2022 at 02:51, Nelson Chu <nelson@rivosinc.com> wrote:
> Do we expect this in the 2.40 release? I haven't seen this in master for
> now.
>
> Thanks
> Nelson
>
> On Sat, Dec 17, 2022 at 3:00 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> >
> > On Fri, 16 Dec 2022 10:59:53 PST (-0800), christoph.muellner@vrull.eu
> wrote:
> > > On Fri, Dec 16, 2022 at 7:56 PM Palmer Dabbelt <palmer@dabbelt.com>
> wrote:
> > >
> > >> On Fri, 16 Dec 2022 10:51:33 PST (-0800), christoph.muellner@vrull.eu
> > >> wrote:
> > >> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> > >> >
> > >> > A recent change in the XTheadFmv spec fixed an encoding bug in the
> > >> > document. This patch changes the code to follow this bugfix.
> > >> >
> > >> > Spec patch can be found here:
> > >> > https://github.com/T-head-Semi/thead-extension-spec/pull/11
> > >>
> > >> There's not much info in there. Was this just a bug in the ISA
> manual?
> > >> In other words, does the existing hardware (I know of at least C906s
> and
> > >> C910s in the wild) behave the new way already? In that case
> > >>
> > >
> > > Yes, this was just a bug in the ISA manual, which slipped through the
> > > review.
> > > The manual now matches the implementation.
> >
> > OK, thanks!
> >
> > >
> > >
> > >
> > >>
> > >> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
> > >>
> > >> but if the hardware has the old behavior then we'll need to do
> something
> > >> more complicated to avoid breaking compatibility.
> > >>
> > >> >
> > >> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > >> > ---
> > >> > gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
> > >> > include/opcode/riscv-opc.h | 4 ++--
> > >> > 2 files changed, 4 insertions(+), 4 deletions(-)
> > >> >
> > >> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d
> > >> b/gas/testsuite/gas/riscv/x-thead-fmv.d
> > >> > index f2bbe010beb..af8ce0c8ee0 100644
> > >> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.d
> > >> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
> > >> > @@ -7,5 +7,5 @@
> > >> > Disassembly of section .text:
> > >> >
> > >> > 0+000 <target>:
> > >> > -[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
> > >> > -[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> > >> > +[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
> > >> > +[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> > >> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> > >> > index 06e3df0f5a6..5420bfac91b 100644
> > >> > --- a/include/opcode/riscv-opc.h
> > >> > +++ b/include/opcode/riscv-opc.h
> > >> > @@ -2209,9 +2209,9 @@
> > >> > #define MATCH_TH_FSURW 0x5000700b
> > >> > #define MASK_TH_FSURW 0xf800707f
> > >> > /* Vendor-specific (T-Head) XTheadFmv instructions. */
> > >> > -#define MATCH_TH_FMV_HW_X 0x6000100b
> > >> > +#define MATCH_TH_FMV_HW_X 0x5000100b
> > >> > #define MASK_TH_FMV_HW_X 0xfff0707f
> > >> > -#define MATCH_TH_FMV_X_HW 0x5000100b
> > >> > +#define MATCH_TH_FMV_X_HW 0x6000100b
> > >> > #define MASK_TH_FMV_X_HW 0xfff0707f
> > >> > /* Vendor-specific (T-Head) XTheadInt instructions. */
> > >> > #define MATCH_TH_IPOP 0x0050000b
> > >>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Offline] Re: [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding
2022-12-27 19:45 ` Philipp Tomsich
@ 2022-12-28 1:08 ` Nelson Chu
0 siblings, 0 replies; 7+ messages in thread
From: Nelson Chu @ 2022-12-28 1:08 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Palmer Dabbelt, Christoph Müllner, Binutils,
Andrew Waterman, Lifang Xia
Thanks for your help!
Nelson
On Wed, Dec 28, 2022 at 3:45 AM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> Nelson,
>
> I had missed the OK on this one as I had been traveling for RISC-V Summit and now took care of it.
>
> Applied to master, thanks!
> Philipp.
>
>
> On Thu, 22 Dec 2022 at 02:51, Nelson Chu <nelson@rivosinc.com> wrote:
>>
>> Do we expect this in the 2.40 release? I haven't seen this in master for now.
>>
>> Thanks
>> Nelson
>>
>> On Sat, Dec 17, 2022 at 3:00 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>> >
>> > On Fri, 16 Dec 2022 10:59:53 PST (-0800), christoph.muellner@vrull.eu wrote:
>> > > On Fri, Dec 16, 2022 at 7:56 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>> > >
>> > >> On Fri, 16 Dec 2022 10:51:33 PST (-0800), christoph.muellner@vrull.eu
>> > >> wrote:
>> > >> > From: Christoph Müllner <christoph.muellner@vrull.eu>
>> > >> >
>> > >> > A recent change in the XTheadFmv spec fixed an encoding bug in the
>> > >> > document. This patch changes the code to follow this bugfix.
>> > >> >
>> > >> > Spec patch can be found here:
>> > >> > https://github.com/T-head-Semi/thead-extension-spec/pull/11
>> > >>
>> > >> There's not much info in there. Was this just a bug in the ISA manual?
>> > >> In other words, does the existing hardware (I know of at least C906s and
>> > >> C910s in the wild) behave the new way already? In that case
>> > >>
>> > >
>> > > Yes, this was just a bug in the ISA manual, which slipped through the
>> > > review.
>> > > The manual now matches the implementation.
>> >
>> > OK, thanks!
>> >
>> > >
>> > >
>> > >
>> > >>
>> > >> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>> > >>
>> > >> but if the hardware has the old behavior then we'll need to do something
>> > >> more complicated to avoid breaking compatibility.
>> > >>
>> > >> >
>> > >> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
>> > >> > ---
>> > >> > gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
>> > >> > include/opcode/riscv-opc.h | 4 ++--
>> > >> > 2 files changed, 4 insertions(+), 4 deletions(-)
>> > >> >
>> > >> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > >> b/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > >> > index f2bbe010beb..af8ce0c8ee0 100644
>> > >> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > >> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > >> > @@ -7,5 +7,5 @@
>> > >> > Disassembly of section .text:
>> > >> >
>> > >> > 0+000 <target>:
>> > >> > -[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
>> > >> > -[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
>> > >> > +[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
>> > >> > +[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
>> > >> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> > >> > index 06e3df0f5a6..5420bfac91b 100644
>> > >> > --- a/include/opcode/riscv-opc.h
>> > >> > +++ b/include/opcode/riscv-opc.h
>> > >> > @@ -2209,9 +2209,9 @@
>> > >> > #define MATCH_TH_FSURW 0x5000700b
>> > >> > #define MASK_TH_FSURW 0xf800707f
>> > >> > /* Vendor-specific (T-Head) XTheadFmv instructions. */
>> > >> > -#define MATCH_TH_FMV_HW_X 0x6000100b
>> > >> > +#define MATCH_TH_FMV_HW_X 0x5000100b
>> > >> > #define MASK_TH_FMV_HW_X 0xfff0707f
>> > >> > -#define MATCH_TH_FMV_X_HW 0x5000100b
>> > >> > +#define MATCH_TH_FMV_X_HW 0x6000100b
>> > >> > #define MASK_TH_FMV_X_HW 0xfff0707f
>> > >> > /* Vendor-specific (T-Head) XTheadInt instructions. */
>> > >> > #define MATCH_TH_IPOP 0x0050000b
>> > >>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-12-28 1:08 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2022-12-16 18:51 [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding Christoph Muellner
2022-12-16 18:56 ` Palmer Dabbelt
2022-12-16 18:59 ` Christoph Müllner
2022-12-16 19:00 ` Palmer Dabbelt
2022-12-22 1:50 ` [Offline] " Nelson Chu
2022-12-27 19:45 ` Philipp Tomsich
2022-12-28 1:08 ` Nelson Chu
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