[REVIEW ONLY 0/1] UNRATIFIED RISC-V: Add 'Svadu' extension

[REVIEW ONLY 0/1] UNRATIFIED RISC-V: Add 'Svadu' extension

[Tsukasa OI]

*** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and not frozen RISC-V extension
and not intended to be merged for now.
The only intent to submit this patchset is to test new instructions for
your (possibly virtual) environment and early review for fast adoption
after ratification.


This patchset adds following unratified extension to GNU Binutils:

-   'Svadu' (Hardware Updating of PTE A/D Bits)
    version 0.1 (may change on ratification)

which adds no instructions or no CSRs (but new CSR bits so 'Zicsr'
dependency is added along with extension name support).

This extension provides CSR-based control of hardware PTE updates.


This is based on the specification documentation, version 0.1:
<https://github.com/riscv/riscv-svadu/releases/tag/vv0.1>




Tsukasa OI (1):
  UNRATIFIED RISC-V: Add 'Svadu' extension

 bfd/elfxx-riscv.c | 2 ++
 1 file changed, 2 insertions(+)


base-commit: cb44f89ce977b1ab2d4063f2487950bddfb75bc7
-- 
2.38.1

[REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'Svadu' extension

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

[DO NOT MERGE]
Until 'Svadu' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream.  This commit uses
unratified version 0.1 as in the documentation (instead of possible 1.0
after ratification).

This commit implements support for 'Svadu' extension.  Because it does not
add any instructions or CSRs (but adds bits to existing CSRs), this commit
adds extension name support and implication to the 'Zicsr' extension.

This is based on "Hardware Updating of PTE A/D Bits (Svadu)" version 0.1,
stable <https://github.com/riscv/riscv-svadu/releases/tag/vv0.1>.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implication from
	'Svadu' to 'Zicsr'.  (riscv_supported_std_s_ext) Add 'Svadu'.
---
 bfd/elfxx-riscv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0bcf2fdcfa34..826f248f88c4 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1108,6 +1108,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"sscofpmf", "zicsr",		check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
   {"sstc", "zicsr",		check_implicit_always},
+  {"svadu", "zicsr",		check_implicit_always},
   {NULL, NULL, NULL}
 };
 
@@ -1230,6 +1231,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"svadu",		ISA_SPEC_CLASS_DRAFT,		0, 1, 0 },
   {"svinval",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svnapot",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svpbmt",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
-- 
2.38.1

Re: [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'Svadu' extension

[Palmer Dabbelt]

On Mon, 28 Nov 2022 17:18:15 PST (-0800), binutils@sourceware.org wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> [DO NOT MERGE]
> Until 'Svadu' extension is frozen/ratified and final version number is
> determined, this patch should not be merged upstream.  This commit uses
> unratified version 0.1 as in the documentation (instead of possible 1.0
> after ratification).
>
> This commit implements support for 'Svadu' extension.  Because it does not
> add any instructions or CSRs (but adds bits to existing CSRs), this commit
> adds extension name support and implication to the 'Zicsr' extension.
>
> This is based on "Hardware Updating of PTE A/D Bits (Svadu)" version 0.1,
> stable <https://github.com/riscv/riscv-svadu/releases/tag/vv0.1>.
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c (riscv_implicit_subsets): Add implication from
> 	'Svadu' to 'Zicsr'.  (riscv_supported_std_s_ext) Add 'Svadu'.
> ---
>  bfd/elfxx-riscv.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 0bcf2fdcfa34..826f248f88c4 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1108,6 +1108,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
>    {"sscofpmf", "zicsr",		check_implicit_always},
>    {"ssstateen", "zicsr",	check_implicit_always},
>    {"sstc", "zicsr",		check_implicit_always},
> +  {"svadu", "zicsr",		check_implicit_always},
>    {NULL, NULL, NULL}
>  };
>
> @@ -1230,6 +1231,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
>    {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
>    {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
>    {"sstc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
> +  {"svadu",		ISA_SPEC_CLASS_DRAFT,		0, 1, 0 },
>    {"svinval",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
>    {"svnapot",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
>    {"svpbmt",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> # pending freeze

[REVIEW ONLY 0/1] RISC-V: Add stub support for the 'Svadu' extension

[Tsukasa OI]

Hi,

This is non-review-only patch set for the 'Svadu' extension.
REVIEW ONLY (2022-11-29):
<https://sourceware.org/pipermail/binutils/2022-November/124752.html>

Because this extension is now frozen, unlikely to change and adds no new
instructions or CSRs (but a new bit to an existing CSR), this patch set
only adds extension name / implication support.

This patch set is based on the version 1.0-rc1 (Frozen):
<https://github.com/riscv/riscv-svadu/releases/tag/v1.0-rc1>

Thanks,
Tsukasa




Tsukasa OI (1):
  RISC-V: Add stub support for the 'Svadu' extension

 bfd/elfxx-riscv.c | 2 ++
 1 file changed, 2 insertions(+)


base-commit: a496e1a71e1766d4bb02b241cb23e2e9874d2605
-- 
2.42.0

[REVIEW ONLY 1/1] RISC-V: Add stub support for the 'Svadu' extension

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

This commit implements support for 'Svadu' extension.  Because it does not
add any instructions or CSRs (but adds bits to existing CSRs), this commit
only adds extension name support and implication to the 'Zicsr' extension.

This is based on the "Hardware Updating of PTE A/D Bits (Svadu)"
specification, version 1.0-rc1 (Frozen):
<https://github.com/riscv/riscv-svadu/releases/tag/v1.0-rc1>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implication from
	'Svadu' to 'Zicsr'.  (riscv_supported_std_s_ext) Add 'Svadu'.
---
 bfd/elfxx-riscv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cb65024beaff..9189b7da8374 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1189,6 +1189,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"sscofpmf", "zicsr",		check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
   {"sstc", "zicsr",		check_implicit_always},
+  {"svadu", "zicsr",		check_implicit_always},
   {NULL, NULL, NULL}
 };
 
@@ -1334,6 +1335,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"svadu",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svinval",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svnapot",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svpbmt",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
-- 
2.42.0

Re: [REVIEW ONLY 0/1] RISC-V: Add stub support for the 'Svadu' extension

[Tsukasa OI]

Oops, wrong subject lines (forgot to update format-patch options).

They should not be [REVIEW ONLY] but intended to be [PATCH v1].

Sincerely,
Tsukasa

On 2023/09/03 12:13, Tsukasa OI wrote:
> Hi,
> 
> This is non-review-only patch set for the 'Svadu' extension.
> REVIEW ONLY (2022-11-29):
> <https://sourceware.org/pipermail/binutils/2022-November/124752.html>
> 
> Because this extension is now frozen, unlikely to change and adds no new
> instructions or CSRs (but a new bit to an existing CSR), this patch set
> only adds extension name / implication support.
> 
> This patch set is based on the version 1.0-rc1 (Frozen):
> <https://github.com/riscv/riscv-svadu/releases/tag/v1.0-rc1>
> 
> Thanks,
> Tsukasa
> 
> 
> 
> 
> Tsukasa OI (1):
>   RISC-V: Add stub support for the 'Svadu' extension
> 
>  bfd/elfxx-riscv.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> 
> base-commit: a496e1a71e1766d4bb02b241cb23e2e9874d2605

Re: [REVIEW ONLY 0/1] RISC-V: Add stub support for the 'Svadu' extension

[Nelson Chu]

[-- Attachment #1: Type: text/plain, Size: 1197 bytes --]

Since it was already frozen last week, it's okay to commit for now, thanks.

Nelson

On Sun, Sep 3, 2023 at 11:16 AM Tsukasa OI <research_trasio@irq.a4lg.com>
wrote:

> Oops, wrong subject lines (forgot to update format-patch options).
>
> They should not be [REVIEW ONLY] but intended to be [PATCH v1].
>
> Sincerely,
> Tsukasa
>
> On 2023/09/03 12:13, Tsukasa OI wrote:
> > Hi,
> >
> > This is non-review-only patch set for the 'Svadu' extension.
> > REVIEW ONLY (2022-11-29):
> > <https://sourceware.org/pipermail/binutils/2022-November/124752.html>
> >
> > Because this extension is now frozen, unlikely to change and adds no new
> > instructions or CSRs (but a new bit to an existing CSR), this patch set
> > only adds extension name / implication support.
> >
> > This patch set is based on the version 1.0-rc1 (Frozen):
> > <https://github.com/riscv/riscv-svadu/releases/tag/v1.0-rc1>
> >
> > Thanks,
> > Tsukasa
> >
> >
> >
> >
> > Tsukasa OI (1):
> >   RISC-V: Add stub support for the 'Svadu' extension
> >
> >  bfd/elfxx-riscv.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> >
> > base-commit: a496e1a71e1766d4bb02b241cb23e2e9874d2605
>