* [PATCH] Add new model m32r2 of Renesas M32R.
@ 2003-12-02 11:04 Kazuhiro Inaoka
2003-12-03 17:45 ` Nick Clifton
0 siblings, 1 reply; 4+ messages in thread
From: Kazuhiro Inaoka @ 2003-12-02 11:04 UTC (permalink / raw)
To: cgen; +Cc: gdb-patches, binutils
[-- Attachment #1: Type: text/plain, Size: 1859 bytes --]
Hi,
The attached patches and files add new model m32r2 of Renesas M32R
architecture support.
Please commit.
Kazuhiro Inaoka.
cgen/ChangLog
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* cpu/m32r.cpu : Add new model m32r2.
Add new instructions.
Replace occurrances of 'Mitsubishi' with 'Renesas'.
Changed PIPE attr of push from O to OS.
Care for Little-endian of M32R.
* cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
Care for Little-endian of M32R.
(parse_slo16): signed extension for value.
bfd/ChangeLog
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* archures.c (bfd_mach_m32r2): New machine types.
* cpu-m32r.c : New machine types.
* elf32-m32r.c (m32r_elf_object_p, m32r_elf_final_write_processing,
m32r_elf_merge_private_bfd_data): New machine types.
gas/ChangeLog
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* config/tc-m32r.c : Add new machine m32r2.
Add new instructions.
(line_separator_chars) : Use '!'.
* config/tc-m32r.h : Add new machine m32r2.
gas/tsetsuite/ChangeLog
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* gas/m32r/m32r2.exp : New file for m32r2.
* gas/m32r/m32r2.s : Likewise.
* gas/m32r/m32r2.d : Likewise.
include/ChangeLog
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* elf/m32r.h : Add new machine type m32r2 and instruction modes.
ChangeLog/sim/m32r
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* Makefile.in : Add new machine m32r2.
* m32r2.c : New file for m32r2.
* mloop2.in : Ditto
* model2.c : Ditto
* sem2-switch.c : Ditto
* m32r-sim.h : Add EVB register.
* sim-if.h : Ditto
* sim-main.h : Ditto
* traps.c : Ditto
[-- Attachment #2: sem2-switch.c --]
[-- Type: application/octet-stream, Size: 186925 bytes --]
/* Simulator instruction semantics for m32r2f.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifdef DEFINE_LABELS
/* The labels have the case they have because the enum of insn types
is all uppercase and in the non-stdc case the insn symbol is built
into the enum name. */
static struct {
int index;
void *label;
} labels[] = {
{ M32R2F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
{ M32R2F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
{ M32R2F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
{ M32R2F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
{ M32R2F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
{ M32R2F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
{ M32R2F_INSN_ADD, && case_sem_INSN_ADD },
{ M32R2F_INSN_ADD3, && case_sem_INSN_ADD3 },
{ M32R2F_INSN_AND, && case_sem_INSN_AND },
{ M32R2F_INSN_AND3, && case_sem_INSN_AND3 },
{ M32R2F_INSN_OR, && case_sem_INSN_OR },
{ M32R2F_INSN_OR3, && case_sem_INSN_OR3 },
{ M32R2F_INSN_XOR, && case_sem_INSN_XOR },
{ M32R2F_INSN_XOR3, && case_sem_INSN_XOR3 },
{ M32R2F_INSN_ADDI, && case_sem_INSN_ADDI },
{ M32R2F_INSN_ADDV, && case_sem_INSN_ADDV },
{ M32R2F_INSN_ADDV3, && case_sem_INSN_ADDV3 },
{ M32R2F_INSN_ADDX, && case_sem_INSN_ADDX },
{ M32R2F_INSN_BC8, && case_sem_INSN_BC8 },
{ M32R2F_INSN_BC24, && case_sem_INSN_BC24 },
{ M32R2F_INSN_BEQ, && case_sem_INSN_BEQ },
{ M32R2F_INSN_BEQZ, && case_sem_INSN_BEQZ },
{ M32R2F_INSN_BGEZ, && case_sem_INSN_BGEZ },
{ M32R2F_INSN_BGTZ, && case_sem_INSN_BGTZ },
{ M32R2F_INSN_BLEZ, && case_sem_INSN_BLEZ },
{ M32R2F_INSN_BLTZ, && case_sem_INSN_BLTZ },
{ M32R2F_INSN_BNEZ, && case_sem_INSN_BNEZ },
{ M32R2F_INSN_BL8, && case_sem_INSN_BL8 },
{ M32R2F_INSN_BL24, && case_sem_INSN_BL24 },
{ M32R2F_INSN_BCL8, && case_sem_INSN_BCL8 },
{ M32R2F_INSN_BCL24, && case_sem_INSN_BCL24 },
{ M32R2F_INSN_BNC8, && case_sem_INSN_BNC8 },
{ M32R2F_INSN_BNC24, && case_sem_INSN_BNC24 },
{ M32R2F_INSN_BNE, && case_sem_INSN_BNE },
{ M32R2F_INSN_BRA8, && case_sem_INSN_BRA8 },
{ M32R2F_INSN_BRA24, && case_sem_INSN_BRA24 },
{ M32R2F_INSN_BNCL8, && case_sem_INSN_BNCL8 },
{ M32R2F_INSN_BNCL24, && case_sem_INSN_BNCL24 },
{ M32R2F_INSN_CMP, && case_sem_INSN_CMP },
{ M32R2F_INSN_CMPI, && case_sem_INSN_CMPI },
{ M32R2F_INSN_CMPU, && case_sem_INSN_CMPU },
{ M32R2F_INSN_CMPUI, && case_sem_INSN_CMPUI },
{ M32R2F_INSN_CMPEQ, && case_sem_INSN_CMPEQ },
{ M32R2F_INSN_CMPZ, && case_sem_INSN_CMPZ },
{ M32R2F_INSN_DIV, && case_sem_INSN_DIV },
{ M32R2F_INSN_DIVU, && case_sem_INSN_DIVU },
{ M32R2F_INSN_REM, && case_sem_INSN_REM },
{ M32R2F_INSN_REMU, && case_sem_INSN_REMU },
{ M32R2F_INSN_REMH, && case_sem_INSN_REMH },
{ M32R2F_INSN_REMUH, && case_sem_INSN_REMUH },
{ M32R2F_INSN_REMB, && case_sem_INSN_REMB },
{ M32R2F_INSN_REMUB, && case_sem_INSN_REMUB },
{ M32R2F_INSN_DIVUH, && case_sem_INSN_DIVUH },
{ M32R2F_INSN_DIVB, && case_sem_INSN_DIVB },
{ M32R2F_INSN_DIVUB, && case_sem_INSN_DIVUB },
{ M32R2F_INSN_DIVH, && case_sem_INSN_DIVH },
{ M32R2F_INSN_JC, && case_sem_INSN_JC },
{ M32R2F_INSN_JNC, && case_sem_INSN_JNC },
{ M32R2F_INSN_JL, && case_sem_INSN_JL },
{ M32R2F_INSN_JMP, && case_sem_INSN_JMP },
{ M32R2F_INSN_LD, && case_sem_INSN_LD },
{ M32R2F_INSN_LD_D, && case_sem_INSN_LD_D },
{ M32R2F_INSN_LDB, && case_sem_INSN_LDB },
{ M32R2F_INSN_LDB_D, && case_sem_INSN_LDB_D },
{ M32R2F_INSN_LDH, && case_sem_INSN_LDH },
{ M32R2F_INSN_LDH_D, && case_sem_INSN_LDH_D },
{ M32R2F_INSN_LDUB, && case_sem_INSN_LDUB },
{ M32R2F_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
{ M32R2F_INSN_LDUH, && case_sem_INSN_LDUH },
{ M32R2F_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
{ M32R2F_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
{ M32R2F_INSN_LD24, && case_sem_INSN_LD24 },
{ M32R2F_INSN_LDI8, && case_sem_INSN_LDI8 },
{ M32R2F_INSN_LDI16, && case_sem_INSN_LDI16 },
{ M32R2F_INSN_LOCK, && case_sem_INSN_LOCK },
{ M32R2F_INSN_MACHI_A, && case_sem_INSN_MACHI_A },
{ M32R2F_INSN_MACLO_A, && case_sem_INSN_MACLO_A },
{ M32R2F_INSN_MACWHI_A, && case_sem_INSN_MACWHI_A },
{ M32R2F_INSN_MACWLO_A, && case_sem_INSN_MACWLO_A },
{ M32R2F_INSN_MUL, && case_sem_INSN_MUL },
{ M32R2F_INSN_MULHI_A, && case_sem_INSN_MULHI_A },
{ M32R2F_INSN_MULLO_A, && case_sem_INSN_MULLO_A },
{ M32R2F_INSN_MULWHI_A, && case_sem_INSN_MULWHI_A },
{ M32R2F_INSN_MULWLO_A, && case_sem_INSN_MULWLO_A },
{ M32R2F_INSN_MV, && case_sem_INSN_MV },
{ M32R2F_INSN_MVFACHI_A, && case_sem_INSN_MVFACHI_A },
{ M32R2F_INSN_MVFACLO_A, && case_sem_INSN_MVFACLO_A },
{ M32R2F_INSN_MVFACMI_A, && case_sem_INSN_MVFACMI_A },
{ M32R2F_INSN_MVFC, && case_sem_INSN_MVFC },
{ M32R2F_INSN_MVTACHI_A, && case_sem_INSN_MVTACHI_A },
{ M32R2F_INSN_MVTACLO_A, && case_sem_INSN_MVTACLO_A },
{ M32R2F_INSN_MVTC, && case_sem_INSN_MVTC },
{ M32R2F_INSN_NEG, && case_sem_INSN_NEG },
{ M32R2F_INSN_NOP, && case_sem_INSN_NOP },
{ M32R2F_INSN_NOT, && case_sem_INSN_NOT },
{ M32R2F_INSN_RAC_DSI, && case_sem_INSN_RAC_DSI },
{ M32R2F_INSN_RACH_DSI, && case_sem_INSN_RACH_DSI },
{ M32R2F_INSN_RTE, && case_sem_INSN_RTE },
{ M32R2F_INSN_SETH, && case_sem_INSN_SETH },
{ M32R2F_INSN_SLL, && case_sem_INSN_SLL },
{ M32R2F_INSN_SLL3, && case_sem_INSN_SLL3 },
{ M32R2F_INSN_SLLI, && case_sem_INSN_SLLI },
{ M32R2F_INSN_SRA, && case_sem_INSN_SRA },
{ M32R2F_INSN_SRA3, && case_sem_INSN_SRA3 },
{ M32R2F_INSN_SRAI, && case_sem_INSN_SRAI },
{ M32R2F_INSN_SRL, && case_sem_INSN_SRL },
{ M32R2F_INSN_SRL3, && case_sem_INSN_SRL3 },
{ M32R2F_INSN_SRLI, && case_sem_INSN_SRLI },
{ M32R2F_INSN_ST, && case_sem_INSN_ST },
{ M32R2F_INSN_ST_D, && case_sem_INSN_ST_D },
{ M32R2F_INSN_STB, && case_sem_INSN_STB },
{ M32R2F_INSN_STB_D, && case_sem_INSN_STB_D },
{ M32R2F_INSN_STH, && case_sem_INSN_STH },
{ M32R2F_INSN_STH_D, && case_sem_INSN_STH_D },
{ M32R2F_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
{ M32R2F_INSN_STH_PLUS, && case_sem_INSN_STH_PLUS },
{ M32R2F_INSN_STB_PLUS, && case_sem_INSN_STB_PLUS },
{ M32R2F_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
{ M32R2F_INSN_SUB, && case_sem_INSN_SUB },
{ M32R2F_INSN_SUBV, && case_sem_INSN_SUBV },
{ M32R2F_INSN_SUBX, && case_sem_INSN_SUBX },
{ M32R2F_INSN_TRAP, && case_sem_INSN_TRAP },
{ M32R2F_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
{ M32R2F_INSN_SATB, && case_sem_INSN_SATB },
{ M32R2F_INSN_SATH, && case_sem_INSN_SATH },
{ M32R2F_INSN_SAT, && case_sem_INSN_SAT },
{ M32R2F_INSN_PCMPBZ, && case_sem_INSN_PCMPBZ },
{ M32R2F_INSN_SADD, && case_sem_INSN_SADD },
{ M32R2F_INSN_MACWU1, && case_sem_INSN_MACWU1 },
{ M32R2F_INSN_MSBLO, && case_sem_INSN_MSBLO },
{ M32R2F_INSN_MULWU1, && case_sem_INSN_MULWU1 },
{ M32R2F_INSN_MACLH1, && case_sem_INSN_MACLH1 },
{ M32R2F_INSN_SC, && case_sem_INSN_SC },
{ M32R2F_INSN_SNC, && case_sem_INSN_SNC },
{ M32R2F_INSN_CLRPSW, && case_sem_INSN_CLRPSW },
{ M32R2F_INSN_SETPSW, && case_sem_INSN_SETPSW },
{ M32R2F_INSN_BSET, && case_sem_INSN_BSET },
{ M32R2F_INSN_BCLR, && case_sem_INSN_BCLR },
{ M32R2F_INSN_BTST, && case_sem_INSN_BTST },
{ M32R2F_INSN_PAR_ADD, && case_sem_INSN_PAR_ADD },
{ M32R2F_INSN_WRITE_ADD, && case_sem_INSN_WRITE_ADD },
{ M32R2F_INSN_PAR_AND, && case_sem_INSN_PAR_AND },
{ M32R2F_INSN_WRITE_AND, && case_sem_INSN_WRITE_AND },
{ M32R2F_INSN_PAR_OR, && case_sem_INSN_PAR_OR },
{ M32R2F_INSN_WRITE_OR, && case_sem_INSN_WRITE_OR },
{ M32R2F_INSN_PAR_XOR, && case_sem_INSN_PAR_XOR },
{ M32R2F_INSN_WRITE_XOR, && case_sem_INSN_WRITE_XOR },
{ M32R2F_INSN_PAR_ADDI, && case_sem_INSN_PAR_ADDI },
{ M32R2F_INSN_WRITE_ADDI, && case_sem_INSN_WRITE_ADDI },
{ M32R2F_INSN_PAR_ADDV, && case_sem_INSN_PAR_ADDV },
{ M32R2F_INSN_WRITE_ADDV, && case_sem_INSN_WRITE_ADDV },
{ M32R2F_INSN_PAR_ADDX, && case_sem_INSN_PAR_ADDX },
{ M32R2F_INSN_WRITE_ADDX, && case_sem_INSN_WRITE_ADDX },
{ M32R2F_INSN_PAR_BC8, && case_sem_INSN_PAR_BC8 },
{ M32R2F_INSN_WRITE_BC8, && case_sem_INSN_WRITE_BC8 },
{ M32R2F_INSN_PAR_BL8, && case_sem_INSN_PAR_BL8 },
{ M32R2F_INSN_WRITE_BL8, && case_sem_INSN_WRITE_BL8 },
{ M32R2F_INSN_PAR_BCL8, && case_sem_INSN_PAR_BCL8 },
{ M32R2F_INSN_WRITE_BCL8, && case_sem_INSN_WRITE_BCL8 },
{ M32R2F_INSN_PAR_BNC8, && case_sem_INSN_PAR_BNC8 },
{ M32R2F_INSN_WRITE_BNC8, && case_sem_INSN_WRITE_BNC8 },
{ M32R2F_INSN_PAR_BRA8, && case_sem_INSN_PAR_BRA8 },
{ M32R2F_INSN_WRITE_BRA8, && case_sem_INSN_WRITE_BRA8 },
{ M32R2F_INSN_PAR_BNCL8, && case_sem_INSN_PAR_BNCL8 },
{ M32R2F_INSN_WRITE_BNCL8, && case_sem_INSN_WRITE_BNCL8 },
{ M32R2F_INSN_PAR_CMP, && case_sem_INSN_PAR_CMP },
{ M32R2F_INSN_WRITE_CMP, && case_sem_INSN_WRITE_CMP },
{ M32R2F_INSN_PAR_CMPU, && case_sem_INSN_PAR_CMPU },
{ M32R2F_INSN_WRITE_CMPU, && case_sem_INSN_WRITE_CMPU },
{ M32R2F_INSN_PAR_CMPEQ, && case_sem_INSN_PAR_CMPEQ },
{ M32R2F_INSN_WRITE_CMPEQ, && case_sem_INSN_WRITE_CMPEQ },
{ M32R2F_INSN_PAR_CMPZ, && case_sem_INSN_PAR_CMPZ },
{ M32R2F_INSN_WRITE_CMPZ, && case_sem_INSN_WRITE_CMPZ },
{ M32R2F_INSN_PAR_JC, && case_sem_INSN_PAR_JC },
{ M32R2F_INSN_WRITE_JC, && case_sem_INSN_WRITE_JC },
{ M32R2F_INSN_PAR_JNC, && case_sem_INSN_PAR_JNC },
{ M32R2F_INSN_WRITE_JNC, && case_sem_INSN_WRITE_JNC },
{ M32R2F_INSN_PAR_JL, && case_sem_INSN_PAR_JL },
{ M32R2F_INSN_WRITE_JL, && case_sem_INSN_WRITE_JL },
{ M32R2F_INSN_PAR_JMP, && case_sem_INSN_PAR_JMP },
{ M32R2F_INSN_WRITE_JMP, && case_sem_INSN_WRITE_JMP },
{ M32R2F_INSN_PAR_LD, && case_sem_INSN_PAR_LD },
{ M32R2F_INSN_WRITE_LD, && case_sem_INSN_WRITE_LD },
{ M32R2F_INSN_PAR_LDB, && case_sem_INSN_PAR_LDB },
{ M32R2F_INSN_WRITE_LDB, && case_sem_INSN_WRITE_LDB },
{ M32R2F_INSN_PAR_LDH, && case_sem_INSN_PAR_LDH },
{ M32R2F_INSN_WRITE_LDH, && case_sem_INSN_WRITE_LDH },
{ M32R2F_INSN_PAR_LDUB, && case_sem_INSN_PAR_LDUB },
{ M32R2F_INSN_WRITE_LDUB, && case_sem_INSN_WRITE_LDUB },
{ M32R2F_INSN_PAR_LDUH, && case_sem_INSN_PAR_LDUH },
{ M32R2F_INSN_WRITE_LDUH, && case_sem_INSN_WRITE_LDUH },
{ M32R2F_INSN_PAR_LD_PLUS, && case_sem_INSN_PAR_LD_PLUS },
{ M32R2F_INSN_WRITE_LD_PLUS, && case_sem_INSN_WRITE_LD_PLUS },
{ M32R2F_INSN_PAR_LDI8, && case_sem_INSN_PAR_LDI8 },
{ M32R2F_INSN_WRITE_LDI8, && case_sem_INSN_WRITE_LDI8 },
{ M32R2F_INSN_PAR_LOCK, && case_sem_INSN_PAR_LOCK },
{ M32R2F_INSN_WRITE_LOCK, && case_sem_INSN_WRITE_LOCK },
{ M32R2F_INSN_PAR_MACHI_A, && case_sem_INSN_PAR_MACHI_A },
{ M32R2F_INSN_WRITE_MACHI_A, && case_sem_INSN_WRITE_MACHI_A },
{ M32R2F_INSN_PAR_MACLO_A, && case_sem_INSN_PAR_MACLO_A },
{ M32R2F_INSN_WRITE_MACLO_A, && case_sem_INSN_WRITE_MACLO_A },
{ M32R2F_INSN_PAR_MACWHI_A, && case_sem_INSN_PAR_MACWHI_A },
{ M32R2F_INSN_WRITE_MACWHI_A, && case_sem_INSN_WRITE_MACWHI_A },
{ M32R2F_INSN_PAR_MACWLO_A, && case_sem_INSN_PAR_MACWLO_A },
{ M32R2F_INSN_WRITE_MACWLO_A, && case_sem_INSN_WRITE_MACWLO_A },
{ M32R2F_INSN_PAR_MUL, && case_sem_INSN_PAR_MUL },
{ M32R2F_INSN_WRITE_MUL, && case_sem_INSN_WRITE_MUL },
{ M32R2F_INSN_PAR_MULHI_A, && case_sem_INSN_PAR_MULHI_A },
{ M32R2F_INSN_WRITE_MULHI_A, && case_sem_INSN_WRITE_MULHI_A },
{ M32R2F_INSN_PAR_MULLO_A, && case_sem_INSN_PAR_MULLO_A },
{ M32R2F_INSN_WRITE_MULLO_A, && case_sem_INSN_WRITE_MULLO_A },
{ M32R2F_INSN_PAR_MULWHI_A, && case_sem_INSN_PAR_MULWHI_A },
{ M32R2F_INSN_WRITE_MULWHI_A, && case_sem_INSN_WRITE_MULWHI_A },
{ M32R2F_INSN_PAR_MULWLO_A, && case_sem_INSN_PAR_MULWLO_A },
{ M32R2F_INSN_WRITE_MULWLO_A, && case_sem_INSN_WRITE_MULWLO_A },
{ M32R2F_INSN_PAR_MV, && case_sem_INSN_PAR_MV },
{ M32R2F_INSN_WRITE_MV, && case_sem_INSN_WRITE_MV },
{ M32R2F_INSN_PAR_MVFACHI_A, && case_sem_INSN_PAR_MVFACHI_A },
{ M32R2F_INSN_WRITE_MVFACHI_A, && case_sem_INSN_WRITE_MVFACHI_A },
{ M32R2F_INSN_PAR_MVFACLO_A, && case_sem_INSN_PAR_MVFACLO_A },
{ M32R2F_INSN_WRITE_MVFACLO_A, && case_sem_INSN_WRITE_MVFACLO_A },
{ M32R2F_INSN_PAR_MVFACMI_A, && case_sem_INSN_PAR_MVFACMI_A },
{ M32R2F_INSN_WRITE_MVFACMI_A, && case_sem_INSN_WRITE_MVFACMI_A },
{ M32R2F_INSN_PAR_MVFC, && case_sem_INSN_PAR_MVFC },
{ M32R2F_INSN_WRITE_MVFC, && case_sem_INSN_WRITE_MVFC },
{ M32R2F_INSN_PAR_MVTACHI_A, && case_sem_INSN_PAR_MVTACHI_A },
{ M32R2F_INSN_WRITE_MVTACHI_A, && case_sem_INSN_WRITE_MVTACHI_A },
{ M32R2F_INSN_PAR_MVTACLO_A, && case_sem_INSN_PAR_MVTACLO_A },
{ M32R2F_INSN_WRITE_MVTACLO_A, && case_sem_INSN_WRITE_MVTACLO_A },
{ M32R2F_INSN_PAR_MVTC, && case_sem_INSN_PAR_MVTC },
{ M32R2F_INSN_WRITE_MVTC, && case_sem_INSN_WRITE_MVTC },
{ M32R2F_INSN_PAR_NEG, && case_sem_INSN_PAR_NEG },
{ M32R2F_INSN_WRITE_NEG, && case_sem_INSN_WRITE_NEG },
{ M32R2F_INSN_PAR_NOP, && case_sem_INSN_PAR_NOP },
{ M32R2F_INSN_WRITE_NOP, && case_sem_INSN_WRITE_NOP },
{ M32R2F_INSN_PAR_NOT, && case_sem_INSN_PAR_NOT },
{ M32R2F_INSN_WRITE_NOT, && case_sem_INSN_WRITE_NOT },
{ M32R2F_INSN_PAR_RAC_DSI, && case_sem_INSN_PAR_RAC_DSI },
{ M32R2F_INSN_WRITE_RAC_DSI, && case_sem_INSN_WRITE_RAC_DSI },
{ M32R2F_INSN_PAR_RACH_DSI, && case_sem_INSN_PAR_RACH_DSI },
{ M32R2F_INSN_WRITE_RACH_DSI, && case_sem_INSN_WRITE_RACH_DSI },
{ M32R2F_INSN_PAR_RTE, && case_sem_INSN_PAR_RTE },
{ M32R2F_INSN_WRITE_RTE, && case_sem_INSN_WRITE_RTE },
{ M32R2F_INSN_PAR_SLL, && case_sem_INSN_PAR_SLL },
{ M32R2F_INSN_WRITE_SLL, && case_sem_INSN_WRITE_SLL },
{ M32R2F_INSN_PAR_SLLI, && case_sem_INSN_PAR_SLLI },
{ M32R2F_INSN_WRITE_SLLI, && case_sem_INSN_WRITE_SLLI },
{ M32R2F_INSN_PAR_SRA, && case_sem_INSN_PAR_SRA },
{ M32R2F_INSN_WRITE_SRA, && case_sem_INSN_WRITE_SRA },
{ M32R2F_INSN_PAR_SRAI, && case_sem_INSN_PAR_SRAI },
{ M32R2F_INSN_WRITE_SRAI, && case_sem_INSN_WRITE_SRAI },
{ M32R2F_INSN_PAR_SRL, && case_sem_INSN_PAR_SRL },
{ M32R2F_INSN_WRITE_SRL, && case_sem_INSN_WRITE_SRL },
{ M32R2F_INSN_PAR_SRLI, && case_sem_INSN_PAR_SRLI },
{ M32R2F_INSN_WRITE_SRLI, && case_sem_INSN_WRITE_SRLI },
{ M32R2F_INSN_PAR_ST, && case_sem_INSN_PAR_ST },
{ M32R2F_INSN_WRITE_ST, && case_sem_INSN_WRITE_ST },
{ M32R2F_INSN_PAR_STB, && case_sem_INSN_PAR_STB },
{ M32R2F_INSN_WRITE_STB, && case_sem_INSN_WRITE_STB },
{ M32R2F_INSN_PAR_STH, && case_sem_INSN_PAR_STH },
{ M32R2F_INSN_WRITE_STH, && case_sem_INSN_WRITE_STH },
{ M32R2F_INSN_PAR_ST_PLUS, && case_sem_INSN_PAR_ST_PLUS },
{ M32R2F_INSN_WRITE_ST_PLUS, && case_sem_INSN_WRITE_ST_PLUS },
{ M32R2F_INSN_PAR_STH_PLUS, && case_sem_INSN_PAR_STH_PLUS },
{ M32R2F_INSN_WRITE_STH_PLUS, && case_sem_INSN_WRITE_STH_PLUS },
{ M32R2F_INSN_PAR_STB_PLUS, && case_sem_INSN_PAR_STB_PLUS },
{ M32R2F_INSN_WRITE_STB_PLUS, && case_sem_INSN_WRITE_STB_PLUS },
{ M32R2F_INSN_PAR_ST_MINUS, && case_sem_INSN_PAR_ST_MINUS },
{ M32R2F_INSN_WRITE_ST_MINUS, && case_sem_INSN_WRITE_ST_MINUS },
{ M32R2F_INSN_PAR_SUB, && case_sem_INSN_PAR_SUB },
{ M32R2F_INSN_WRITE_SUB, && case_sem_INSN_WRITE_SUB },
{ M32R2F_INSN_PAR_SUBV, && case_sem_INSN_PAR_SUBV },
{ M32R2F_INSN_WRITE_SUBV, && case_sem_INSN_WRITE_SUBV },
{ M32R2F_INSN_PAR_SUBX, && case_sem_INSN_PAR_SUBX },
{ M32R2F_INSN_WRITE_SUBX, && case_sem_INSN_WRITE_SUBX },
{ M32R2F_INSN_PAR_TRAP, && case_sem_INSN_PAR_TRAP },
{ M32R2F_INSN_WRITE_TRAP, && case_sem_INSN_WRITE_TRAP },
{ M32R2F_INSN_PAR_UNLOCK, && case_sem_INSN_PAR_UNLOCK },
{ M32R2F_INSN_WRITE_UNLOCK, && case_sem_INSN_WRITE_UNLOCK },
{ M32R2F_INSN_PAR_PCMPBZ, && case_sem_INSN_PAR_PCMPBZ },
{ M32R2F_INSN_WRITE_PCMPBZ, && case_sem_INSN_WRITE_PCMPBZ },
{ M32R2F_INSN_PAR_SADD, && case_sem_INSN_PAR_SADD },
{ M32R2F_INSN_WRITE_SADD, && case_sem_INSN_WRITE_SADD },
{ M32R2F_INSN_PAR_MACWU1, && case_sem_INSN_PAR_MACWU1 },
{ M32R2F_INSN_WRITE_MACWU1, && case_sem_INSN_WRITE_MACWU1 },
{ M32R2F_INSN_PAR_MSBLO, && case_sem_INSN_PAR_MSBLO },
{ M32R2F_INSN_WRITE_MSBLO, && case_sem_INSN_WRITE_MSBLO },
{ M32R2F_INSN_PAR_MULWU1, && case_sem_INSN_PAR_MULWU1 },
{ M32R2F_INSN_WRITE_MULWU1, && case_sem_INSN_WRITE_MULWU1 },
{ M32R2F_INSN_PAR_MACLH1, && case_sem_INSN_PAR_MACLH1 },
{ M32R2F_INSN_WRITE_MACLH1, && case_sem_INSN_WRITE_MACLH1 },
{ M32R2F_INSN_PAR_SC, && case_sem_INSN_PAR_SC },
{ M32R2F_INSN_WRITE_SC, && case_sem_INSN_WRITE_SC },
{ M32R2F_INSN_PAR_SNC, && case_sem_INSN_PAR_SNC },
{ M32R2F_INSN_WRITE_SNC, && case_sem_INSN_WRITE_SNC },
{ M32R2F_INSN_PAR_CLRPSW, && case_sem_INSN_PAR_CLRPSW },
{ M32R2F_INSN_WRITE_CLRPSW, && case_sem_INSN_WRITE_CLRPSW },
{ M32R2F_INSN_PAR_SETPSW, && case_sem_INSN_PAR_SETPSW },
{ M32R2F_INSN_WRITE_SETPSW, && case_sem_INSN_WRITE_SETPSW },
{ M32R2F_INSN_PAR_BTST, && case_sem_INSN_PAR_BTST },
{ M32R2F_INSN_WRITE_BTST, && case_sem_INSN_WRITE_BTST },
{ 0, 0 }
};
int i;
for (i = 0; labels[i].label != 0; ++i)
{
#if FAST_P
CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
#else
CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
#endif
}
#undef DEFINE_LABELS
#endif /* DEFINE_LABELS */
#ifdef DEFINE_SWITCH
/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
off frills like tracing and profiling. */
/* FIXME: A better way would be to have TRACE_RESULT check for something
that can cause it to be optimized out. Another way would be to emit
special handlers into the instruction "stream". */
#if FAST_P
#undef TRACE_RESULT
#define TRACE_RESULT(cpu, abuf, name, type, val)
#endif
#undef GET_ATTR
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
#else
#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
#endif
{
#if WITH_SCACHE_PBB
/* Branch to next handler without going around main loop. */
#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
#else /* ! WITH_SCACHE_PBB */
#define NEXT(vpc) BREAK (sem)
#ifdef __GNUC__
#if FAST_P
SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
#else
SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
#endif
#else
SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
#endif
#endif /* ! WITH_SCACHE_PBB */
{
CASE (sem, INSN_X_INVALID) : /* --invalid-- */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
/* Update the recorded pc in the cpu state struct.
Only necessary for WITH_SCACHE case, but to avoid the
conditional compilation .... */
SET_H_PC (pc);
/* Virtual insns have zero size. Overwrite vpc with address of next insn
using the default-insn-bitsize spec. When executing insns in parallel
we may want to queue the fault and continue execution. */
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_X_AFTER) : /* --after-- */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_M32R2F
m32r2f_pbb_after (current_cpu, sem_arg);
#endif
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_X_BEFORE) : /* --before-- */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_M32R2F
m32r2f_pbb_before (current_cpu, sem_arg);
#endif
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_M32R2F
#ifdef DEFINE_SWITCH
vpc = m32r2f_pbb_cti_chain (current_cpu, sem_arg,
pbb_br_type, pbb_br_npc);
BREAK (sem);
#else
/* FIXME: Allow provision of explicit ifmt spec in insn spec. */
vpc = m32r2f_pbb_cti_chain (current_cpu, sem_arg,
CPU_PBB_BR_TYPE (current_cpu),
CPU_PBB_BR_NPC (current_cpu));
#endif
#endif
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_X_CHAIN) : /* --chain-- */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_M32R2F
vpc = m32r2f_pbb_chain (current_cpu, sem_arg);
#ifdef DEFINE_SWITCH
BREAK (sem);
#endif
#endif
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_X_BEGIN) : /* --begin-- */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_M32R2F
#if defined DEFINE_SWITCH || defined FAST_P
/* In the switch case FAST_P is a constant, allowing several optimizations
in any called inline functions. */
vpc = m32r2f_pbb_begin (current_cpu, FAST_P);
#else
#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
vpc = m32r2f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
#else
vpc = m32r2f_pbb_begin (current_cpu, 0);
#endif
#endif
#endif
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_ADD) : /* add $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_AND) : /* and $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_and3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_OR) : /* or $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_and3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_XOR) : /* xor $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_and3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_addi.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;BI temp1;
temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
{
SI opval = temp0;
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
BI opval = temp1;
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI temp0;BI temp1;
temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
{
SI opval = temp0;
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
BI opval = temp1;
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;BI temp1;
temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
{
SI opval = temp0;
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
BI opval = temp1;
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BC8) : /* bc.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (CPU (h_cond)) {
{
USI opval = FLD (i_disp8);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BC24) : /* bc.l $disp24 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl24.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (CPU (h_cond)) {
{
USI opval = FLD (i_disp24);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_beq.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
{
USI opval = FLD (i_disp16);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_beq.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (EQSI (* FLD (i_src2), 0)) {
{
USI opval = FLD (i_disp16);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_beq.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (GESI (* FLD (i_src2), 0)) {
{
USI opval = FLD (i_disp16);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_beq.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (GTSI (* FLD (i_src2), 0)) {
{
USI opval = FLD (i_disp16);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_beq.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (LESI (* FLD (i_src2), 0)) {
{
USI opval = FLD (i_disp16);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_beq.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (LTSI (* FLD (i_src2), 0)) {
{
USI opval = FLD (i_disp16);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_beq.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_src2), 0)) {
{
USI opval = FLD (i_disp16);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BL8) : /* bl.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
{
SI opval = ADDSI (ANDSI (pc, -4), 4);
CPU (h_gr[((UINT) 14)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = FLD (i_disp8);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BL24) : /* bl.l $disp24 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl24.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
SI opval = ADDSI (pc, 4);
CPU (h_gr[((UINT) 14)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = FLD (i_disp24);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BCL8) : /* bcl.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (CPU (h_cond)) {
{
{
SI opval = ADDSI (ANDSI (pc, -4), 4);
CPU (h_gr[((UINT) 14)]) = opval;
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = FLD (i_disp8);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BCL24) : /* bcl.l $disp24 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl24.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (CPU (h_cond)) {
{
{
SI opval = ADDSI (pc, 4);
CPU (h_gr[((UINT) 14)]) = opval;
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = FLD (i_disp24);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (NOTBI (CPU (h_cond))) {
{
USI opval = FLD (i_disp8);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl24.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NOTBI (CPU (h_cond))) {
{
USI opval = FLD (i_disp24);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_beq.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_src1), * FLD (i_src2))) {
{
USI opval = FLD (i_disp16);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
USI opval = FLD (i_disp8);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl24.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
USI opval = FLD (i_disp24);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BNCL8) : /* bncl.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (NOTBI (CPU (h_cond))) {
{
{
SI opval = ADDSI (ANDSI (pc, -4), 4);
CPU (h_gr[((UINT) 14)]) = opval;
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = FLD (i_disp8);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BNCL24) : /* bncl.l $disp24 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl24.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NOTBI (CPU (h_cond))) {
{
{
SI opval = ADDSI (pc, 4);
CPU (h_gr[((UINT) 14)]) = opval;
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = FLD (i_disp24);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_d.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_d.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_CMPEQ) : /* cmpeq $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_CMPZ) : /* cmpz $src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = EQSI (* FLD (i_src2), 0);
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_DIV) : /* div $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_REM) : /* rem $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_REMU) : /* remu $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_REMH) : /* remh $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = MODSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_REMUH) : /* remuh $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_REMB) : /* remb $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = MODSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_REMUB) : /* remub $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_DIVUH) : /* divuh $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_DIVB) : /* divb $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = DIVSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_DIVUB) : /* divub $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_DIVH) : /* divh $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (* FLD (i_sr), 0)) {
{
SI opval = DIVSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));
* FLD (i_dr) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_JC) : /* jc $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_jl.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (CPU (h_cond)) {
{
USI opval = ANDSI (* FLD (i_sr), -4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_JNC) : /* jnc $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_jl.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (NOTBI (CPU (h_cond))) {
{
USI opval = ANDSI (* FLD (i_sr), -4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_JL) : /* jl $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_jl.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;USI temp1;
temp0 = ADDSI (ANDSI (pc, -4), 4);
temp1 = ANDSI (* FLD (i_sr), -4);
{
SI opval = temp0;
CPU (h_gr[((UINT) 14)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = temp1;
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_JMP) : /* jmp $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_jl.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
USI opval = ANDSI (* FLD (i_sr), -4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LD) : /* ld $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;SI temp1;
temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
temp1 = ADDSI (* FLD (i_sr), 4);
{
SI opval = temp0;
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
SI opval = temp1;
* FLD (i_sr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld24.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = FLD (i_uimm24);
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_addi.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = FLD (f_simm8);
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = FLD (f_simm16);
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
{
BI opval = 1;
CPU (h_lock) = opval;
TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MACHI_A) : /* machi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
SET_H_ACCUMS (FLD (f_acc), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MACLO_A) : /* maclo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
SET_H_ACCUMS (FLD (f_acc), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MACWHI_A) : /* macwhi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
SET_H_ACCUMS (FLD (f_acc), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MACWLO_A) : /* macwlo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
SET_H_ACCUMS (FLD (f_acc), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MUL) : /* mul $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MULHI_A) : /* mulhi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
SET_H_ACCUMS (FLD (f_acc), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MULLO_A) : /* mullo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
SET_H_ACCUMS (FLD (f_acc), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
SET_H_ACCUMS (FLD (f_acc), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
SET_H_ACCUMS (FLD (f_acc), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MV) : /* mv $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = * FLD (i_sr);
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MVFACHI_A) : /* mvfachi $dr,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MVFACLO_A) : /* mvfaclo $dr,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MVFACMI_A) : /* mvfacmi $dr,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = GET_H_CR (FLD (f_r2));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MVTACHI_A) : /* mvtachi $src1,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
SET_H_ACCUMS (FLD (f_accs), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MVTACLO_A) : /* mvtaclo $src1,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
SET_H_ACCUMS (FLD (f_accs), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
USI opval = * FLD (i_sr);
SET_H_CR (FLD (f_r1), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_NEG) : /* neg $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = NEGSI (* FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_NOP) : /* nop */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_NOT) : /* not $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = INVSI (* FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_RAC_DSI) : /* rac $accd,$accs,$imm1 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_rac_dsi.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI tmp_tmp1;
tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
{
DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
SET_H_ACCUMS (FLD (f_accd), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_RACH_DSI) : /* rach $accd,$accs,$imm1 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_rac_dsi.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI tmp_tmp1;
tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
{
DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
SET_H_ACCUMS (FLD (f_accd), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_RTE) : /* rte */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
{
USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
{
USI opval = GET_H_CR (((UINT) 14));
SET_H_CR (((UINT) 6), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
{
UQI opval = CPU (h_bpsw);
SET_H_PSW (opval);
TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
}
{
UQI opval = CPU (h_bbpsw);
CPU (h_bpsw) = opval;
TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
}
}
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_seth.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = SLLSI (FLD (f_hi16), 16);
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SLL) : /* sll $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_slli.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SRA) : /* sra $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_slli.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SRL) : /* srl $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_slli.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_ST) : /* st $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_d.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
QI opval = * FLD (i_src1);
SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_d.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI opval = * FLD (i_src1);
SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
HI opval = * FLD (i_src1);
SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_d.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
HI opval = * FLD (i_src1);
SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI tmp_new_src2;
tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
{
SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
{
SI opval = tmp_new_src2;
* FLD (i_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_STH_PLUS) : /* sth $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
HI tmp_new_src2;
{
HI opval = * FLD (i_src1);
SETMEMHI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
{
SI opval = tmp_new_src2;
* FLD (i_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_STB_PLUS) : /* stb $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
QI tmp_new_src2;
{
QI opval = * FLD (i_src1);
SETMEMQI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
{
SI opval = tmp_new_src2;
* FLD (i_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI tmp_new_src2;
tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
{
SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
{
SI opval = tmp_new_src2;
* FLD (i_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SUB) : /* sub $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;BI temp1;
temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
{
SI opval = temp0;
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
BI opval = temp1;
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;BI temp1;
temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
{
SI opval = temp0;
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
BI opval = temp1;
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_TRAP) : /* trap $uimm4 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_trap.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
{
USI opval = GET_H_CR (((UINT) 6));
SET_H_CR (((UINT) 14), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
{
USI opval = ADDSI (pc, 4);
SET_H_CR (((UINT) 6), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
{
UQI opval = CPU (h_bpsw);
CPU (h_bbpsw) = opval;
TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
}
{
UQI opval = GET_H_PSW ();
CPU (h_bpsw) = opval;
TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
}
{
UQI opval = ANDQI (GET_H_PSW (), 128);
SET_H_PSW (opval);
TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
}
{
SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
SEM_BRANCH_FINI (vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
if (CPU (h_lock)) {
{
SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
{
BI opval = 0;
CPU (h_lock) = opval;
TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
}
}
abuf->written = written;
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SATB) : /* satb $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = (GESI (* FLD (i_sr), 127)) ? (127) : (LESI (* FLD (i_sr), -128)) ? (-128) : (* FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SATH) : /* sath $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = (GESI (* FLD (i_sr), 32767)) ? (32767) : (LESI (* FLD (i_sr), -32768)) ? (-32768) : (* FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SAT) : /* sat $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = ((CPU (h_cond)) ? (((LTSI (* FLD (i_sr), 0)) ? (2147483647) : (0x80000000))) : (* FLD (i_sr)));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PCMPBZ) : /* pcmpbz $src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SADD) : /* sadd */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
SET_H_ACCUMS (((UINT) 0), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MACWU1) : /* macwu1 $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
SET_H_ACCUMS (((UINT) 1), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MSBLO) : /* msblo $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
SET_H_ACCUM (opval);
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MULWU1) : /* mulwu1 $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
SET_H_ACCUMS (((UINT) 1), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_MACLH1) : /* maclh1 $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
SET_H_ACCUMS (((UINT) 1), opval);
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SC) : /* sc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (ZEXTBISI (CPU (h_cond)))
SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SNC) : /* snc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (ZEXTBISI (NOTBI (CPU (h_cond))))
SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_clrpsw.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
SET_H_CR (((UINT) 0), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_clrpsw.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = FLD (f_uimm8);
SET_H_CR (((UINT) 0), opval);
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bset.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bset.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bset.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_ADD) : /* add $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_ADD) : /* add $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_AND) : /* and $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_AND) : /* and $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_OR) : /* or $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_OR) : /* or $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_XOR) : /* xor $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_XOR) : /* xor $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_ADDI) : /* addi $dr,$simm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_addi.f
#define OPRND(f) par_exec->operands.sfmt_addi.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_ADDI) : /* addi $dr,$simm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_addi.f
#define OPRND(f) par_exec->operands.sfmt_addi.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_ADDV) : /* addv $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_addv.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;BI temp1;
temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
{
SI opval = temp0;
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
BI opval = temp1;
OPRND (condbit) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_ADDV) : /* addv $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_addv.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_cond) = OPRND (condbit);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_ADDX) : /* addx $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_addx.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;BI temp1;
temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
{
SI opval = temp0;
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
BI opval = temp1;
OPRND (condbit) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_ADDX) : /* addx $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_addx.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_cond) = OPRND (condbit);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_BC8) : /* bc.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bc8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (CPU (h_cond)) {
{
USI opval = FLD (i_disp8);
OPRND (pc) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_BC8) : /* bc.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bc8.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
if (written & (1 << 2))
{
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
}
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_BL8) : /* bl.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bl8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
{
SI opval = ADDSI (ANDSI (pc, -4), 4);
OPRND (h_gr_SI_14) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = FLD (i_disp8);
OPRND (pc) = opval;
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_BL8) : /* bl.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bl8.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_BCL8) : /* bcl.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bcl8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (CPU (h_cond)) {
{
{
SI opval = ADDSI (ANDSI (pc, -4), 4);
OPRND (h_gr_SI_14) = opval;
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = FLD (i_disp8);
OPRND (pc) = opval;
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
abuf->written = written;
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_BCL8) : /* bcl.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bcl8.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
if (written & (1 << 3))
{
CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
}
if (written & (1 << 4))
{
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
}
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_BNC8) : /* bnc.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bc8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (NOTBI (CPU (h_cond))) {
{
USI opval = FLD (i_disp8);
OPRND (pc) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_BNC8) : /* bnc.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bc8.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
if (written & (1 << 2))
{
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
}
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_BRA8) : /* bra.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bra8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
USI opval = FLD (i_disp8);
OPRND (pc) = opval;
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_BRA8) : /* bra.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bra8.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_BNCL8) : /* bncl.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bcl8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (NOTBI (CPU (h_cond))) {
{
{
SI opval = ADDSI (ANDSI (pc, -4), 4);
OPRND (h_gr_SI_14) = opval;
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = FLD (i_disp8);
OPRND (pc) = opval;
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
abuf->written = written;
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_BNCL8) : /* bncl.s $disp8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_bl8.f
#define OPRND(f) par_exec->operands.sfmt_bcl8.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
if (written & (1 << 3))
{
CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
}
if (written & (1 << 4))
{
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
}
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_CMP) : /* cmp $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_cmp.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
OPRND (condbit) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_CMP) : /* cmp $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_cmp.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_cond) = OPRND (condbit);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_CMPU) : /* cmpu $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_cmp.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
OPRND (condbit) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_CMPU) : /* cmpu $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_cmp.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_cond) = OPRND (condbit);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_CMPEQ) : /* cmpeq $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_cmp.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
OPRND (condbit) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_CMPEQ) : /* cmpeq $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_cmp.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_cond) = OPRND (condbit);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_CMPZ) : /* cmpz $src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_cmpz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = EQSI (* FLD (i_src2), 0);
OPRND (condbit) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_CMPZ) : /* cmpz $src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_cmpz.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_cond) = OPRND (condbit);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_JC) : /* jc $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_jl.f
#define OPRND(f) par_exec->operands.sfmt_jc.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (CPU (h_cond)) {
{
USI opval = ANDSI (* FLD (i_sr), -4);
OPRND (pc) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_JC) : /* jc $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_jl.f
#define OPRND(f) par_exec->operands.sfmt_jc.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
if (written & (1 << 2))
{
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
}
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_JNC) : /* jnc $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_jl.f
#define OPRND(f) par_exec->operands.sfmt_jc.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (NOTBI (CPU (h_cond))) {
{
USI opval = ANDSI (* FLD (i_sr), -4);
OPRND (pc) = opval;
written |= (1 << 2);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_JNC) : /* jnc $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_jl.f
#define OPRND(f) par_exec->operands.sfmt_jc.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
if (written & (1 << 2))
{
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
}
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_JL) : /* jl $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_jl.f
#define OPRND(f) par_exec->operands.sfmt_jl.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;USI temp1;
temp0 = ADDSI (ANDSI (pc, -4), 4);
temp1 = ANDSI (* FLD (i_sr), -4);
{
SI opval = temp0;
OPRND (h_gr_SI_14) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = temp1;
OPRND (pc) = opval;
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_JL) : /* jl $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_jl.f
#define OPRND(f) par_exec->operands.sfmt_jl.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_JMP) : /* jmp $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_jl.f
#define OPRND(f) par_exec->operands.sfmt_jmp.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
USI opval = ANDSI (* FLD (i_sr), -4);
OPRND (pc) = opval;
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_JMP) : /* jmp $sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_jl.f
#define OPRND(f) par_exec->operands.sfmt_jmp.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_LD) : /* ld $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ld.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_LD) : /* ld $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ld.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_LDB) : /* ldb $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ldb.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ldb.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_LDH) : /* ldh $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ldh.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ldh.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_LDUB) : /* ldub $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ldb.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ldb.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_LDUH) : /* lduh $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ldh.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_LDUH) : /* lduh $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ldh.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_LD_PLUS) : /* ld $dr,@$sr+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ld_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;SI temp1;
temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
temp1 = ADDSI (* FLD (i_sr), 4);
{
SI opval = temp0;
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
SI opval = temp1;
OPRND (sr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_LD_PLUS) : /* ld $dr,@$sr+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_ld_plus.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
* FLD (i_sr) = OPRND (sr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_LDI8) : /* ldi8 $dr,$simm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_addi.f
#define OPRND(f) par_exec->operands.sfmt_ldi8.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = FLD (f_simm8);
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_LDI8) : /* ldi8 $dr,$simm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_addi.f
#define OPRND(f) par_exec->operands.sfmt_ldi8.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_LOCK) : /* lock $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_lock.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
{
BI opval = 1;
OPRND (h_lock_BI) = opval;
TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_LOCK) : /* lock $dr,@$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_lock.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
CPU (h_lock) = OPRND (h_lock_BI);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MACHI_A) : /* machi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
OPRND (acc) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MACHI_A) : /* machi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_machi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MACLO_A) : /* maclo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
OPRND (acc) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MACLO_A) : /* maclo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_machi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MACWHI_A) : /* macwhi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
OPRND (acc) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MACWHI_A) : /* macwhi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_machi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MACWLO_A) : /* macwlo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_machi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
OPRND (acc) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MACWLO_A) : /* macwlo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_machi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MUL) : /* mul $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MUL) : /* mul $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MULHI_A) : /* mulhi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
OPRND (acc) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MULHI_A) : /* mulhi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MULLO_A) : /* mullo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
OPRND (acc) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MULLO_A) : /* mullo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
OPRND (acc) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
OPRND (acc) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_machi_a.f
#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MV) : /* mv $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_mv.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = * FLD (i_sr);
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MV) : /* mv $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_mv.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MVFACHI_A) : /* mvfachi $dr,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MVFACHI_A) : /* mvfachi $dr,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MVFACLO_A) : /* mvfaclo $dr,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MVFACLO_A) : /* mvfaclo $dr,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MVFACMI_A) : /* mvfacmi $dr,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MVFACMI_A) : /* mvfacmi $dr,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MVFC) : /* mvfc $dr,$scr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_mvfc.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = GET_H_CR (FLD (f_r2));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MVFC) : /* mvfc $dr,$scr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_mvfc.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MVTACHI_A) : /* mvtachi $src1,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
OPRND (accs) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MVTACHI_A) : /* mvtachi $src1,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MVTACLO_A) : /* mvtaclo $src1,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
OPRND (accs) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MVTACLO_A) : /* mvtaclo $src1,$accs */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MVTC) : /* mvtc $sr,$dcr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_mvtc.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
USI opval = * FLD (i_sr);
OPRND (dcr) = opval;
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MVTC) : /* mvtc $sr,$dcr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_mvtc.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_CR (FLD (f_r1), OPRND (dcr));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_NEG) : /* neg $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_mv.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = NEGSI (* FLD (i_sr));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_NEG) : /* neg $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_mv.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_NOP) : /* nop */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define OPRND(f) par_exec->operands.sfmt_nop.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_NOP) : /* nop */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.fmt_empty.f
#define OPRND(f) par_exec->operands.sfmt_nop.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_NOT) : /* not $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_mv.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = INVSI (* FLD (i_sr));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_NOT) : /* not $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_ld_plus.f
#define OPRND(f) par_exec->operands.sfmt_mv.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_RAC_DSI) : /* rac $accd,$accs,$imm1 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_rac_dsi.f
#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI tmp_tmp1;
tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
{
DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
OPRND (accd) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_RAC_DSI) : /* rac $accd,$accs,$imm1 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_rac_dsi.f
#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_RACH_DSI) : /* rach $accd,$accs,$imm1 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_rac_dsi.f
#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI tmp_tmp1;
tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
{
DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
OPRND (accd) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_RACH_DSI) : /* rach $accd,$accs,$imm1 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_rac_dsi.f
#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_RTE) : /* rte */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define OPRND(f) par_exec->operands.sfmt_rte.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
{
USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
OPRND (pc) = opval;
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
{
USI opval = GET_H_CR (((UINT) 14));
OPRND (h_cr_USI_6) = opval;
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
{
UQI opval = CPU (h_bpsw);
OPRND (h_psw_UQI) = opval;
TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
}
{
UQI opval = CPU (h_bbpsw);
OPRND (h_bpsw_UQI) = opval;
TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_RTE) : /* rte */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.fmt_empty.f
#define OPRND(f) par_exec->operands.sfmt_rte.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_bpsw) = OPRND (h_bpsw_UQI);
SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));
SET_H_PSW (OPRND (h_psw_UQI));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SLL) : /* sll $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SLL) : /* sll $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SLLI) : /* slli $dr,$uimm5 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_slli.f
#define OPRND(f) par_exec->operands.sfmt_slli.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SLLI) : /* slli $dr,$uimm5 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_slli.f
#define OPRND(f) par_exec->operands.sfmt_slli.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SRA) : /* sra $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SRA) : /* sra $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SRAI) : /* srai $dr,$uimm5 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_slli.f
#define OPRND(f) par_exec->operands.sfmt_slli.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SRAI) : /* srai $dr,$uimm5 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_slli.f
#define OPRND(f) par_exec->operands.sfmt_slli.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SRL) : /* srl $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SRL) : /* srl $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SRLI) : /* srli $dr,$uimm5 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_slli.f
#define OPRND(f) par_exec->operands.sfmt_slli.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SRLI) : /* srli $dr,$uimm5 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_slli.f
#define OPRND(f) par_exec->operands.sfmt_slli.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_ST) : /* st $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_st.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = * FLD (i_src1);
OPRND (h_memory_SI_src2_idx) = * FLD (i_src2);
OPRND (h_memory_SI_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_st.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_STB) : /* stb $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_stb.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
QI opval = * FLD (i_src1);
OPRND (h_memory_QI_src2_idx) = * FLD (i_src2);
OPRND (h_memory_QI_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_stb.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_src2_idx), OPRND (h_memory_QI_src2));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_STH) : /* sth $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_sth.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
HI opval = * FLD (i_src1);
OPRND (h_memory_HI_src2_idx) = * FLD (i_src2);
OPRND (h_memory_HI_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_sth.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_src2_idx), OPRND (h_memory_HI_src2));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_ST_PLUS) : /* st $src1,@+$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI tmp_new_src2;
tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
{
SI opval = * FLD (i_src1);
OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2;
OPRND (h_memory_SI_new_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
{
SI opval = tmp_new_src2;
OPRND (src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_st_plus.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2));
* FLD (i_src2) = OPRND (src2);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_STH_PLUS) : /* sth $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_sth_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
HI tmp_new_src2;
{
HI opval = * FLD (i_src1);
OPRND (h_memory_HI_new_src2_idx) = tmp_new_src2;
OPRND (h_memory_HI_new_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
{
SI opval = tmp_new_src2;
OPRND (src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_STH_PLUS) : /* sth $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_sth_plus.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_new_src2_idx), OPRND (h_memory_HI_new_src2));
* FLD (i_src2) = OPRND (src2);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_STB_PLUS) : /* stb $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_stb_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
QI tmp_new_src2;
{
QI opval = * FLD (i_src1);
OPRND (h_memory_QI_new_src2_idx) = tmp_new_src2;
OPRND (h_memory_QI_new_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
{
SI opval = tmp_new_src2;
OPRND (src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_STB_PLUS) : /* stb $src1,@$src2+ */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_stb_plus.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_new_src2_idx), OPRND (h_memory_QI_new_src2));
* FLD (i_src2) = OPRND (src2);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_ST_MINUS) : /* st $src1,@-$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_st_plus.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI tmp_new_src2;
tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
{
SI opval = * FLD (i_src1);
OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2;
OPRND (h_memory_SI_new_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
{
SI opval = tmp_new_src2;
OPRND (src2) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_ST_MINUS) : /* st $src1,@-$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_st_plus.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2));
* FLD (i_src2) = OPRND (src2);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SUB) : /* sub $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SUB) : /* sub $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_add.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SUBV) : /* subv $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_addv.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;BI temp1;
temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
{
SI opval = temp0;
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
BI opval = temp1;
OPRND (condbit) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SUBV) : /* subv $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_addv.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_cond) = OPRND (condbit);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SUBX) : /* subx $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_addx.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI temp0;BI temp1;
temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
{
SI opval = temp0;
OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
BI opval = temp1;
OPRND (condbit) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SUBX) : /* subx $dr,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_add.f
#define OPRND(f) par_exec->operands.sfmt_addx.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_cond) = OPRND (condbit);
* FLD (i_dr) = OPRND (dr);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_TRAP) : /* trap $uimm4 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_trap.f
#define OPRND(f) par_exec->operands.sfmt_trap.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
{
USI opval = GET_H_CR (((UINT) 6));
OPRND (h_cr_USI_14) = opval;
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
{
USI opval = ADDSI (pc, 4);
OPRND (h_cr_USI_6) = opval;
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
{
UQI opval = CPU (h_bpsw);
OPRND (h_bbpsw_UQI) = opval;
TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
}
{
UQI opval = GET_H_PSW ();
OPRND (h_bpsw_UQI) = opval;
TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
}
{
UQI opval = ANDQI (GET_H_PSW (), 128);
OPRND (h_psw_UQI) = opval;
TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
}
{
SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
OPRND (pc) = opval;
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_trap.f
#define OPRND(f) par_exec->operands.sfmt_trap.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_bbpsw) = OPRND (h_bbpsw_UQI);
CPU (h_bpsw) = OPRND (h_bpsw_UQI);
SET_H_CR (((UINT) 14), OPRND (h_cr_USI_14));
SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));
SET_H_PSW (OPRND (h_psw_UQI));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
SEM_BRANCH_FINI (vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_UNLOCK) : /* unlock $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_unlock.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
if (CPU (h_lock)) {
{
SI opval = * FLD (i_src1);
OPRND (h_memory_SI_src2_idx) = * FLD (i_src2);
OPRND (h_memory_SI_src2) = opval;
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
}
{
BI opval = 0;
OPRND (h_lock_BI) = opval;
TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
}
}
abuf->written = written;
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_UNLOCK) : /* unlock $src1,@$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_unlock.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_lock) = OPRND (h_lock_BI);
if (written & (1 << 4))
{
SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2));
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_PCMPBZ) : /* pcmpbz $src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_cmpz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
OPRND (condbit) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_PCMPBZ) : /* pcmpbz $src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_cmpz.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_cond) = OPRND (condbit);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SADD) : /* sadd */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define OPRND(f) par_exec->operands.sfmt_sadd.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
OPRND (h_accums_DI_0) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SADD) : /* sadd */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.fmt_empty.f
#define OPRND(f) par_exec->operands.sfmt_sadd.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_DI_0));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MACWU1) : /* macwu1 $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_macwu1.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
OPRND (h_accums_DI_1) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MACWU1) : /* macwu1 $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_macwu1.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MSBLO) : /* msblo $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_msblo.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
OPRND (accum) = opval;
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MSBLO) : /* msblo $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_msblo.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUM (OPRND (accum));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MULWU1) : /* mulwu1 $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_mulwu1.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
OPRND (h_accums_DI_1) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_mulwu1.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_MACLH1) : /* maclh1 $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_macwu1.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
OPRND (h_accums_DI_1) = opval;
TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_MACLH1) : /* maclh1 $src1,$src2 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_st_plus.f
#define OPRND(f) par_exec->operands.sfmt_macwu1.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SC) : /* sc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define OPRND(f) par_exec->operands.sfmt_sc.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (ZEXTBISI (CPU (h_cond)))
SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SC) : /* sc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.fmt_empty.f
#define OPRND(f) par_exec->operands.sfmt_sc.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SNC) : /* snc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.fmt_empty.f
#define OPRND(f) par_exec->operands.sfmt_sc.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
if (ZEXTBISI (NOTBI (CPU (h_cond))))
SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SNC) : /* snc */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.fmt_empty.f
#define OPRND(f) par_exec->operands.sfmt_sc.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_CLRPSW) : /* clrpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_clrpsw.f
#define OPRND(f) par_exec->operands.sfmt_clrpsw.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
OPRND (h_cr_USI_0) = opval;
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_CLRPSW) : /* clrpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
#define OPRND(f) par_exec->operands.sfmt_clrpsw.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_SETPSW) : /* setpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_clrpsw.f
#define OPRND(f) par_exec->operands.sfmt_setpsw.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
SI opval = FLD (f_uimm8);
OPRND (h_cr_USI_0) = opval;
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_SETPSW) : /* setpsw $uimm8 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_clrpsw.f
#define OPRND(f) par_exec->operands.sfmt_setpsw.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_PAR_BTST) : /* btst $uimm3,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_bset.f
#define OPRND(f) par_exec->operands.sfmt_btst.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{
BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
OPRND (condbit) = opval;
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
}
#undef OPRND
#undef FLD
}
NEXT (vpc);
CASE (sem, INSN_WRITE_BTST) : /* btst $uimm3,$sr */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
#define FLD(f) abuf->fields.sfmt_bset.f
#define OPRND(f) par_exec->operands.sfmt_btst.f
int UNUSED written = abuf->written;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
CPU (h_cond) = OPRND (condbit);
#undef OPRND
#undef FLD
}
NEXT (vpc);
}
ENDSWITCH (sem) /* End of semantic switch. */
/* At this point `vpc' contains the next insn to execute. */
}
#undef DEFINE_SWITCH
#endif /* DEFINE_SWITCH */
[-- Attachment #3: m32r2.d --]
[-- Type: application/octet-stream, Size: 2584 bytes --]
#as: -m32r2
#objdump: -dr
#name: m32r2
.*: +file format .*
Disassembly of section .text:
0+0000 <setpsw>:
0: 71 c1 71 ff setpsw #0xc1 -> setpsw #0xff
0+0004 <clrpsw>:
4: 72 c1 72 ff clrpsw #0xc1 -> clrpsw #0xff
0+0008 <bset>:
8: a0 61 00 04 bset #0x0,@\(4,r1\)
c: a1 61 00 04 bset #0x1,@\(4,r1\)
10: a7 61 00 04 bset #0x7,@\(4,r1\)
0+0014 <bclr>:
14: a0 71 00 04 bclr #0x0,@\(4,r1\)
18: a1 71 00 04 bclr #0x1,@\(4,r1\)
1c: a7 71 00 04 bclr #0x7,@\(4,r1\)
0+0020 <btst>:
20: 00 fd 01 fd btst #0x0,fp -> btst #0x1,fp
24: 07 fd f0 00 btst #0x7,fp \|\| nop
28: 01 fd 90 82 btst #0x1,fp \|\| mv r0,r2
2c: 01 fd 90 82 btst #0x1,fp \|\| mv r0,r2
0+0030 <divuh>:
30: 9d 1d 00 10 divuh fp,fp
0+0034 <divb>:
34: 9d 0d 00 18 divb fp,fp
0+0038 <divub>:
38: 9d 1d 00 18 divub fp,fp
0+003c <remh>:
3c: 9d 2d 00 10 remh fp,fp
0+0040 <remuh>:
40: 9d 3d 00 10 remuh fp,fp
0+0044 <remb>:
44: 9d 2d 00 18 remb fp,fp
0+0048 <remub>:
48: 9d 3d 00 18 remub fp,fp
0+004c <sll>:
4c: 10 41 92 43 sll r0,r1 \|\| sll r2,r3
50: 12 43 90 61 sll r2,r3 \|\| mul r0,r1
54: 10 41 92 63 sll r0,r1 \|\| mul r2,r3
58: 60 01 92 43 ldi r0,#1 \|\| sll r2,r3
5c: 10 41 e2 01 sll r0,r1 \|\| ldi r2,#1
0+0060 <slli>:
60: 50 41 d2 5f slli r0,#0x1 \|\| slli r2,#0x1f
64: 52 5f 90 61 slli r2,#0x1f \|\| mul r0,r1
68: 50 41 92 63 slli r0,#0x1 \|\| mul r2,r3
6c: 60 01 d2 5f ldi r0,#1 \|\| slli r2,#0x1f
70: 50 41 e2 01 slli r0,#0x1 \|\| ldi r2,#1
0+0074 <sra>:
74: 10 21 92 23 sra r0,r1 \|\| sra r2,r3
78: 12 23 90 61 sra r2,r3 \|\| mul r0,r1
7c: 10 21 92 63 sra r0,r1 \|\| mul r2,r3
80: 60 01 92 23 ldi r0,#1 \|\| sra r2,r3
84: 10 21 e2 01 sra r0,r1 \|\| ldi r2,#1
0+0088 <srai>:
88: 50 21 d2 3f srai r0,#0x1 \|\| srai r2,#0x1f
8c: 52 3f 90 61 srai r2,#0x1f \|\| mul r0,r1
90: 50 21 92 63 srai r0,#0x1 \|\| mul r2,r3
94: 60 01 d2 3f ldi r0,#1 \|\| srai r2,#0x1f
98: 50 21 e2 01 srai r0,#0x1 \|\| ldi r2,#1
0+009c <srl>:
9c: 10 01 92 03 srl r0,r1 \|\| srl r2,r3
a0: 12 03 90 61 srl r2,r3 \|\| mul r0,r1
a4: 10 01 92 63 srl r0,r1 \|\| mul r2,r3
a8: 60 01 92 03 ldi r0,#1 \|\| srl r2,r3
ac: 10 01 e2 01 srl r0,r1 \|\| ldi r2,#1
0+00b0 <srli>:
b0: 50 01 d2 1f srli r0,#0x1 \|\| srli r2,#0x1f
b4: 52 1f 90 61 srli r2,#0x1f \|\| mul r0,r1
b8: 50 01 92 63 srli r0,#0x1 \|\| mul r2,r3
bc: 60 01 d2 1f ldi r0,#1 \|\| srli r2,#0x1f
c0: 50 01 e2 01 srli r0,#0x1 \|\| ldi r2,#1
[-- Attachment #4: m32r2.exp --]
[-- Type: application/octet-stream, Size: 89 bytes --]
# M32R2 assembler testsuite.
if [istarget m32r*-*-*] {
run_dump_test "m32r2"
}
[-- Attachment #5: mloop2.in --]
[-- Type: application/octet-stream, Size: 13255 bytes --]
# Simulator main loop for m32r2. -*- C -*-
# Copyright (C) 1996, 1997, 1998, 2003 Free Software Foundation, Inc.
#
# This file is part of the GNU Simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
# Syntax:
# /bin/sh mainloop.in command
#
# Command is one of:
#
# init
# support
# extract-{simple,scache,pbb}
# {full,fast}-exec-{simple,scache,pbb}
#
# A target need only provide a "full" version of one of simple,scache,pbb.
# If the target wants it can also provide a fast version of same, or if
# the slow (full featured) version is `simple', then the fast version can be
# one of scache/pbb.
# A target can't provide more than this.
# ??? After a few more ports are done, revisit.
# Will eventually need to machine generate a lot of this.
case "x$1" in
xsupport)
cat <<EOF
/* Emit insns to write back the results of insns executed in parallel.
SC points to a sufficient number of scache entries for the writeback
handlers.
SC1/ID1 is the first insn (left slot, lower address).
SC2/ID2 is the second insn (right slot, higher address). */
static INLINE void
emit_par_finish (SIM_CPU *current_cpu, PCADDR pc, SCACHE *sc,
SCACHE *sc1, const IDESC *id1, SCACHE *sc2, const IDESC *id2)
{
ARGBUF *abuf;
abuf = &sc->argbuf;
id1 = id1->par_idesc;
abuf->fields.write.abuf = &sc1->argbuf;
@cpu@_fill_argbuf (current_cpu, abuf, id1, pc, 0);
/* no need to set trace_p,profile_p */
#if 0 /* not currently needed for id2 since results written directly */
abuf = &sc[1].argbuf;
id2 = id2->par_idesc;
abuf->fields.write.abuf = &sc2->argbuf;
@cpu@_fill_argbuf (current_cpu, abuf, id2, pc + 2, 0);
/* no need to set trace_p,profile_p */
#endif
}
static INLINE const IDESC *
emit_16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
SCACHE *sc, int fast_p, int parallel_p)
{
ARGBUF *abuf = &sc->argbuf;
const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
if (parallel_p)
id = id->par_idesc;
@cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
return id;
}
static INLINE const IDESC *
emit_full16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
int trace_p, int profile_p)
{
const IDESC *id;
@cpu@_emit_before (current_cpu, sc, pc, 1);
id = emit_16 (current_cpu, pc, insn, sc + 1, 0, 0);
@cpu@_emit_after (current_cpu, sc + 2, pc);
sc[1].argbuf.trace_p = trace_p;
sc[1].argbuf.profile_p = profile_p;
return id;
}
static INLINE const IDESC *
emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
SCACHE *sc, int fast_p)
{
const IDESC *id,*id2;
/* Emit both insns, then emit a finisher-upper.
We speed things up by handling the second insn serially
[not parallelly]. Then the writeback only has to deal
with the first insn. */
/* ??? Revisit to handle exceptions right. */
/* FIXME: No need to handle this parallely if second is nop. */
id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1);
/* Note that this can never be a cti. No cti's go in the S pipeline. */
id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, fast_p, 0);
/* Set sc/snc insns notion of where to skip to. */
if (IDESC_SKIP_P (id))
SEM_SKIP_COMPILE (current_cpu, sc, 1);
/* Emit code to finish executing the semantics
(write back the results). */
emit_par_finish (current_cpu, pc, sc + 2, sc, id, sc + 1, id2);
return id;
}
static INLINE const IDESC *
emit_full_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
SCACHE *sc, int trace_p, int profile_p)
{
const IDESC *id,*id2;
/* Emit both insns, then emit a finisher-upper.
We speed things up by handling the second insn serially
[not parallelly]. Then the writeback only has to deal
with the first insn. */
/* ??? Revisit to handle exceptions right. */
@cpu@_emit_before (current_cpu, sc, pc, 1);
/* FIXME: No need to handle this parallelly if second is nop. */
id = emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 1);
sc[1].argbuf.trace_p = trace_p;
sc[1].argbuf.profile_p = profile_p;
@cpu@_emit_before (current_cpu, sc + 2, pc, 0);
/* Note that this can never be a cti. No cti's go in the S pipeline. */
id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 3, 0, 0);
sc[3].argbuf.trace_p = trace_p;
sc[3].argbuf.profile_p = profile_p;
/* Set sc/snc insns notion of where to skip to. */
if (IDESC_SKIP_P (id))
SEM_SKIP_COMPILE (current_cpu, sc, 4);
/* Emit code to finish executing the semantics
(write back the results). */
emit_par_finish (current_cpu, pc, sc + 4, sc + 1, id, sc + 3, id2);
@cpu@_emit_after (current_cpu, sc + 5, pc);
return id;
}
static INLINE const IDESC *
emit_32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
SCACHE *sc, int fast_p)
{
ARGBUF *abuf = &sc->argbuf;
const IDESC *id = @cpu@_decode (current_cpu, pc,
(USI) insn >> 16, insn, abuf);
@cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
return id;
}
static INLINE const IDESC *
emit_full32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
int trace_p, int profile_p)
{
const IDESC *id;
@cpu@_emit_before (current_cpu, sc, pc, 1);
id = emit_32 (current_cpu, pc, insn, sc + 1, 0);
@cpu@_emit_after (current_cpu, sc + 2, pc);
sc[1].argbuf.trace_p = trace_p;
sc[1].argbuf.profile_p = profile_p;
return id;
}
EOF
;;
xinit)
# Nothing needed.
;;
xextract-pbb)
# Inputs: current_cpu, pc, sc, max_insns, FAST_P
# Outputs: sc, pc
# sc must be left pointing past the last created entry.
# pc must be left pointing past the last created entry.
# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
# to record the vpc of the cti insn.
# SET_INSN_COUNT(n) must be called to record number of real insns.
cat <<EOF
{
const IDESC *idesc;
int icount = 0;
if ((pc & 3) != 0)
{
/* This occurs when single stepping and when compiling the not-taken
part of conditional branches. */
UHI insn = GETIMEMUHI (current_cpu, pc);
int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
SCACHE *cti_sc; /* ??? tmp hack */
/* A parallel insn isn't allowed here, but we don't mind nops.
??? We need to wait until the insn is executed before signalling
the error, for situations where such signalling is wanted. */
#if 0
if ((insn & 0x8000) != 0
&& (insn & 0x7fff) != 0x7000) /* parallel nops are ok */
sim_engine_invalid_insn (current_cpu, pc, 0);
#endif
/* Only emit before/after handlers if necessary. */
if (FAST_P || (! trace_p && ! profile_p))
{
idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P, 0);
cti_sc = sc;
++sc;
--max_insns;
}
else
{
idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
trace_p, profile_p);
cti_sc = sc + 1;
sc += 3;
max_insns -= 3;
}
++icount;
pc += 2;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (cti_sc);
goto Finish;
}
}
/* There are two copies of the compiler: full(!fast) and fast.
The "full" case emits before/after handlers for each insn.
Having two copies of this code is a tradeoff, having one copy
seemed a bit more difficult to read (due to constantly testing
FAST_P). ??? On the other hand, with address ranges we'll want to
omit before/after handlers for unwanted insns. Having separate loops
for FAST/!FAST avoids constantly doing the test in the loop, but
typically FAST_P is a constant and such tests will get optimized out. */
if (FAST_P)
{
while (max_insns > 0)
{
USI insn = GETIMEMUSI (current_cpu, pc);
if ((SI) insn < 0)
{
/* 32 bit insn */
idesc = emit_32 (current_cpu, pc, insn, sc, 1);
++sc;
--max_insns;
++icount;
pc += 4;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (sc - 1);
break;
}
}
else
{
if ((insn & 0x8000) != 0) /* parallel? */
{
/* Yep. Here's the "interesting" [sic] part. */
idesc = emit_parallel (current_cpu, pc, insn, sc, 1);
sc += 3;
max_insns -= 3;
icount += 2;
pc += 4;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (sc - 3);
break;
}
}
else /* 2 serial 16 bit insns */
{
idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 1, 0);
++sc;
--max_insns;
++icount;
pc += 2;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (sc - 1);
break;
}
/* While we're guaranteed that there's room to extract the
insn, when single stepping we can't; the pbb must stop
after the first insn. */
if (max_insns == 0)
break;
idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 1, 0);
++sc;
--max_insns;
++icount;
pc += 2;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (sc - 1);
break;
}
}
}
}
}
else /* ! FAST_P */
{
while (max_insns > 0)
{
USI insn = GETIMEMUSI (current_cpu, pc);
int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
SCACHE *cti_sc; /* ??? tmp hack */
if ((SI) insn < 0)
{
/* 32 bit insn
Only emit before/after handlers if necessary. */
if (trace_p || profile_p)
{
idesc = emit_full32 (current_cpu, pc, insn, sc,
trace_p, profile_p);
cti_sc = sc + 1;
sc += 3;
max_insns -= 3;
}
else
{
idesc = emit_32 (current_cpu, pc, insn, sc, 0);
cti_sc = sc;
++sc;
--max_insns;
}
++icount;
pc += 4;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (cti_sc);
break;
}
}
else
{
if ((insn & 0x8000) != 0) /* parallel? */
{
/* Yep. Here's the "interesting" [sic] part.
Only emit before/after handlers if necessary. */
if (trace_p || profile_p)
{
idesc = emit_full_parallel (current_cpu, pc, insn, sc,
trace_p, profile_p);
cti_sc = sc + 1;
sc += 6;
max_insns -= 6;
}
else
{
idesc = emit_parallel (current_cpu, pc, insn, sc, 0);
cti_sc = sc;
sc += 3;
max_insns -= 3;
}
icount += 2;
pc += 4;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (cti_sc);
break;
}
}
else /* 2 serial 16 bit insns */
{
/* Only emit before/after handlers if necessary. */
if (trace_p || profile_p)
{
idesc = emit_full16 (current_cpu, pc, insn >> 16, sc,
trace_p, profile_p);
cti_sc = sc + 1;
sc += 3;
max_insns -= 3;
}
else
{
idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 0, 0);
cti_sc = sc;
++sc;
--max_insns;
}
++icount;
pc += 2;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (cti_sc);
break;
}
/* While we're guaranteed that there's room to extract the
insn, when single stepping we can't; the pbb must stop
after the first insn. */
if (max_insns <= 0)
break;
/* Use the same trace/profile address for the 2nd insn.
Saves us having to compute it and they come in pairs
anyway (e.g. can never branch to the 2nd insn). */
if (trace_p || profile_p)
{
idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
trace_p, profile_p);
cti_sc = sc + 1;
sc += 3;
max_insns -= 3;
}
else
{
idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 0, 0);
cti_sc = sc;
++sc;
--max_insns;
}
++icount;
pc += 2;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (cti_sc);
break;
}
}
}
}
}
Finish:
SET_INSN_COUNT (icount);
}
EOF
;;
xfull-exec-pbb)
# Inputs: current_cpu, vpc, FAST_P
# Outputs: vpc
# vpc is the virtual program counter.
cat <<EOF
#define DEFINE_SWITCH
#include "sem2-switch.c"
EOF
;;
*)
echo "Invalid argument to mainloop.in: $1" >&2
exit 1
;;
esac
[-- Attachment #6: m32r2.c --]
[-- Type: application/octet-stream, Size: 8293 bytes --]
/* m32r2 simulator support code
Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define WANT_CPU m32r2f
#define WANT_CPU_M32R2F
#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
/* The contents of BUF are in target byte order. */
int
m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
return m32rbf_fetch_register (current_cpu, rn, buf, len);
}
/* The contents of BUF are in target byte order. */
int
m32r2f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
return m32rbf_store_register (current_cpu, rn, buf, len);
}
\f
/* Cover fns to get/set the control registers.
FIXME: Duplicated from m32r.c. The issue is structure offsets. */
USI
m32r2f_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
{
switch (cr)
{
case H_CR_PSW : /* psw */
return (((CPU (h_bpsw) & 0xc1) << 8)
| ((CPU (h_psw) & 0xc0) << 0)
| GET_H_COND ());
case H_CR_BBPSW : /* backup backup psw */
return CPU (h_bbpsw) & 0xc1;
case H_CR_CBR : /* condition bit */
return GET_H_COND ();
case H_CR_SPI : /* interrupt stack pointer */
if (! GET_H_SM ())
return CPU (h_gr[H_GR_SP]);
else
return CPU (h_cr[H_CR_SPI]);
case H_CR_SPU : /* user stack pointer */
if (GET_H_SM ())
return CPU (h_gr[H_GR_SP]);
else
return CPU (h_cr[H_CR_SPU]);
case H_CR_BPC : /* backup pc */
return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
case H_CR_BBPC : /* backup backup pc */
return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
case 4 : /* ??? unspecified, but apparently available */
case 5 : /* ??? unspecified, but apparently available */
return CPU (h_cr[cr]);
default :
return 0;
}
}
void
m32r2f_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
{
switch (cr)
{
case H_CR_PSW : /* psw */
{
int old_sm = (CPU (h_psw) & 0x80) != 0;
int new_sm = (newval & 0x80) != 0;
CPU (h_bpsw) = (newval >> 8) & 0xff;
CPU (h_psw) = newval & 0xff;
SET_H_COND (newval & 1);
/* When switching stack modes, update the registers. */
if (old_sm != new_sm)
{
if (old_sm)
{
/* Switching user -> system. */
CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
}
else
{
/* Switching system -> user. */
CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
}
}
break;
}
case H_CR_BBPSW : /* backup backup psw */
CPU (h_bbpsw) = newval & 0xff;
break;
case H_CR_CBR : /* condition bit */
SET_H_COND (newval & 1);
break;
case H_CR_SPI : /* interrupt stack pointer */
if (! GET_H_SM ())
CPU (h_gr[H_GR_SP]) = newval;
else
CPU (h_cr[H_CR_SPI]) = newval;
break;
case H_CR_SPU : /* user stack pointer */
if (GET_H_SM ())
CPU (h_gr[H_GR_SP]) = newval;
else
CPU (h_cr[H_CR_SPU]) = newval;
break;
case H_CR_BPC : /* backup pc */
CPU (h_cr[H_CR_BPC]) = newval;
break;
case H_CR_BBPC : /* backup backup pc */
CPU (h_cr[H_CR_BBPC]) = newval;
break;
case 4 : /* ??? unspecified, but apparently available */
case 5 : /* ??? unspecified, but apparently available */
CPU (h_cr[cr]) = newval;
break;
default :
/* ignore */
break;
}
}
/* Cover fns to access h-psw. */
UQI
m32r2f_h_psw_get_handler (SIM_CPU *current_cpu)
{
return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
}
void
m32r2f_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
{
CPU (h_psw) = newval;
CPU (h_cond) = newval & 1;
}
/* Cover fns to access h-accum. */
DI
m32r2f_h_accum_get_handler (SIM_CPU *current_cpu)
{
/* Sign extend the top 8 bits. */
DI r;
r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
r = XORDI (r, MAKEDI (0x800000, 0));
r = SUBDI (r, MAKEDI (0x800000, 0));
return r;
}
void
m32r2f_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
{
CPU (h_accum) = newval;
}
/* Cover fns to access h-accums. */
DI
m32r2f_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
{
/* FIXME: Yes, this is just a quick hack. */
DI r;
if (regno == 0)
r = CPU (h_accum);
else
r = CPU (h_accums[1]);
/* Sign extend the top 8 bits. */
r = ANDDI (r, MAKEDI (0xffffff, 0xffffffff));
r = XORDI (r, MAKEDI (0x800000, 0));
r = SUBDI (r, MAKEDI (0x800000, 0));
return r;
}
void
m32r2f_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval)
{
/* FIXME: Yes, this is just a quick hack. */
if (regno == 0)
CPU (h_accum) = newval;
else
CPU (h_accums[1]) = newval;
}
\f
#if WITH_PROFILE_MODEL_P
/* Initialize cycle counting for an insn.
FIRST_P is non-zero if this is the first insn in a set of parallel
insns. */
void
m32r2f_model_insn_before (SIM_CPU *cpu, int first_p)
{
m32rbf_model_insn_before (cpu, first_p);
}
/* Record the cycles computed for an insn.
LAST_P is non-zero if this is the last insn in a set of parallel insns,
and we update the total cycle count.
CYCLES is the cycle count of the insn. */
void
m32r2f_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
{
m32rbf_model_insn_after (cpu, last_p, cycles);
}
static INLINE void
check_load_stall (SIM_CPU *cpu, int regno)
{
UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
if (regno != -1
&& (h_gr & (1 << regno)) != 0)
{
CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
if (TRACE_INSN_P (cpu))
cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
}
}
int
m32r2f_model_m32r2_u_exec (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT sr, INT sr2, INT dr)
{
check_load_stall (cpu, sr);
check_load_stall (cpu, sr2);
return idesc->timing->units[unit_num].done;
}
int
m32r2f_model_m32r2_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT src1, INT src2)
{
check_load_stall (cpu, src1);
check_load_stall (cpu, src2);
return idesc->timing->units[unit_num].done;
}
int
m32r2f_model_m32r2_u_mac (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT src1, INT src2)
{
check_load_stall (cpu, src1);
check_load_stall (cpu, src2);
return idesc->timing->units[unit_num].done;
}
int
m32r2f_model_m32r2_u_cti (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT sr)
{
PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
int taken_p = (referenced & (1 << 1)) != 0;
check_load_stall (cpu, sr);
if (taken_p)
{
CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
}
else
PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
return idesc->timing->units[unit_num].done;
}
int
m32r2f_model_m32r2_u_load (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT sr, INT dr)
{
CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
return idesc->timing->units[unit_num].done;
}
int
m32r2f_model_m32r2_u_store (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT src1, INT src2)
{
return idesc->timing->units[unit_num].done;
}
#endif /* WITH_PROFILE_MODEL_P */
[-- Attachment #7: bfd.m32r2.patch --]
[-- Type: application/octet-stream, Size: 3867 bytes --]
bfd/ChangeLog
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* archures.c (bfd_mach_m32r2): New machine types.
* cpu-m32r.c : New machine types.
* elf32-m32r.c (m32r_elf_object_p, m32r_elf_final_write_processing,
m32r_elf_merge_private_bfd_data): New machine types.
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.87
diff -c -r1.87 archures.c
*** bfd/archures.c 24 Nov 2003 18:06:39 -0000 1.87
--- bfd/archures.c 2 Dec 2003 08:56:08 -0000
***************
*** 272,277 ****
--- 272,278 ----
. bfd_arch_m32r, {* Renesas M32R (formerly Mitsubishi M32R/D) *}
.#define bfd_mach_m32r 1 {* For backwards compatibility. *}
.#define bfd_mach_m32rx 'x'
+ .#define bfd_mach_m32r2 '2'
. bfd_arch_mn10200, {* Matsushita MN10200 *}
. bfd_arch_mn10300, {* Matsushita MN10300 *}
.#define bfd_mach_mn10300 300
Index: bfd/cpu-m32r.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-m32r.c,v
retrieving revision 1.5
diff -c -r1.5 cpu-m32r.c
*** bfd/cpu-m32r.c 30 Nov 2002 08:39:36 -0000 1.5
--- bfd/cpu-m32r.c 2 Dec 2003 08:56:09 -0000
***************
*** 26,35 ****
bfd_default_compatible, bfd_default_scan, next }
#define NEXT NULL
static const bfd_arch_info_type arch_info_struct[] =
{
! N (bfd_mach_m32rx, "m32rx", FALSE, NULL)
};
#undef NEXT
--- 26,37 ----
bfd_default_compatible, bfd_default_scan, next }
#define NEXT NULL
+ #define M32R2_NEXT &arch_info_struct[1]
static const bfd_arch_info_type arch_info_struct[] =
{
! N (bfd_mach_m32rx, "m32rx", FALSE, M32R2_NEXT) ,
! N (bfd_mach_m32r2, "m32r2", FALSE, NULL)
};
#undef NEXT
Index: bfd/elf32-m32r.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-m32r.c,v
retrieving revision 1.37
diff -c -r1.37 elf32-m32r.c
*** bfd/elf32-m32r.c 1 Dec 2003 06:28:23 -0000 1.37
--- bfd/elf32-m32r.c 2 Dec 2003 08:56:09 -0000
***************
*** 1863,1868 ****
--- 1863,1869 ----
default:
case E_M32R_ARCH: (void) bfd_default_set_arch_mach (abfd, bfd_arch_m32r, bfd_mach_m32r); break;
case E_M32RX_ARCH: (void) bfd_default_set_arch_mach (abfd, bfd_arch_m32r, bfd_mach_m32rx); break;
+ case E_M32R2_ARCH: (void) bfd_default_set_arch_mach (abfd, bfd_arch_m32r, bfd_mach_m32r2); break;
}
return TRUE;
}
***************
*** 1880,1885 ****
--- 1881,1887 ----
default:
case bfd_mach_m32r: val = E_M32R_ARCH; break;
case bfd_mach_m32rx: val = E_M32RX_ARCH; break;
+ case bfd_mach_m32r2: val = E_M32R2_ARCH; break;
}
elf_elfheader (abfd)->e_flags &=~ EF_M32R_ARCH;
***************
*** 1946,1952 ****
if ((in_flags & EF_M32R_ARCH) != (out_flags & EF_M32R_ARCH))
{
! if ((in_flags & EF_M32R_ARCH) != E_M32R_ARCH)
{
(*_bfd_error_handler)
(_("%s: Instruction set mismatch with previous modules"),
--- 1948,1956 ----
if ((in_flags & EF_M32R_ARCH) != (out_flags & EF_M32R_ARCH))
{
! if (((in_flags & EF_M32R_ARCH) != E_M32R_ARCH)
! || ((out_flags & EF_M32R_ARCH) == E_M32R_ARCH)
! || ((in_flags & EF_M32R_ARCH) == E_M32R2_ARCH))
{
(*_bfd_error_handler)
(_("%s: Instruction set mismatch with previous modules"),
***************
*** 1979,1984 ****
--- 1983,1989 ----
default:
case E_M32R_ARCH: fprintf (file, _(": m32r instructions")); break;
case E_M32RX_ARCH: fprintf (file, _(": m32rx instructions")); break;
+ case E_M32R2_ARCH: fprintf (file, _(": m32r2 instructions")); break;
}
fputc ('\n', file);
[-- Attachment #8: cgen.m32r2.patch --]
[-- Type: application/octet-stream, Size: 62382 bytes --]
cgen/ChangLog
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* cpu/m32r.cpu : Add new model m32r2.
Add new instructions.
Replace occurrances of 'Mitsubishi' with 'Renesas'.
Changed PIPE attr of push from O to OS.
Care for Little-endian of M32R.
* cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
Care for Little-endian of M32R.
(parse_slo16): signed extension for value.
Index: cgen/cpu/m32r.cpu
===================================================================
RCS file: /cvs/src/src/cgen/cpu/m32r.cpu,v
retrieving revision 1.4
diff -c -r1.4 m32r.cpu
*** cgen/cpu/m32r.cpu 16 Jul 2003 05:35:48 -0000 1.4
--- cgen/cpu/m32r.cpu 2 Dec 2003 08:56:10 -0000
***************
*** 1,4 ****
! ; Mitsubishi M32R CPU description. -*- Scheme -*-
; Copyright (C) 2000 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
--- 1,4 ----
! ; Renesas M32R CPU description. -*- Scheme -*-
; Copyright (C) 2000 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
***************
*** 12,34 ****
(define-arch
(name m32r) ; name of cpu family
! (comment "Mitsubishi M32R")
(default-alignment aligned)
(insn-lsb0? #f)
! (machs m32r m32rx)
(isas m32r)
)
; Attributes.
; An attribute to describe which pipeline an insn runs in.
(define-attr
(for insn)
(type enum)
(name PIPE)
(comment "parallel execution pipeline selection")
! (values NONE O S OS)
)
; A derived attribute that says which insns can be executed in parallel
--- 12,36 ----
(define-arch
(name m32r) ; name of cpu family
! (comment "Renesas M32R")
(default-alignment aligned)
(insn-lsb0? #f)
! (machs m32r m32rx m32r2)
(isas m32r)
)
; Attributes.
; An attribute to describe which pipeline an insn runs in.
+ ; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.
+ ; Thease instructions have O attribute for m32rx and OS attribute for m32r2.
(define-attr
(for insn)
(type enum)
(name PIPE)
(comment "parallel execution pipeline selection")
! (values NONE O S OS O_OS)
)
; A derived attribute that says which insns can be executed in parallel
***************
*** 141,148 ****
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name m32rbf)
! (comment "Mitsubishi M32R base family")
! (endian big)
(word-bitsize 32)
; Override isa spec (??? keeps things simpler, though it was more true
; in the early days and not so much now).
--- 143,150 ----
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name m32rbf)
! (comment "Renesas M32R base family")
! (endian either)
(word-bitsize 32)
; Override isa spec (??? keeps things simpler, though it was more true
; in the early days and not so much now).
***************
*** 151,163 ****
(define-cpu
(name m32rxf)
! (comment "Mitsubishi M32Rx family")
! (endian big)
(word-bitsize 32)
; Generated files have an "x" suffix.
(file-transform "x")
)
(define-mach
(name m32r)
(comment "Generic M32R cpu")
--- 153,175 ----
(define-cpu
(name m32rxf)
! (comment "Renesas M32Rx family")
! (endian either)
(word-bitsize 32)
; Generated files have an "x" suffix.
(file-transform "x")
)
+ (define-cpu
+ (name m32r2f)
+ (comment "Renesas M32R2 family")
+ (endian either)
+ (word-bitsize 32)
+ ; Generated files have an "2" suffix.
+ (file-transform "2")
+ )
+
+
(define-mach
(name m32r)
(comment "Generic M32R cpu")
***************
*** 169,174 ****
--- 181,192 ----
(comment "M32RX cpu")
(cpu m32rxf)
)
+
+ (define-mach
+ (name m32r2)
+ (comment "M32R2 cpu")
+ (cpu m32r2f)
+ )
\f
; Model descriptions.
***************
*** 309,314 ****
--- 327,385 ----
() ; profile action (default)
)
)
+
+ (define-model
+ (name m32r2) (comment "m32r2") (attrs)
+ (mach m32r2)
+
+ ; ??? It's 6 stages but I forget the details right now.
+ (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
+ (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
+ (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
+
+ (unit u-exec "Execution Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((sr INT -1) (dr INT -1)) ; inputs
+ ((dr INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-cmp "Compare Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((src1 INT -1) (src2 INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ (unit u-mac "Multiply/Accumulate Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((src1 INT -1) (src2 INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ (unit u-cti "Branch Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((sr INT -1)) ; inputs
+ ((pc)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-load "Memory Load Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((sr INT)) ; inputs
+ ((dr INT)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-store "Memory Store Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((src1 INT) (src2 INT)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ )
\f
; The instruction fetch/execute cycle.
; This is split into two parts as sometimes more than one instruction is
***************
*** 379,386 ****
--- 450,459 ----
(df f-simm8 "simm8" () 8 8 INT #f #f)
(df f-simm16 "simm16" () 16 16 INT #f #f)
(dnf f-shift-op2 "shift op2" () 8 3)
+ (dnf f-uimm3 "uimm3" () 5 3)
(dnf f-uimm4 "uimm4" () 12 4)
(dnf f-uimm5 "uimm5" () 11 5)
+ (dnf f-uimm8 "uimm8" () 8 8)
(dnf f-uimm16 "uimm16" () 16 16)
(dnf f-uimm24 "uimm24" (ABS-ADDR RELOC) 8 24)
(dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16)
***************
*** 400,405 ****
--- 473,479 ----
(dnf f-accs "accs" () 12 2)
(dnf f-accd "accd" () 4 2)
(dnf f-bits67 "bits67" () 6 2)
+ (dnf f-bit4 "bit4" () 4 1)
(dnf f-bit14 "bit14" () 14 1)
(define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")
***************
*** 472,478 ****
(print-name h-cr)
(prefix "")
(values (psw 0) (cbr 1) (spi 2) (spu 3)
! (bpc 6) (bbpsw 8) (bbpc 14)
(cr0 0) (cr1 1) (cr2 2) (cr3 3)
(cr4 4) (cr5 5) (cr6 6) (cr7 7)
(cr8 8) (cr9 9) (cr10 10) (cr11 11)
--- 546,552 ----
(print-name h-cr)
(prefix "")
(values (psw 0) (cbr 1) (spi 2) (spu 3)
! (bpc 6) (bbpsw 8) (bbpc 14) (evb 5)
(cr0 0) (cr1 1) (cr2 2) (cr3 3)
(cr4 4) (cr5 5) (cr6 6) (cr7 7)
(cr8 8) (cr9 9) (cr10 10) (cr11 11)
***************
*** 506,512 ****
(define-hardware
(name h-accums)
(comment "accumulators")
! (attrs (MACH m32rx))
(type register DI (2))
(indices keyword "" ((a0 0) (a1 1)))
; get/set so a0 accesses are redirected to h-accum.
--- 580,586 ----
(define-hardware
(name h-accums)
(comment "accumulators")
! (attrs (MACH m32rx,m32r2))
(type register DI (2))
(indices keyword "" ((a0 0) (a1 1)))
; get/set so a0 accesses are redirected to h-accum.
***************
*** 571,584 ****
(dnop simm8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-simm8)
(dnop simm16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-simm16)
(dnop uimm4 "4 bit trap number" (HASH-PREFIX) h-uint f-uimm4)
(dnop uimm5 "5 bit shift count" (HASH-PREFIX) h-uint f-uimm5)
(dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16)
! (dnop imm1 "1 bit immediate" ((MACH m32rx) HASH-PREFIX) h-uint f-imm1)
! (dnop accd "accumulator destination register" ((MACH m32rx)) h-accums f-accd)
! (dnop accs "accumulator source register" ((MACH m32rx)) h-accums f-accs)
! (dnop acc "accumulator reg (d)" ((MACH m32rx)) h-accums f-acc)
; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.
; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use HASH-PREFIX.
--- 645,660 ----
(dnop simm8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-simm8)
(dnop simm16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-simm16)
+ (dnop uimm3 "3 bit unsigned number" (HASH-PREFIX) h-uint f-uimm3)
(dnop uimm4 "4 bit trap number" (HASH-PREFIX) h-uint f-uimm4)
(dnop uimm5 "5 bit shift count" (HASH-PREFIX) h-uint f-uimm5)
+ (dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8)
(dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16)
! (dnop imm1 "1 bit immediate" ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1)
! (dnop accd "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd)
! (dnop accs "accumulator source register" ((MACH m32rx,m32r2)) h-accums f-accs)
! (dnop acc "accumulator reg (d)" ((MACH m32rx,m32r2)) h-accums f-acc)
; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.
; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use HASH-PREFIX.
***************
*** 676,681 ****
--- 752,771 ----
(comment "non-public m32rx insn")
)
+ (define-attr
+ (for insn)
+ (type boolean)
+ (name SPECIAL_M32R)
+ (comment "non-public m32r insn")
+ )
+
+ (define-attr
+ (for insn)
+ (type boolean)
+ (name SPECIAL_FLOAT)
+ (comment "floating point insn")
+ )
+
; IDOC attribute for instruction documentation.
(define-attr
***************
*** 727,733 ****
(+ OP1_4 dr simm8)
(set dr (add dr simm8))
((m32r/d (unit u-exec))
! (m32rx (unit u-exec)))
)
(dni addv "addv"
--- 817,824 ----
(+ OP1_4 dr simm8)
(set dr (add dr simm8))
((m32r/d (unit u-exec))
! (m32rx (unit u-exec))
! (m32r2 (unit u-exec)))
)
(dni addv "addv"
***************
*** 766,772 ****
(+ OP1_7 (f-r1 12) disp8)
(if condbit (set pc disp8))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti)))
)
(dnmi bc8r "relaxable bc8"
--- 857,864 ----
(+ OP1_7 (f-r1 12) disp8)
(if condbit (set pc disp8))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bc8r "relaxable bc8"
***************
*** 781,787 ****
(+ OP1_15 (f-r1 12) disp24)
(if condbit (set pc disp24))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti)))
)
(dnmi bc24r "relaxable bc24"
--- 873,880 ----
(+ OP1_15 (f-r1 12) disp24)
(if condbit (set pc disp24))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bc24r "relaxable bc24"
***************
*** 796,802 ****
(+ OP1_11 OP2_0 src1 src2 disp16)
(if (eq src1 src2) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
! (m32rx (unit u-cti) (unit u-cmp (cycles 0))))
)
(define-pmacro (cbranch sym comment op2-op comp-op)
--- 889,896 ----
(+ OP1_11 OP2_0 src1 src2 disp16)
(if (eq src1 src2) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
! (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
! (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
)
(define-pmacro (cbranch sym comment op2-op comp-op)
***************
*** 805,811 ****
(+ OP1_11 op2-op (f-r1 0) src2 disp16)
(if (comp-op src2 (const WI 0)) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
! (m32rx (unit u-cti) (unit u-cmp (cycles 0))))
)
)
(cbranch beqz "beqz" OP2_8 eq)
--- 899,906 ----
(+ OP1_11 op2-op (f-r1 0) src2 disp16)
(if (comp-op src2 (const WI 0)) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
! (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
! (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
)
)
(cbranch beqz "beqz" OP2_8 eq)
***************
*** 824,830 ****
(add (and pc (const -4)) (const 4)))
(set pc disp8))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti)))
)
(dnmi bl8r "relaxable bl8"
--- 919,926 ----
(add (and pc (const -4)) (const 4)))
(set pc disp8))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bl8r "relaxable bl8"
***************
*** 841,847 ****
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti)))
)
(dnmi bl24r "relaxable bl24"
--- 937,944 ----
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bl24r "relaxable bl24"
***************
*** 851,857 ****
)
(dni bcl8 "bcl with 8 bit displacement"
! (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) (IDOC BR))
"bcl.s $disp8"
(+ OP1_7 (f-r1 8) disp8)
(if condbit
--- 948,954 ----
)
(dni bcl8 "bcl with 8 bit displacement"
! (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
"bcl.s $disp8"
(+ OP1_7 (f-r1 8) disp8)
(if condbit
***************
*** 860,887 ****
(add (and pc (const -4))
(const 4)))
(set pc disp8)))
! ((m32rx (unit u-cti)))
)
(dnmi bcl8r "relaxable bcl8"
! (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) RELAXABLE (IDOC BR))
"bcl $disp8"
(emit bcl8 disp8)
)
(dni bcl24 "bcl with 24 bit displacement"
! (COND-CTI (MACH m32rx) (IDOC BR))
"bcl.l $disp24"
(+ OP1_15 (f-r1 8) disp24)
(if condbit
(sequence ()
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24)))
! ((m32rx (unit u-cti)))
)
(dnmi bcl24r "relaxable bcl24"
! (COND-CTI (MACH m32rx) RELAXED (IDOC BR))
"bcl $disp24"
(emit bcl24 disp24)
)
--- 957,986 ----
(add (and pc (const -4))
(const 4)))
(set pc disp8)))
! ((m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bcl8r "relaxable bcl8"
! (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
"bcl $disp8"
(emit bcl8 disp8)
)
(dni bcl24 "bcl with 24 bit displacement"
! (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
"bcl.l $disp24"
(+ OP1_15 (f-r1 8) disp24)
(if condbit
(sequence ()
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24)))
! ((m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bcl24r "relaxable bcl24"
! (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
"bcl $disp24"
(emit bcl24 disp24)
)
***************
*** 892,898 ****
(+ OP1_7 (f-r1 13) disp8)
(if (not condbit) (set pc disp8))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti)))
)
(dnmi bnc8r "relaxable bnc8"
--- 991,998 ----
(+ OP1_7 (f-r1 13) disp8)
(if (not condbit) (set pc disp8))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bnc8r "relaxable bnc8"
***************
*** 907,913 ****
(+ OP1_15 (f-r1 13) disp24)
(if (not condbit) (set pc disp24))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti)))
)
(dnmi bnc24r "relaxable bnc24"
--- 1007,1014 ----
(+ OP1_15 (f-r1 13) disp24)
(if (not condbit) (set pc disp24))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bnc24r "relaxable bnc24"
***************
*** 922,928 ****
(+ OP1_11 OP2_1 src1 src2 disp16)
(if (ne src1 src2) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
! (m32rx (unit u-cti) (unit u-cmp (cycles 0))))
)
(dni bra8 "bra with 8 bit displacement"
--- 1023,1030 ----
(+ OP1_11 OP2_1 src1 src2 disp16)
(if (ne src1 src2) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
! (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
! (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
)
(dni bra8 "bra with 8 bit displacement"
***************
*** 931,937 ****
(+ OP1_7 (f-r1 15) disp8)
(set pc disp8)
((m32r/d (unit u-cti))
! (m32rx (unit u-cti)))
)
(dnmi bra8r "relaxable bra8"
--- 1033,1040 ----
(+ OP1_7 (f-r1 15) disp8)
(set pc disp8)
((m32r/d (unit u-cti))
! (m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bra8r "relaxable bra8"
***************
*** 946,952 ****
(+ OP1_15 (f-r1 15) disp24)
(set pc disp24)
((m32r/d (unit u-cti))
! (m32rx (unit u-cti)))
)
(dnmi bra24r "relaxable bra24"
--- 1049,1056 ----
(+ OP1_15 (f-r1 15) disp24)
(set pc disp24)
((m32r/d (unit u-cti))
! (m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bra24r "relaxable bra24"
***************
*** 956,962 ****
)
(dni bncl8 "bncl with 8 bit displacement"
! (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) (IDOC BR))
"bncl.s $disp8"
(+ OP1_7 (f-r1 9) disp8)
(if (not condbit)
--- 1060,1066 ----
)
(dni bncl8 "bncl with 8 bit displacement"
! (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
"bncl.s $disp8"
(+ OP1_7 (f-r1 9) disp8)
(if (not condbit)
***************
*** 965,992 ****
(add (and pc (const -4))
(const 4)))
(set pc disp8)))
! ((m32rx (unit u-cti)))
)
(dnmi bncl8r "relaxable bncl8"
! (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) RELAXABLE (IDOC BR))
"bncl $disp8"
(emit bncl8 disp8)
)
(dni bncl24 "bncl with 24 bit displacement"
! (COND-CTI (MACH m32rx) (IDOC BR))
"bncl.l $disp24"
(+ OP1_15 (f-r1 9) disp24)
(if (not condbit)
(sequence ()
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24)))
! ((m32rx (unit u-cti)))
)
(dnmi bncl24r "relaxable bncl24"
! (COND-CTI (MACH m32rx) RELAXED (IDOC BR))
"bncl $disp24"
(emit bncl24 disp24)
)
--- 1069,1098 ----
(add (and pc (const -4))
(const 4)))
(set pc disp8)))
! ((m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bncl8r "relaxable bncl8"
! (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
"bncl $disp8"
(emit bncl8 disp8)
)
(dni bncl24 "bncl with 24 bit displacement"
! (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
"bncl.l $disp24"
(+ OP1_15 (f-r1 9) disp24)
(if (not condbit)
(sequence ()
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24)))
! ((m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dnmi bncl24r "relaxable bncl24"
! (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
"bncl $disp24"
(emit bncl24 disp24)
)
***************
*** 997,1003 ****
(+ OP1_0 OP2_4 src1 src2)
(set condbit (lt src1 src2))
((m32r/d (unit u-cmp))
! (m32rx (unit u-cmp)))
)
(dni cmpi "cmpi"
--- 1103,1110 ----
(+ OP1_0 OP2_4 src1 src2)
(set condbit (lt src1 src2))
((m32r/d (unit u-cmp))
! (m32rx (unit u-cmp))
! (m32r2 (unit u-cmp)))
)
(dni cmpi "cmpi"
***************
*** 1006,1012 ****
(+ OP1_8 (f-r1 0) OP2_4 src2 simm16)
(set condbit (lt src2 simm16))
((m32r/d (unit u-cmp))
! (m32rx (unit u-cmp)))
)
(dni cmpu "cmpu"
--- 1113,1120 ----
(+ OP1_8 (f-r1 0) OP2_4 src2 simm16)
(set condbit (lt src2 simm16))
((m32r/d (unit u-cmp))
! (m32rx (unit u-cmp))
! (m32r2 (unit u-cmp)))
)
(dni cmpu "cmpu"
***************
*** 1015,1021 ****
(+ OP1_0 OP2_5 src1 src2)
(set condbit (ltu src1 src2))
((m32r/d (unit u-cmp))
! (m32rx (unit u-cmp)))
)
(dni cmpui "cmpui"
--- 1123,1130 ----
(+ OP1_0 OP2_5 src1 src2)
(set condbit (ltu src1 src2))
((m32r/d (unit u-cmp))
! (m32rx (unit u-cmp))
! (m32r2 (unit u-cmp)))
)
(dni cmpui "cmpui"
***************
*** 1024,1046 ****
(+ OP1_8 (f-r1 0) OP2_5 src2 simm16)
(set condbit (ltu src2 simm16))
((m32r/d (unit u-cmp))
! (m32rx (unit u-cmp)))
)
(dni cmpeq "cmpeq"
! ((MACH m32rx) (PIPE OS) (IDOC ALU))
"cmpeq $src1,$src2"
(+ OP1_0 OP2_6 src1 src2)
(set condbit (eq src1 src2))
! ((m32rx (unit u-cmp)))
)
(dni cmpz "cmpz"
! ((MACH m32rx) (PIPE OS) (IDOC ALU))
"cmpz $src2"
(+ OP1_0 OP2_7 (f-r1 0) src2)
(set condbit (eq src2 (const 0)))
! ((m32rx (unit u-cmp)))
)
(dni div "div"
--- 1133,1158 ----
(+ OP1_8 (f-r1 0) OP2_5 src2 simm16)
(set condbit (ltu src2 simm16))
((m32r/d (unit u-cmp))
! (m32rx (unit u-cmp))
! (m32r2 (unit u-cmp)))
)
(dni cmpeq "cmpeq"
! ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
"cmpeq $src1,$src2"
(+ OP1_0 OP2_6 src1 src2)
(set condbit (eq src1 src2))
! ((m32rx (unit u-cmp))
! (m32r2 (unit u-cmp)))
)
(dni cmpz "cmpz"
! ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
"cmpz $src2"
(+ OP1_0 OP2_7 (f-r1 0) src2)
(set condbit (eq src2 (const 0)))
! ((m32rx (unit u-cmp))
! (m32r2 (unit u-cmp)))
)
(dni div "div"
***************
*** 1049,1055 ****
(+ OP1_9 OP2_0 dr sr (f-simm16 0))
(if (ne sr (const 0)) (set dr (div dr sr)))
((m32r/d (unit u-exec (cycles 37)))
! (m32rx (unit u-exec (cycles 37))))
)
(dni divu "divu"
--- 1161,1168 ----
(+ OP1_9 OP2_0 dr sr (f-simm16 0))
(if (ne sr (const 0)) (set dr (div dr sr)))
((m32r/d (unit u-exec (cycles 37)))
! (m32rx (unit u-exec (cycles 37)))
! (m32r2 (unit u-exec (cycles 37))))
)
(dni divu "divu"
***************
*** 1058,1064 ****
(+ OP1_9 OP2_1 dr sr (f-simm16 0))
(if (ne sr (const 0)) (set dr (udiv dr sr)))
((m32r/d (unit u-exec (cycles 37)))
! (m32rx (unit u-exec (cycles 37))))
)
(dni rem "rem"
--- 1171,1178 ----
(+ OP1_9 OP2_1 dr sr (f-simm16 0))
(if (ne sr (const 0)) (set dr (udiv dr sr)))
((m32r/d (unit u-exec (cycles 37)))
! (m32rx (unit u-exec (cycles 37)))
! (m32r2 (unit u-exec (cycles 37))))
)
(dni rem "rem"
***************
*** 1068,1074 ****
; FIXME: Check rounding direction.
(if (ne sr (const 0)) (set dr (mod dr sr)))
((m32r/d (unit u-exec (cycles 37)))
! (m32rx (unit u-exec (cycles 37))))
)
(dni remu "remu"
--- 1182,1189 ----
; FIXME: Check rounding direction.
(if (ne sr (const 0)) (set dr (mod dr sr)))
((m32r/d (unit u-exec (cycles 37)))
! (m32rx (unit u-exec (cycles 37)))
! (m32r2 (unit u-exec (cycles 37))))
)
(dni remu "remu"
***************
*** 1078,1108 ****
; FIXME: Check rounding direction.
(if (ne sr (const 0)) (set dr (umod dr sr)))
((m32r/d (unit u-exec (cycles 37)))
! (m32rx (unit u-exec (cycles 37))))
)
(dni divh "divh"
! ((MACH m32rx) (IDOC ALU))
"divh $dr,$sr"
(+ OP1_9 OP2_0 dr sr (f-simm16 #x10))
(if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))
! ((m32rx (unit u-exec (cycles 21))))
)
(dni jc "jc"
! (COND-CTI (MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
"jc $sr"
(+ OP1_1 (f-r1 12) OP2_12 sr)
(if condbit (set pc (and sr (const -4))))
! ((m32rx (unit u-cti)))
)
(dni jnc "jnc"
! (COND-CTI (MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
"jnc $sr"
(+ OP1_1 (f-r1 13) OP2_12 sr)
(if (not condbit) (set pc (and sr (const -4))))
! ((m32rx (unit u-cti)))
)
(dni jl "jl"
--- 1193,1287 ----
; FIXME: Check rounding direction.
(if (ne sr (const 0)) (set dr (umod dr sr)))
((m32r/d (unit u-exec (cycles 37)))
! (m32rx (unit u-exec (cycles 37)))
! (m32r2 (unit u-exec (cycles 37))))
! )
!
! (dni remh "remh"
! ((MACH m32r2))
! "remh $dr,$sr"
! (+ OP1_9 OP2_2 dr sr (f-simm16 #x10))
! ; FIXME: Check rounding direction.
! (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr)))
! ((m32r2 (unit u-exec (cycles 21))))
! )
!
! (dni remuh "remuh"
! ((MACH m32r2))
! "remuh $dr,$sr"
! (+ OP1_9 OP2_3 dr sr (f-simm16 #x10))
! ; FIXME: Check rounding direction.
! (if (ne sr (const 0)) (set dr (umod dr sr)))
! ((m32r2 (unit u-exec (cycles 21))))
! )
!
! (dni remb "remb"
! ((MACH m32r2))
! "remb $dr,$sr"
! (+ OP1_9 OP2_2 dr sr (f-simm16 #x18))
! ; FIXME: Check rounding direction.
! (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr)))
! ((m32r2 (unit u-exec (cycles 21))))
! )
!
! (dni remub "remub"
! ((MACH m32r2))
! "remub $dr,$sr"
! (+ OP1_9 OP2_3 dr sr (f-simm16 #x18))
! ; FIXME: Check rounding direction.
! (if (ne sr (const 0)) (set dr (umod dr sr)))
! ((m32r2 (unit u-exec (cycles 21))))
! )
!
! (dni divuh "divuh"
! ((MACH m32r2))
! "divuh $dr,$sr"
! (+ OP1_9 OP2_1 dr sr (f-simm16 #x10))
! (if (ne sr (const 0)) (set dr (udiv dr sr)))
! ((m32r2 (unit u-exec (cycles 21))))
! )
!
! (dni divb "divb"
! ((MACH m32r2))
! "divb $dr,$sr"
! (+ OP1_9 OP2_0 dr sr (f-simm16 #x18))
! (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr)))
! ((m32r2 (unit u-exec (cycles 21))))
! )
!
! (dni divub "divub"
! ((MACH m32r2))
! "divub $dr,$sr"
! (+ OP1_9 OP2_1 dr sr (f-simm16 #x18))
! (if (ne sr (const 0)) (set dr (udiv dr sr)))
! ((m32r2 (unit u-exec (cycles 21))))
)
(dni divh "divh"
! ((MACH m32rx,m32r2) (IDOC ALU))
"divh $dr,$sr"
(+ OP1_9 OP2_0 dr sr (f-simm16 #x10))
(if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))
! ((m32rx (unit u-exec (cycles 21)))
! (m32r2 (unit u-exec (cycles 21))))
)
(dni jc "jc"
! (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"jc $sr"
(+ OP1_1 (f-r1 12) OP2_12 sr)
(if condbit (set pc (and sr (const -4))))
! ((m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dni jnc "jnc"
! (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"jnc $sr"
(+ OP1_1 (f-r1 13) OP2_12 sr)
(if (not condbit) (set pc (and sr (const -4))))
! ((m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dni jl "jl"
***************
*** 1114,1120 ****
(add (and pc (const -4)) (const 4)))
(set pc (and sr (const -4))))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti)))
)
(dni jmp "jmp"
--- 1293,1300 ----
(add (and pc (const -4)) (const 4)))
(set pc (and sr (const -4))))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(dni jmp "jmp"
***************
*** 1136,1142 ****
; (add WI (and WI pc (const WI -4)) (const WI 4))))
; (set WI pc sr))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti)))
)
(define-pmacro (no-ext-expr mode expr) expr)
--- 1316,1323 ----
; (add WI (and WI pc (const WI -4)) (const WI 4))))
; (set WI pc sr))
((m32r/d (unit u-cti))
! (m32rx (unit u-cti))
! (m32r2 (unit u-cti)))
)
(define-pmacro (no-ext-expr mode expr) expr)
***************
*** 1151,1157 ****
(+ OP1_2 op2-op dr sr)
(set dr (ext-op WI (mem mode sr)))
((m32r/d (unit u-load))
! (m32rx (unit u-load)))
)
(dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")
(NO-DIS (PIPE O) (IDOC MEM))
--- 1332,1339 ----
(+ OP1_2 op2-op dr sr)
(set dr (ext-op WI (mem mode sr)))
((m32r/d (unit u-load))
! (m32rx (unit u-load))
! (m32r2 (unit u-load)))
)
(dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")
(NO-DIS (PIPE O) (IDOC MEM))
***************
*** 1163,1169 ****
(+ OP1_10 op2-op dr sr slo16)
(set dr (ext-op WI (mem mode (add sr slo16))))
((m32r/d (unit u-load (cycles 2)))
! (m32rx (unit u-load (cycles 2))))
)
(dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")
(NO-DIS (IDOC MEM))
--- 1345,1352 ----
(+ OP1_10 op2-op dr sr slo16)
(set dr (ext-op WI (mem mode (add sr slo16))))
((m32r/d (unit u-load (cycles 2)))
! (m32rx (unit u-load (cycles 2)))
! (m32r2 (unit u-load (cycles 2))))
)
(dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")
(NO-DIS (IDOC MEM))
***************
*** 1199,1204 ****
--- 1382,1389 ----
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
(m32rx (unit u-load)
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
+ (m32r2 (unit u-load)
+ (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
)
)
***************
*** 1254,1260 ****
(set (reg h-lock) (const BI 1))
(set dr (mem WI sr)))
((m32r/d (unit u-load))
! (m32rx (unit u-load)))
)
(dni machi "machi"
--- 1439,1446 ----
(set (reg h-lock) (const BI 1))
(set dr (mem WI sr)))
((m32r/d (unit u-load))
! (m32rx (unit u-load))
! (m32r2 (unit u-load)))
)
(dni machi "machi"
***************
*** 1281,1287 ****
)
(dni machi-a "machi-a"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"machi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 4) src2)
(set acc
--- 1467,1473 ----
)
(dni machi-a "machi-a"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"machi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 4) src2)
(set acc
***************
*** 1294,1300 ****
(ext DI (trunc HI (sra WI src2 (const 16))))))
(const 8))
(const 8)))
! ((m32rx (unit u-mac)))
)
(dni maclo "maclo"
--- 1480,1487 ----
(ext DI (trunc HI (sra WI src2 (const 16))))))
(const 8))
(const 8)))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
(dni maclo "maclo"
***************
*** 1315,1321 ****
)
(dni maclo-a "maclo-a"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"maclo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 5) src2)
(set acc
--- 1502,1508 ----
)
(dni maclo-a "maclo-a"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"maclo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 5) src2)
(set acc
***************
*** 1328,1334 ****
(ext DI (trunc HI src2))))
(const 8))
(const 8)))
! ((m32rx (unit u-mac)))
)
(dni macwhi "macwhi"
--- 1515,1522 ----
(ext DI (trunc HI src2))))
(const 8))
(const 8)))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
(dni macwhi "macwhi"
***************
*** 1349,1355 ****
)
(dni macwhi-a "macwhi-a"
! ((MACH m32rx) (PIPE S) SPECIAL (IDOC MAC))
"macwhi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 6) src2)
; Note that this doesn't do the sign extension, which is correct.
--- 1537,1543 ----
)
(dni macwhi-a "macwhi-a"
! ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
"macwhi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 6) src2)
; Note that this doesn't do the sign extension, which is correct.
***************
*** 1357,1363 ****
(add acc
(mul (ext DI src1)
(ext DI (trunc HI (sra src2 (const 16)))))))
! ((m32rx (unit u-mac)))
)
(dni macwlo "macwlo"
--- 1545,1552 ----
(add acc
(mul (ext DI src1)
(ext DI (trunc HI (sra src2 (const 16)))))))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
(dni macwlo "macwlo"
***************
*** 1378,1384 ****
)
(dni macwlo-a "macwlo-a"
! ((MACH m32rx) (PIPE S) SPECIAL (IDOC MAC))
"macwlo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 7) src2)
; Note that this doesn't do the sign extension, which is correct.
--- 1567,1573 ----
)
(dni macwlo-a "macwlo-a"
! ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
"macwlo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 7) src2)
; Note that this doesn't do the sign extension, which is correct.
***************
*** 1386,1392 ****
(add acc
(mul (ext DI src1)
(ext DI (trunc HI src2)))))
! ((m32rx (unit u-mac)))
)
(dni mul "mul"
--- 1575,1582 ----
(add acc
(mul (ext DI src1)
(ext DI (trunc HI src2)))))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
(dni mul "mul"
***************
*** 1395,1401 ****
(+ OP1_1 OP2_6 dr sr)
(set dr (mul dr sr))
((m32r/d (unit u-exec (cycles 4)))
! (m32rx (unit u-exec (cycles 4))))
)
(dni mulhi "mulhi"
--- 1585,1592 ----
(+ OP1_1 OP2_6 dr sr)
(set dr (mul dr sr))
((m32r/d (unit u-exec (cycles 4)))
! (m32rx (unit u-exec (cycles 4)))
! (m32r2 (unit u-exec (cycles 4))))
)
(dni mulhi "mulhi"
***************
*** 1414,1420 ****
)
(dni mulhi-a "mulhi-a"
! ((MACH m32rx) (PIPE S) (IDOC ACCUM))
"mulhi $src1,$src2,$acc"
(+ OP1_3 (f-op23 0) src1 acc src2)
(set acc
--- 1605,1611 ----
)
(dni mulhi-a "mulhi-a"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mulhi $src1,$src2,$acc"
(+ OP1_3 (f-op23 0) src1 acc src2)
(set acc
***************
*** 1425,1431 ****
(ext DI (trunc HI (sra WI src2 (const 16)))))
(const 16))
(const 16)))
! ((m32rx (unit u-mac)))
)
(dni mullo "mullo"
--- 1616,1623 ----
(ext DI (trunc HI (sra WI src2 (const 16)))))
(const 16))
(const 16)))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
(dni mullo "mullo"
***************
*** 1444,1450 ****
)
(dni mullo-a "mullo-a"
! ((MACH m32rx) (PIPE S) (IDOC ACCUM))
"mullo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 1) src2)
(set acc
--- 1636,1642 ----
)
(dni mullo-a "mullo-a"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mullo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 1) src2)
(set acc
***************
*** 1455,1461 ****
(ext DI (trunc HI src2)))
(const 16))
(const 16)))
! ((m32rx (unit u-mac)))
)
(dni mulwhi "mulwhi"
--- 1647,1654 ----
(ext DI (trunc HI src2)))
(const 16))
(const 16)))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
(dni mulwhi "mulwhi"
***************
*** 1474,1487 ****
)
(dni mulwhi-a "mulwhi-a"
! ((MACH m32rx) (PIPE S) SPECIAL (IDOC ACCUM))
"mulwhi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 2) src2)
; Note that this doesn't do the sign extension, which is correct.
(set acc
(mul (ext DI src1)
(ext DI (trunc HI (sra src2 (const 16))))))
! ((m32rx (unit u-mac)))
)
(dni mulwlo "mulwlo"
--- 1667,1681 ----
)
(dni mulwhi-a "mulwhi-a"
! ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
"mulwhi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 2) src2)
; Note that this doesn't do the sign extension, which is correct.
(set acc
(mul (ext DI src1)
(ext DI (trunc HI (sra src2 (const 16))))))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
(dni mulwlo "mulwlo"
***************
*** 1500,1513 ****
)
(dni mulwlo-a "mulwlo-a"
! ((MACH m32rx) (PIPE S) SPECIAL (IDOC ACCUM))
"mulwlo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 3) src2)
; Note that this doesn't do the sign extension, which is correct.
(set acc
(mul (ext DI src1)
(ext DI (trunc HI src2))))
! ((m32rx (unit u-mac)))
)
(dni mv "mv"
--- 1694,1708 ----
)
(dni mulwlo-a "mulwlo-a"
! ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
"mulwlo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 3) src2)
; Note that this doesn't do the sign extension, which is correct.
(set acc
(mul (ext DI src1)
(ext DI (trunc HI src2))))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
(dni mv "mv"
***************
*** 1527,1537 ****
)
(dni mvfachi-a "mvfachi-a"
! ((MACH m32rx) (PIPE S) (IDOC ACCUM))
"mvfachi $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 0))
(set dr (trunc WI (sra DI accs (const 32))))
! ((m32rx (unit u-exec (cycles 2))))
)
(dni mvfaclo "mvfaclo"
--- 1722,1733 ----
)
(dni mvfachi-a "mvfachi-a"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvfachi $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 0))
(set dr (trunc WI (sra DI accs (const 32))))
! ((m32rx (unit u-exec (cycles 2)))
! (m32r2 (unit u-exec (cycles 2))))
)
(dni mvfaclo "mvfaclo"
***************
*** 1543,1553 ****
)
(dni mvfaclo-a "mvfaclo-a"
! ((MACH m32rx) (PIPE S) (IDOC ACCUM))
"mvfaclo $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 1))
(set dr (trunc WI accs))
! ((m32rx (unit u-exec (cycles 2))))
)
(dni mvfacmi "mvfacmi"
--- 1739,1750 ----
)
(dni mvfaclo-a "mvfaclo-a"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvfaclo $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 1))
(set dr (trunc WI accs))
! ((m32rx (unit u-exec (cycles 2)))
! (m32r2 (unit u-exec (cycles 2))))
)
(dni mvfacmi "mvfacmi"
***************
*** 1559,1569 ****
)
(dni mvfacmi-a "mvfacmi-a"
! ((MACH m32rx) (PIPE S) (IDOC ACCUM))
"mvfacmi $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 2))
(set dr (trunc WI (sra DI accs (const 16))))
! ((m32rx (unit u-exec (cycles 2))))
)
(dni mvfc "mvfc"
--- 1756,1767 ----
)
(dni mvfacmi-a "mvfacmi-a"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvfacmi $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 2))
(set dr (trunc WI (sra DI accs (const 16))))
! ((m32rx (unit u-exec (cycles 2)))
! (m32r2 (unit u-exec (cycles 2))))
)
(dni mvfc "mvfc"
***************
*** 1586,1599 ****
)
(dni mvtachi-a "mvtachi-a"
! ((MACH m32rx) (PIPE S) (IDOC ACCUM))
"mvtachi $src1,$accs"
(+ OP1_5 src1 OP2_7 accs (f-op3 0))
(set accs
(or DI
(and DI accs (const DI #xffffffff))
(sll DI (ext DI src1) (const 32))))
! ((m32rx (unit u-exec (in sr src1))))
)
(dni mvtaclo "mvtaclo"
--- 1784,1798 ----
)
(dni mvtachi-a "mvtachi-a"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvtachi $src1,$accs"
(+ OP1_5 src1 OP2_7 accs (f-op3 0))
(set accs
(or DI
(and DI accs (const DI #xffffffff))
(sll DI (ext DI src1) (const 32))))
! ((m32rx (unit u-exec (in sr src1)))
! (m32r2 (unit u-exec (in sr src1))))
)
(dni mvtaclo "mvtaclo"
***************
*** 1608,1621 ****
)
(dni mvtaclo-a "mvtaclo-a"
! ((MACH m32rx) (PIPE S) (IDOC ACCUM))
"mvtaclo $src1,$accs"
(+ OP1_5 src1 OP2_7 accs (f-op3 1))
(set accs
(or DI
(and DI accs (const DI #xffffffff00000000))
(zext DI src1)))
! ((m32rx (unit u-exec (in sr src1))))
)
(dni mvtc "mvtc"
--- 1807,1821 ----
)
(dni mvtaclo-a "mvtaclo-a"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvtaclo $src1,$accs"
(+ OP1_5 src1 OP2_7 accs (f-op3 1))
(set accs
(or DI
(and DI accs (const DI #xffffffff00000000))
(zext DI src1)))
! ((m32rx (unit u-exec (in sr src1)))
! (m32r2 (unit u-exec (in sr src1))))
)
(dni mvtc "mvtc"
***************
*** 1642,1648 ****
; FIXME: quick hack: parallel nops don't contribute to cycle count.
; Other kinds of nops do however (which we currently ignore).
((m32r/d (unit u-exec (cycles 0)))
! (m32rx (unit u-exec (cycles 0))))
)
(dni not "not"
--- 1842,1849 ----
; FIXME: quick hack: parallel nops don't contribute to cycle count.
; Other kinds of nops do however (which we currently ignore).
((m32r/d (unit u-exec (cycles 0)))
! (m32rx (unit u-exec (cycles 0)))
! (m32r2 (unit u-exec (cycles 0))))
)
(dni not "not"
***************
*** 1672,1678 ****
)
(dni rac-dsi "rac-dsi"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"rac $accd,$accs,$imm1"
(+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
(sequence ((DI tmp1))
--- 1873,1879 ----
)
(dni rac-dsi "rac-dsi"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rac $accd,$accs,$imm1"
(+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
(sequence ((DI tmp1))
***************
*** 1686,1702 ****
(const DI #xffff800000000000))
(else (and tmp1 (const DI #xffffffffffff0000)))))
)
! ((m32rx (unit u-mac)))
)
(dnmi rac-d "rac-d"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"rac $accd"
(emit rac-dsi accd (f-accs 0) (f-imm1 0))
)
(dnmi rac-ds "rac-ds"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"rac $accd,$accs"
(emit rac-dsi accd accs (f-imm1 0))
)
--- 1887,1904 ----
(const DI #xffff800000000000))
(else (and tmp1 (const DI #xffffffffffff0000)))))
)
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
(dnmi rac-d "rac-d"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rac $accd"
(emit rac-dsi accd (f-accs 0) (f-imm1 0))
)
(dnmi rac-ds "rac-ds"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rac $accd,$accs"
(emit rac-dsi accd accs (f-imm1 0))
)
***************
*** 1730,1736 ****
)
(dni rach-dsi "rach-dsi"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"rach $accd,$accs,$imm1"
(+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
(sequence ((DI tmp1))
--- 1932,1938 ----
)
(dni rach-dsi "rach-dsi"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rach $accd,$accs,$imm1"
(+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
(sequence ((DI tmp1))
***************
*** 1744,1760 ****
(const DI #xffff800000000000))
(else (and tmp1 (const DI #xffffffff00000000)))))
)
! ((m32rx (unit u-mac)))
)
(dnmi rach-d "rach-d"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"rach $accd"
(emit rach-dsi accd (f-accs 0) (f-imm1 0))
)
(dnmi rach-ds "rach-ds"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"rach $accd,$accs"
(emit rach-dsi accd accs (f-imm1 0))
)
--- 1946,1963 ----
(const DI #xffff800000000000))
(else (and tmp1 (const DI #xffffffff00000000)))))
)
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
(dnmi rach-d "rach-d"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rach $accd"
(emit rach-dsi accd (f-accs 0) (f-imm1 0))
)
(dnmi rach-ds "rach-ds"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rach $accd,$accs"
(emit rach-dsi accd accs (f-imm1 0))
)
***************
*** 1786,1792 ****
(define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
(begin
! (dni sym sym ((PIPE O) (IDOC ALU))
(.str sym " $dr,$sr")
(+ OP1_1 op2-r-op dr sr)
(set dr (sem-op dr (and sr (const 31))))
--- 1989,1995 ----
(define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
(begin
! (dni sym sym ((PIPE O_OS) (IDOC ALU))
(.str sym " $dr,$sr")
(+ OP1_1 op2-r-op dr sr)
(set dr (sem-op dr (and sr (const 31))))
***************
*** 1798,1804 ****
(set dr (sem-op sr (and WI simm16 (const 31))))
()
)
! (dni (.sym sym "i") sym ((PIPE O) (IDOC ALU))
(.str sym "i $dr,$uimm5")
(+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
(set dr (sem-op dr uimm5))
--- 2001,2007 ----
(set dr (sem-op sr (and WI simm16 (const 31))))
()
)
! (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU))
(.str sym "i $dr,$uimm5")
(+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
(set dr (sem-op dr uimm5))
***************
*** 1818,1824 ****
(+ OP1_2 op2-op src1 src2)
(set mode (mem mode src2) src1)
((m32r/d (unit u-store (cycles 1)))
! (m32rx (unit u-store (cycles 1))))
)
(dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
(NO-DIS (PIPE O) (IDOC MEM))
--- 2021,2028 ----
(+ OP1_2 op2-op src1 src2)
(set mode (mem mode src2) src1)
((m32r/d (unit u-store (cycles 1)))
! (m32rx (unit u-store (cycles 1)))
! (m32r2 (unit u-store (cycles 1))))
)
(dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
(NO-DIS (PIPE O) (IDOC MEM))
***************
*** 1830,1836 ****
(+ OP1_10 op2-op src1 src2 slo16)
(set mode (mem mode (add src2 slo16)) src1)
((m32r/d (unit u-store (cycles 2)))
! (m32rx (unit u-store (cycles 2))))
)
(dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
(NO-DIS (IDOC MEM))
--- 2034,2041 ----
(+ OP1_10 op2-op src1 src2 slo16)
(set mode (mem mode (add src2 slo16)) src1)
((m32r/d (unit u-store (cycles 2)))
! (m32rx (unit u-store (cycles 2)))
! (m32r2 (unit u-store (cycles 2))))
)
(dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
(NO-DIS (IDOC MEM))
***************
*** 1855,1860 ****
--- 2060,2099 ----
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ (m32r2 (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ )
+ )
+
+ (dni sth-plus "sth+"
+ ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
+ "sth $src1,@$src2+"
+ (+ OP1_2 OP2_3 src1 src2)
+ ; This has to be coded carefully to avoid an "earlyclobber" of src2.
+ (sequence ((HI new-src2))
+ (set (mem HI new-src2) src1)
+ (set new-src2 (add src2 (const 2)))
+ (set src2 new-src2))
+ ((m32rx (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ (m32r2 (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ )
+ )
+
+ (dni stb-plus "stb+"
+ ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
+ "stb $src1,@$src2+"
+ (+ OP1_2 OP2_1 src1 src2)
+ ; This has to be coded carefully to avoid an "earlyclobber" of src2.
+ (sequence ((QI new-src2))
+ (set (mem QI new-src2) src1)
+ (set new-src2 (add src2 (const 1)))
+ (set src2 new-src2))
+ ((m32rx (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ (m32r2 (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
***************
*** 1875,1884 ****
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
! (dnmi push "push" ((IDOC MEM))
"push $src1"
(emit st-minus src1 (src2 15)) ; "st %0,@-sp"
)
--- 2114,2125 ----
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ (m32r2 (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
! (dnmi push "push" ((PIPE O) (IDOC MEM))
"push $src1"
(emit st-minus src1 (src2 15)) ; "st %0,@-sp"
)
***************
*** 1943,1954 ****
(set (mem WI src2) src1))
(set (reg h-lock) (const BI 0)))
((m32r/d (unit u-load))
! (m32rx (unit u-load)))
)
; Saturate into byte.
(dni satb "satb"
! ((MACH m32rx) (IDOC ALU))
"satb $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
(set dr
--- 2184,2196 ----
(set (mem WI src2) src1))
(set (reg h-lock) (const BI 0)))
((m32r/d (unit u-load))
! (m32rx (unit u-load))
! (m32r2 (unit u-load)))
)
; Saturate into byte.
(dni satb "satb"
! ((MACH m32rx,m32r2) (IDOC ALU))
"satb $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
(set dr
***************
*** 1962,1968 ****
; Saturate into half word.
(dni sath "sath"
! ((MACH m32rx) (IDOC ALU))
"sath $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
(set dr
--- 2204,2210 ----
; Saturate into half word.
(dni sath "sath"
! ((MACH m32rx,m32r2) (IDOC ALU))
"sath $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
(set dr
***************
*** 1975,1981 ****
; Saturate word.
(dni sat "sat"
! ((MACH m32rx) SPECIAL (IDOC ALU))
"sat $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 0))
(set dr
--- 2217,2223 ----
; Saturate word.
(dni sat "sat"
! ((MACH m32rx,m32r2) SPECIAL (IDOC ALU))
"sat $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 0))
(set dr
***************
*** 1990,1996 ****
; Parallel compare byte zeros.
; Set C bit in condition register if any byte in source register is zero.
(dni pcmpbz "pcmpbz"
! ((MACH m32rx) (PIPE OS) SPECIAL (IDOC ALU))
"pcmpbz $src2"
(+ OP1_0 (f-r1 3) OP2_7 src2)
(set condbit
--- 2232,2238 ----
; Parallel compare byte zeros.
; Set C bit in condition register if any byte in source register is zero.
(dni pcmpbz "pcmpbz"
! ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU))
"pcmpbz $src2"
(+ OP1_0 (f-r1 3) OP2_7 src2)
(set condbit
***************
*** 2000,2022 ****
((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
(else (const BI 0))))
! ((m32rx (unit u-cmp)))
)
; Add accumulators
(dni sadd "sadd"
! ((MACH m32rx) (PIPE S) (IDOC ACCUM))
"sadd"
(+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
(set (reg h-accums 0)
(add (sra (reg h-accums 1) (const 16))
(reg h-accums 0)))
! ((m32rx (unit u-mac)))
)
; Multiply and add into accumulator 1
(dni macwu1 "macwu1"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"macwu1 $src1,$src2"
(+ OP1_5 src1 OP2_11 src2)
(set (reg h-accums 1)
--- 2242,2266 ----
((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
(else (const BI 0))))
! ((m32rx (unit u-cmp))
! (m32r2 (unit u-cmp)))
)
; Add accumulators
(dni sadd "sadd"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"sadd"
(+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
(set (reg h-accums 0)
(add (sra (reg h-accums 1) (const 16))
(reg h-accums 0)))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
; Multiply and add into accumulator 1
(dni macwu1 "macwu1"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"macwu1 $src1,$src2"
(+ OP1_5 src1 OP2_11 src2)
(set (reg h-accums 1)
***************
*** 2029,2040 ****
(ext DI (and src2 (const #xffff)))))
(const 8))
(const 8)))
! ((m32rx (unit u-mac)))
)
; Multiply and subtract from accumulator 0
(dni msblo "msblo"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"msblo $src1,$src2"
(+ OP1_5 src1 OP2_13 src2)
(set accum
--- 2273,2285 ----
(ext DI (and src2 (const #xffff)))))
(const 8))
(const 8)))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
; Multiply and subtract from accumulator 0
(dni msblo "msblo"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"msblo $src1,$src2"
(+ OP1_5 src1 OP2_13 src2)
(set accum
***************
*** 2050,2061 ****
(const 16)))
(const 8))
(const 8)))
! ((m32rx (unit u-mac)))
)
; Multiply into accumulator 1
(dni mulwu1 "mulwu1"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"mulwu1 $src1,$src2"
(+ OP1_5 src1 OP2_10 src2)
(set (reg h-accums 1)
--- 2295,2307 ----
(const 16)))
(const 8))
(const 8)))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
; Multiply into accumulator 1
(dni mulwu1 "mulwu1"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"mulwu1 $src1,$src2"
(+ OP1_5 src1 OP2_10 src2)
(set (reg h-accums 1)
***************
*** 2066,2077 ****
(ext DI (and src2 (const #xffff))))
(const 16))
(const 16)))
! ((m32rx (unit u-mac)))
)
; Multiply and add into accumulator 1
(dni maclh1 "maclh1"
! ((MACH m32rx) (PIPE S) (IDOC MAC))
"maclh1 $src1,$src2"
(+ OP1_5 src1 OP2_12 src2)
(set (reg h-accums 1)
--- 2312,2324 ----
(ext DI (and src2 (const #xffff))))
(const 16))
(const 16)))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
; Multiply and add into accumulator 1
(dni maclh1 "maclh1"
! ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"maclh1 $src1,$src2"
(+ OP1_5 src1 OP2_12 src2)
(set (reg h-accums 1)
***************
*** 2087,2098 ****
(const 16)))
(const 8))
(const 8)))
! ((m32rx (unit u-mac)))
)
; skip instruction if C
(dni sc "sc"
! ((MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
"sc"
(+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
(skip (zext INT condbit))
--- 2334,2346 ----
(const 16)))
(const 8))
(const 8)))
! ((m32rx (unit u-mac))
! (m32r2 (unit u-mac)))
)
; skip instruction if C
(dni sc "sc"
! ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"sc"
(+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
(skip (zext INT condbit))
***************
*** 2101,2109 ****
; skip instruction if not C
(dni snc "snc"
! ((MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
"snc"
(+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
(skip (zext INT (not condbit)))
()
)
--- 2349,2409 ----
; skip instruction if not C
(dni snc "snc"
! ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"snc"
(+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
(skip (zext INT (not condbit)))
()
)
+
+ ; PSW &= ~((unsigned char) uimm8 | 0x000ff00)
+ (dni clrpsw "clrpsw"
+ ((PIPE O) SPECIAL_M32R)
+ "clrpsw $uimm8"
+ (+ OP1_7 (f-r1 2) uimm8)
+ (set USI (reg h-cr 0)
+ (and USI (reg h-cr 0)
+ (or USI (inv BI uimm8) (const #xff00))))
+ ()
+ )
+
+ ; PSW |= (unsigned char) uimm8
+ (dni setpsw "setpsw"
+ ((PIPE O) SPECIAL_M32R)
+ "setpsw $uimm8"
+ (+ OP1_7 (f-r1 1) uimm8)
+ (set USI (reg h-cr 0) uimm8)
+ ()
+ )
+
+ ; bset
+ (dni bset "bset"
+ (SPECIAL_M32R)
+ "bset $uimm3,@($slo16,$sr)"
+ (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)
+ (set QI (mem QI (add sr slo16))
+ (or QI (mem QI (add sr slo16))
+ (sll USI (const 1) (sub (const 7) uimm3))))
+ ()
+ )
+
+ ; bclr
+ (dni bclr "bclr"
+ (SPECIAL_M32R)
+ "bclr $uimm3,@($slo16,$sr)"
+ (+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16)
+ (set QI (mem QI (add sr slo16))
+ (and QI (mem QI (add sr slo16))
+ (inv QI (sll USI (const 1) (sub (const 7) uimm3)))))
+ ()
+ )
+
+ ; btst
+ (dni btst "btst"
+ (SPECIAL_M32R (PIPE O))
+ "btst $uimm3,$sr"
+ (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)
+ (set condbit (and QI (srl USI sr (sub (const 7) uimm3)) (const 1)))
+ ()
+ )
+
Index: cgen/cpu/m32r.opc
===================================================================
RCS file: /cvs/src/src/cgen/cpu/m32r.opc,v
retrieving revision 1.3
diff -c -r1.3 m32r.opc
*** cgen/cpu/m32r.opc 20 Nov 2001 05:16:06 -0000 1.3
--- cgen/cpu/m32r.opc 2 Dec 2003 08:56:10 -0000
***************
*** 23,28 ****
--- 23,29 ----
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 256
#undef CGEN_DIS_HASH
+ #if 0
#define X(b) (((unsigned char *) (b))[0] & 0xf0)
#define CGEN_DIS_HASH(buffer, value) \
(X (buffer) | \
***************
*** 30,38 ****
--- 31,69 ----
: X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
: X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
+ #else
+ #define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)
+ extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);
+ #endif
/* -- */
\f
+ /* -- opc.c */
+ unsigned int
+ m32r_cgen_dis_hash (buf, value)
+ const char * buf ATTRIBUTE_UNUSED;
+ CGEN_INSN_INT value;
+ {
+ unsigned int x;
+
+ if (value & 0xffff0000) /* 32bit instructions */
+ value = (value >> 16) & 0xffff;
+
+ x = (value>>8) & 0xf0;
+ if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
+ return x;
+
+ if (x == 0x70 || x == 0xf0)
+ return x | ((value>>8) & 0x0f);
+
+ if (x == 0x30)
+ return x | ((value & 0x70) >> 4);
+ else
+ return x | ((value & 0xf0) >> 4);
+ }
+
+ /* -- */
+ \f
/* -- asm.c */
static const char * parse_hash
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
***************
*** 133,139 ****
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
! value &= 0xffff;
*valuep = value;
return errmsg;
}
--- 164,174 ----
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
! {
! value &= 0xffff;
! if (value & 0x8000)
! value |= 0xffff0000;
! }
*valuep = value;
return errmsg;
}
***************
*** 233,238 ****
--- 268,275 ----
char *buf = buffer;
int status;
int buflen = (pc & 3) == 0 ? 4 : 2;
+ int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+ char *x;
/* Read the base part of the insn. */
***************
*** 244,265 ****
}
/* 32 bit insn? */
! if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
return print_insn (cd, pc, info, buf, buflen);
/* Print the first insn. */
if ((pc & 3) == 0)
{
if (print_insn (cd, pc, info, buf, 2) == 0)
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
- buf += 2;
}
! if (buf[0] & 0x80)
{
/* Parallel. */
(*info->fprintf_func) (info->stream, " || ");
! buf[0] &= 0x7f;
}
else
(*info->fprintf_func) (info->stream, " -> ");
--- 281,305 ----
}
/* 32 bit insn? */
! x = (big_p ? &buf[0] : &buf[3]);
! if ((pc & 3) == 0 && (*x & 0x80) != 0)
return print_insn (cd, pc, info, buf, buflen);
/* Print the first insn. */
+ buf += (big_p ? 0 : 2);
if ((pc & 3) == 0)
{
if (print_insn (cd, pc, info, buf, 2) == 0)
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
}
+ buf += (big_p ? 2 : -2);
! x = (big_p ? &buf[0] : &buf[1]);
! if (*x & 0x80)
{
/* Parallel. */
(*info->fprintf_func) (info->stream, " || ");
! *x &= 0x7f;
}
else
(*info->fprintf_func) (info->stream, " -> ");
[-- Attachment #9: gas.m32r2.patch --]
[-- Type: application/octet-stream, Size: 21391 bytes --]
gas/ChangeLog
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* config/tc-m32r.c : Add new machine m32r2.
Add new instructions.
(line_separator_chars) : Use '!'.
* config/tc-m32r.h : Add new machine m32r2.
Index: gas/config/tc-m32r.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-m32r.c,v
retrieving revision 1.31
diff -c -r1.31 tc-m32r.c
*** gas/config/tc-m32r.c 22 Nov 2003 02:35:30 -0000 1.31
--- gas/config/tc-m32r.c 2 Dec 2003 08:56:11 -0000
***************
*** 27,32 ****
--- 27,33 ----
#include "opcodes/m32r-desc.h"
#include "opcodes/m32r-opc.h"
#include "cgen.h"
+ #include "elf/m32r.h"
/* Linked list of symbols that are debugging symbols to be defined as the
beginning of the current instruction. */
***************
*** 93,113 ****
shouldn't assume or require it to). */
static int warn_unmatched_high = 0;
! /* Non-zero if -m32rx has been specified, in which case support for the
! extended M32RX instruction set should be enabled. */
! static int enable_m32rx = 0;
/* Non-zero if -m32rx -hidden has been specified, in which case support for
the special M32RX instruction set should be enabled. */
static int enable_special = 0;
/* Non-zero if the programmer should be warned when an explicit parallel
instruction might have constraint violations. */
static int warn_explicit_parallel_conflicts = 1;
/* Non-zero if insns can be made parallel. */
static int optimize;
/* Stuff for .scomm symbols. */
static segT sbss_section;
static asection scom_section;
--- 94,136 ----
shouldn't assume or require it to). */
static int warn_unmatched_high = 0;
! /* 1 if -m32rx has been specified, in which case support for the
! extended M32RX instruction set should be enabled.
! 2 if -m32r2 has been specified, in which case support for the
! extended M32R2 instruction set should be enabled.
! */
! static int enable_m32rx = 0; /* default M32R */
/* Non-zero if -m32rx -hidden has been specified, in which case support for
the special M32RX instruction set should be enabled. */
static int enable_special = 0;
+ /* Non-zero if -bitinst has been specified, in which case support for
+ extended M32R bit-field instruction set should be enabled. */
+ static int enable_special_m32r = 0;
+
+ /* Non-zero if -float has been specified, in which case support for
+ extended M32R floating point instruction set should be enabled. */
+ static int enable_special_float = 0;
+
/* Non-zero if the programmer should be warned when an explicit parallel
instruction might have constraint violations. */
static int warn_explicit_parallel_conflicts = 1;
+ /* Non-zero if the programmer should be errored when an explicit parallel
+ instruction might have constraint violations. */
+ static int error_explicit_parallel_conflicts = 1;
+
+ /* Non-zero if insns can be made parallel. */
+ static int use_parallel = -1;
+
/* Non-zero if insns can be made parallel. */
static int optimize;
+ /* m32r er_flags */
+ static int m32r_flags = 0;
+
+
/* Stuff for .scomm symbols. */
static segT sbss_section;
static asection scom_section;
***************
*** 115,121 ****
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
! const char line_separator_chars[] = "";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
--- 138,144 ----
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
! const char line_separator_chars[] = "!";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
***************
*** 146,163 ****
static struct m32r_hi_fixup *m32r_hi_fixup_list;
\f
! static void allow_m32rx PARAMS ((int));
static void
! allow_m32rx (on)
! int on;
{
enable_m32rx = on;
if (stdoutput != NULL)
! bfd_set_arch_mach (stdoutput, TARGET_ARCH,
! enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
}
\f
#define M32R_SHORTOPTS "O"
--- 169,197 ----
static struct m32r_hi_fixup *m32r_hi_fixup_list;
\f
! struct {
! enum bfd_architecture bfd_mach;
! int mach_flags;
! } mach_table[] =
! {
! { bfd_mach_m32r, (1<<MACH_M32R) },
! { bfd_mach_m32rx, (1<<MACH_M32RX) },
! { bfd_mach_m32r2, (1<<MACH_M32R2) }
! };
!
! static void allow_m32rx (int);
static void
! allow_m32rx (int on)
{
enable_m32rx = on;
if (stdoutput != NULL)
! bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach);
! if (gas_cgen_cpu_desc != NULL)
! gas_cgen_cpu_desc->machs = mach_table[on].mach_flags;
}
+
\f
#define M32R_SHORTOPTS "O"
***************
*** 167,184 ****
{
#define OPTION_M32R (OPTION_MD_BASE)
#define OPTION_M32RX (OPTION_M32R + 1)
! #define OPTION_WARN_PARALLEL (OPTION_M32RX + 1)
#define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
! #define OPTION_SPECIAL (OPTION_NO_WARN_PARALLEL + 1)
! #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL + 1)
#define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)
{"m32r", no_argument, NULL, OPTION_M32R},
{"m32rx", no_argument, NULL, OPTION_M32RX},
{"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
{"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
{"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
{"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
{"hidden", no_argument, NULL, OPTION_SPECIAL},
/* Sigh. I guess all warnings must now have both variants. */
{"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
{"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
--- 201,240 ----
{
#define OPTION_M32R (OPTION_MD_BASE)
#define OPTION_M32RX (OPTION_M32R + 1)
! #define OPTION_M32R2 (OPTION_M32RX + 1)
! #define OPTION_BIG (OPTION_M32R2 + 1)
! #define OPTION_LITTLE (OPTION_BIG + 1)
! #define OPTION_PARALLEL (OPTION_LITTLE + 1)
! #define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1)
! #define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1)
#define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
! #define OPTION_ERROR_PARALLEL (OPTION_NO_WARN_PARALLEL + 1)
! #define OPTION_NO_ERROR_PARALLEL (OPTION_ERROR_PARALLEL + 1)
! #define OPTION_SPECIAL (OPTION_NO_ERROR_PARALLEL + 1)
! #define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1)
! #define OPTION_SPECIAL_FLOAT (OPTION_SPECIAL_M32R + 1)
! #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1)
#define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)
{"m32r", no_argument, NULL, OPTION_M32R},
{"m32rx", no_argument, NULL, OPTION_M32RX},
+ {"m32r2", no_argument, NULL, OPTION_M32R2},
+ {"big", no_argument, NULL, OPTION_BIG},
+ {"little", no_argument, NULL, OPTION_LITTLE},
+ {"EB", no_argument, NULL, OPTION_BIG},
+ {"EL", no_argument, NULL, OPTION_LITTLE},
+ {"parallel", no_argument, NULL, OPTION_PARALLEL},
+ {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL},
{"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
{"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
{"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
{"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
+ {"error-explicit-parallel-conflicts", no_argument, NULL, OPTION_ERROR_PARALLEL},
+ {"Ep", no_argument, NULL, OPTION_ERROR_PARALLEL},
+ {"no-error-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_ERROR_PARALLEL},
+ {"Enp", no_argument, NULL, OPTION_NO_ERROR_PARALLEL},
{"hidden", no_argument, NULL, OPTION_SPECIAL},
+ {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},
+ {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},
/* Sigh. I guess all warnings must now have both variants. */
{"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
{"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
***************
*** 197,202 ****
--- 253,279 ----
size_t md_longopts_size = sizeof (md_longopts);
+ static void little (int);
+ static void
+ little (int on)
+ {
+ target_big_endian = !on;
+ }
+
+ /* Use parallel execution */
+ static int parallel (void);
+ static int
+ parallel (void)
+ {
+ if (!enable_m32rx)
+ return 0;
+
+ if (use_parallel == 1)
+ return 1;
+
+ return 0;
+ }
+
int
md_parse_option (c, arg)
int c;
***************
*** 216,221 ****
--- 293,320 ----
allow_m32rx (1);
break;
+ case OPTION_M32R2:
+ allow_m32rx (2);
+ enable_special = 1;
+ enable_special_m32r = 1;
+ break;
+
+ case OPTION_BIG:
+ target_big_endian = 1;
+ break;
+
+ case OPTION_LITTLE:
+ target_big_endian = 0;
+ break;
+
+ case OPTION_PARALLEL:
+ use_parallel = 1;
+ break;
+
+ case OPTION_NO_PARALLEL:
+ use_parallel = 0;
+ break;
+
case OPTION_WARN_PARALLEL:
warn_explicit_parallel_conflicts = 1;
break;
***************
*** 224,229 ****
--- 323,336 ----
warn_explicit_parallel_conflicts = 0;
break;
+ case OPTION_ERROR_PARALLEL:
+ error_explicit_parallel_conflicts = 1;
+ break;
+
+ case OPTION_NO_ERROR_PARALLEL:
+ error_explicit_parallel_conflicts = 0;
+ break;
+
case OPTION_SPECIAL:
if (enable_m32rx)
enable_special = 1;
***************
*** 235,240 ****
--- 342,355 ----
}
break;
+ case OPTION_SPECIAL_M32R:
+ enable_special_m32r = 1;
+ break;
+
+ case OPTION_SPECIAL_FLOAT:
+ enable_special_float = 1;
+ break;
+
case OPTION_WARN_UNMATCHED:
warn_unmatched_high = 1;
break;
***************
*** 271,276 ****
--- 386,395 ----
fprintf (stream, _("\
-m32rx support the extended m32rx instruction set\n"));
fprintf (stream, _("\
+ -m32r2 support the extended m32r2 instruction set\n"));
+ fprintf (stream, _("\
+ -EL,-little use little endian\n"));
+ fprintf (stream, _("\
-O try to combine instructions in parallel\n"));
fprintf (stream, _("\
***************
*** 285,290 ****
--- 404,421 ----
-Wp synonym for -warn-explicit-parallel-conflicts\n"));
fprintf (stream, _("\
-Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
+ fprintf (stream, _("\
+ -error-explicit-parallel-conflicts error when parallel instructions\n"));
+ fprintf (stream, _("\
+ violate contraints\n"));
+ fprintf (stream, _("\
+ -no-error-explicit-parallel-conflicts do not error when parallel\n"));
+ fprintf (stream, _("\
+ instructions violate contraints\n"));
+ fprintf (stream, _("\
+ -Ep synonym for -error-explicit-parallel-conflicts\n"));
+ fprintf (stream, _("\
+ -Enp synonym for -no-error-explicit-parallel-conflicts\n"));
fprintf (stream, _("\
-warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
***************
*** 295,300 ****
--- 426,432 ----
fprintf (stream, _("\
-Wnuh synonym for -no-warn-unmatched-high\n"));
+
#if 0
fprintf (stream, _("\
-relax create linker relaxable code\n"));
***************
*** 322,327 ****
--- 454,461 ----
/* Not documented as so far there is no need for them.... */
{ "m32r", allow_m32rx, 0 },
{ "m32rx", allow_m32rx, 1 },
+ { "m32r2", allow_m32rx, 2 },
+ { "little", little, 1 },
{ NULL, NULL, 0 }
};
***************
*** 459,464 ****
--- 593,608 ----
input_line_pointer = save_input_line;
}
+ void
+ m32r_flush_pending_output()
+ {
+ if (debug_sym_link)
+ {
+ expand_debug_syms (debug_sym_link, 1);
+ debug_sym_link = (sym_linkS *) 0;
+ }
+ }
+
/* Cover function to fill_insn called after a label and at end of assembly.
The result is always 1: we're called in a conditional to see if the
current line is a label. */
***************
*** 488,493 ****
--- 632,656 ----
return 1;
}
\f
+
+ /* The default target format to use. */
+
+ const char *
+ m32r_target_format ()
+ {
+ #ifdef TE_LINUX
+ if (target_big_endian)
+ return "elf32-m32r-linux";
+ else
+ return "elf32-m32rle-linux";
+ #else
+ if (target_big_endian)
+ return "elf32-m32r";
+ else
+ return "elf32-m32rle";
+ #endif
+ }
+
void
md_begin ()
{
***************
*** 500,506 ****
/* Set the machine number and endian. */
gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
CGEN_CPU_OPEN_ENDIAN,
! CGEN_ENDIAN_BIG,
CGEN_CPU_OPEN_END);
m32r_cgen_init_asm (gas_cgen_cpu_desc);
--- 663,670 ----
/* Set the machine number and endian. */
gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
CGEN_CPU_OPEN_ENDIAN,
! (target_big_endian ?
! CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE),
CGEN_CPU_OPEN_END);
m32r_cgen_init_asm (gas_cgen_cpu_desc);
***************
*** 711,717 ****
go away if the instructions are swapped, and we want to make
sure that any other errors are detected before this happens. */
if (a_pipe == PIPE_S
! || b_pipe == PIPE_O)
return _("Instructions share the same execution pipeline");
return NULL;
--- 875,882 ----
go away if the instructions are swapped, and we want to make
sure that any other errors are detected before this happens. */
if (a_pipe == PIPE_S
! || b_pipe == PIPE_O
! || (b_pipe == PIPE_O_OS && (enable_m32rx != 2)))
return _("Instructions share the same execution pipeline");
return NULL;
***************
*** 791,798 ****
--- 956,981 ----
as_bad (_("not a 16 bit instruction '%s'"), str);
return;
}
+ #ifdef E_M32R2_ARCH
+ else if ((enable_m32rx == 1)
+ /* FIXME: Need standard macro to perform this test. */
+ && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32R2))
+ && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32RX)))))
+ {
+ /* xgettext:c-format */
+ as_bad (_("instruction '%s' is for the M32R2 only"), str);
+ return;
+ }
+ else if ((! enable_special
+ && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
+ || (! enable_special_m32r
+ && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)))
+ #else
else if (! enable_special
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
+ #endif
{
/* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
***************
*** 887,894 ****
--- 1070,1095 ----
as_bad (_("not a 16 bit instruction '%s'"), str);
return;
}
+ #ifdef E_M32R2_ARCH
+ else if ((enable_m32rx == 1)
+ /* FIXME: Need standard macro to perform this test. */
+ && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32R2))
+ && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32RX)))))
+ {
+ /* xgettext:c-format */
+ as_bad (_("instruction '%s' is for the M32R2 only"), str);
+ return;
+ }
+ else if ((! enable_special
+ && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
+ || (! enable_special_m32r
+ && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)))
+ #else
else if (! enable_special
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
+ #endif
{
/* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
***************
*** 1001,1006 ****
--- 1202,1217 ----
return;
}
+ if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)
+ || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
+ m32r_flags |= E_M32R_HAS_HIDDEN_INST;
+ if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)
+ || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))
+ m32r_flags |= E_M32R_HAS_BIT_INST;
+ if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT)
+ || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT))
+ m32r_flags |= E_M32R_HAS_FLOAT_INST;
+
/* Set these so m32r_fill_insn can use them. */
prev_seg = now_seg;
prev_subseg = now_subseg;
***************
*** 1021,1026 ****
--- 1232,1238 ----
if ((str2 = strstr (str, "||")) != NULL)
{
assemble_two_insns (str, str2, 1);
+ m32r_flags |= E_M32R_HAS_PARALLEL;
return;
}
***************
*** 1043,1050 ****
--- 1255,1280 ----
return;
}
+ #ifdef E_M32R2_ARCH
+ if ((enable_m32rx == 1)
+ /* FIXME: Need standard macro to perform this test. */
+ && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32R2))
+ && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32RX)))))
+ {
+ /* xgettext:c-format */
+ as_bad (_("instruction '%s' is for the M32R2 only"), str);
+ return;
+ }
+ else if ((! enable_special
+ && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
+ || (! enable_special_m32r
+ && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)))
+ #else
if (! enable_special
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
+ #endif
{
/* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
***************
*** 1058,1063 ****
--- 1288,1300 ----
return;
}
+ if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
+ m32r_flags |= E_M32R_HAS_HIDDEN_INST;
+ if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))
+ m32r_flags |= E_M32R_HAS_BIT_INST;
+ if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT))
+ m32r_flags |= E_M32R_HAS_FLOAT_INST;
+
if (CGEN_INSN_BITSIZE (insn.insn) == 32)
{
/* 32 bit insns must live on 32 bit boundaries. */
***************
*** 1948,1951 ****
--- 2185,2196 ----
return 0;
return 1;
+ }
+
+ void
+ m32r_elf_final_processing ()
+ {
+ if (use_parallel)
+ m32r_flags |= E_M32R_HAS_PARALLEL;
+ elf_elfheader (stdoutput)->e_flags |= m32r_flags;
}
Index: gas/config/tc-m32r.h
===================================================================
RCS file: /cvs/src/src/gas/config/tc-m32r.h,v
retrieving revision 1.9
diff -c -r1.9 tc-m32r.h
*** gas/config/tc-m32r.h 25 Jul 2003 14:35:54 -0000 1.9
--- gas/config/tc-m32r.h 2 Dec 2003 08:56:11 -0000
***************
*** 26,39 ****
#error M32R support requires BFD_ASSEMBLER
#endif
! #define LISTING_HEADER "M32R GAS "
/* The target BFD architecture. */
#define TARGET_ARCH bfd_arch_m32r
! #define TARGET_FORMAT "elf32-m32r"
#define TARGET_BYTES_BIG_ENDIAN 1
/* call md_pcrel_from_section, not md_pcrel_from */
long md_pcrel_from_section PARAMS ((struct fix *, segT));
--- 26,47 ----
#error M32R support requires BFD_ASSEMBLER
#endif
! #define LISTING_HEADER \
! (target_big_endian \
! ? "M32R GAS" : "M32R GAS Little Endian")
/* The target BFD architecture. */
#define TARGET_ARCH bfd_arch_m32r
! /* The endianness of the target format may change based on command
! line arguments. */
! #define TARGET_FORMAT m32r_target_format()
! extern const char *m32r_target_format PARAMS ((void));
+ /* Default to big endian. */
+ #ifndef TARGET_BYTES_BIG_ENDIAN
#define TARGET_BYTES_BIG_ENDIAN 1
+ #endif
/* call md_pcrel_from_section, not md_pcrel_from */
long md_pcrel_from_section PARAMS ((struct fix *, segT));
***************
*** 101,103 ****
--- 109,118 ----
#define md_cleanup m32r_elf_section_change_hook
#define md_elf_section_change_hook m32r_elf_section_change_hook
extern void m32r_elf_section_change_hook PARAMS ((void));
+
+ #define md_flush_pending_output() m32r_flush_pending_output ()
+ extern void m32r_flush_pending_output PARAMS ((void));
+
+ #define elf_tc_final_processing m32r_elf_final_processing
+ extern void m32r_elf_final_processing PARAMS ((void));
+
[-- Attachment #10: include.m32r2.patch --]
[-- Type: application/octet-stream, Size: 1367 bytes --]
include/ChangeLog
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* elf/m32r.h : Add new machine type m32r2 and instruction modes.
Index: include/elf/m32r.h
===================================================================
RCS file: /cvs/src/src/include/elf/m32r.h,v
retrieving revision 1.5
diff -c -r1.5 m32r.h
*** include/elf/m32r.h 14 Mar 2001 02:27:44 -0000 1.5
--- include/elf/m32r.h 2 Dec 2003 08:56:12 -0000
***************
*** 63,67 ****
--- 63,87 ----
#define E_M32R_ARCH 0x00000000
/* m32rx code. */
#define E_M32RX_ARCH 0x10000000
+ #define E_M32RX_ARCH 0x10000000
+ /* m32r2 code. */
+ #define E_M32R2_ARCH 0x20000000
+
+ /* 12 bit m32r new instructions field. */
+ #define EF_M32R_INST 0x0FFF0000
+ /* parallel instructions */
+ #define E_M32R_HAS_PARALLEL 0x00010000
+ /* hidden instructions for m32rx:
+ jc, jnc, macwhi-a, macwlo-a, mulwhi-a, mulwlo-a, sth+, shb+, sat, pcmpbz,
+ sc, snc */
+ #define E_M32R_HAS_HIDDEN_INST 0x00020000
+ /* new bit instructions:
+ clrpsw, setpsw, bset, bclr, btst */
+ #define E_M32R_HAS_BIT_INST 0x00040000
+ /* floating point instructions */
+ #define E_M32R_HAS_FLOAT_INST 0x00080000
+
+ /* 4 bit m32r ignore to check field. */
+ #define EF_M32R_IGNORE 0x0000000F
#endif
[-- Attachment #11: sim.m32r2.patch --]
[-- Type: application/octet-stream, Size: 14895 bytes --]
ChangeLog/sim/m32r
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* Makefile.in : Add new machine m32r2.
* m32r2.c : New file for m32r2.
* mloop2.in : Ditto
* model2.c : Ditto
* sem2-switch.c : Ditto
* m32r-sim.h : Add EVB register.
* sim-if.h : Ditto
* sim-main.h : Ditto
* traps.c : Ditto
Index: sim/m32r/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/m32r/Makefile.in,v
retrieving revision 1.6
diff -c -r1.6 Makefile.in
*** sim/m32r/Makefile.in 8 Sep 2003 17:26:20 -0000 1.6
--- sim/m32r/Makefile.in 2 Dec 2003 08:56:19 -0000
***************
*** 22,27 ****
--- 22,28 ----
M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
+ M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
CONFIG_DEVICES = dv-sockser.o
CONFIG_DEVICES =
***************
*** 38,43 ****
--- 39,45 ----
sim-if.o arch.o \
$(M32R_OBJS) \
$(M32RX_OBJS) \
+ $(M32R2_OBJS) \
traps.o devices.o \
$(CONFIG_DEVICES)
***************
*** 113,122 ****
semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
m32r-clean:
rm -f mloop.c eng.h stamp-mloop
rm -f mloopx.c engx.h stamp-xmloop
! rm -f stamp-arch stamp-cpu stamp-xcpu
rm -f tmp-*
# cgen support, enable with --enable-cgen-maint
--- 115,149 ----
semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
+ # M32R2 objs
+
+ M32R2F_INCLUDE_DEPS = \
+ $(CGEN_MAIN_CPU_DEPS) \
+ cpu2.h decode2.h eng2.h
+
+ m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)
+
+ # FIXME: Use of `mono' is wip.
+ mloop2.c eng2.h: stamp-2mloop
+ stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
+ $(SHELL) $(srccom)/genmloop.sh \
+ -mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
+ -cpu m32r2f -infile $(srcdir)/mloop2.in
+ $(SHELL) $(srcroot)/move-if-change eng.hin eng2.h
+ $(SHELL) $(srcroot)/move-if-change mloop.cin mloop2.c
+ touch stamp-2mloop
+ mloop2.o: mloop2.c sem2-switch.c $(M32R2F_INCLUDE_DEPS)
+
+ cpu2.o: cpu2.c $(M32R2F_INCLUDE_DEPS)
+ decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
+ sem2.o: sem2.c $(M32R2F_INCLUDE_DEPS)
+ model2.o: model2.c $(M32R2F_INCLUDE_DEPS)
+
m32r-clean:
rm -f mloop.c eng.h stamp-mloop
rm -f mloopx.c engx.h stamp-xmloop
! rm -f mloop2.c eng2.h stamp-2mloop
! rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
rm -f tmp-*
# cgen support, enable with --enable-cgen-maint
***************
*** 148,150 ****
--- 175,187 ----
EXTRAFILES="$(CGEN_CPU_SEMSW)"
touch stamp-xcpu
cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
+
+ stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
+ $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
+ cpu=m32r2f mach=m32r2 SUFFIX=2 \
+ archfile=$(CGEN_CPU_DIR)/m32r.cpu \
+ FLAGS="with-scache with-profile=fn" \
+ EXTRAFILES="$(CGEN_CPU_SEMSW)"
+ touch stamp-2cpu
+ cpu2.h sem2-switch.c model2.c decode2.c decode2.h: $(CGEN_MAINT) stamp-2cpu
+
Index: sim/m32r/m32r-sim.h
===================================================================
RCS file: /cvs/src/src/sim/m32r/m32r-sim.h,v
retrieving revision 1.1.1.3
diff -c -r1.1.1.3 m32r-sim.h
*** sim/m32r/m32r-sim.h 12 Oct 1999 04:37:53 -0000 1.1.1.3
--- sim/m32r/m32r-sim.h 2 Dec 2003 08:56:20 -0000
***************
*** 34,39 ****
--- 34,40 ----
#define ACC1H_REGNUM 25
#define BBPSW_REGNUM 26
#define BBPC_REGNUM 27
+ #define EVB_REGNUM 28
extern int m32r_decode_gdb_ctrl_regnum (int);
Index: sim/m32r/m32r.c
===================================================================
RCS file: /cvs/src/src/sim/m32r/m32r.c,v
retrieving revision 1.1.1.2
diff -c -r1.1.1.2 m32r.c
*** sim/m32r/m32r.c 26 Apr 1999 18:32:56 -0000 1.1.1.2
--- sim/m32r/m32r.c 2 Dec 2003 08:56:20 -0000
***************
*** 39,44 ****
--- 39,45 ----
case BPC_REGNUM : return H_CR_BPC;
case BBPSW_REGNUM : return H_CR_BBPSW;
case BBPC_REGNUM : return H_CR_BBPC;
+ case EVB_REGNUM : return H_CR_CR5;
}
abort ();
}
***************
*** 62,87 ****
case BPC_REGNUM :
case BBPSW_REGNUM :
case BBPC_REGNUM :
SETTWI (buf, a_m32r_h_cr_get (current_cpu,
m32r_decode_gdb_ctrl_regnum (rn)));
break;
case PC_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, m32rbf_h_pc_get (current_cpu));
! else
SETTWI (buf, m32rxf_h_pc_get (current_cpu));
break;
case ACCL_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
! else
SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
break;
case ACCH_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
! else
SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
break;
default :
return 0;
--- 63,95 ----
case BPC_REGNUM :
case BBPSW_REGNUM :
case BBPC_REGNUM :
+ case EVB_REGNUM :
SETTWI (buf, a_m32r_h_cr_get (current_cpu,
m32r_decode_gdb_ctrl_regnum (rn)));
break;
case PC_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, m32rbf_h_pc_get (current_cpu));
! else if (mach == MACH_M32RX)
SETTWI (buf, m32rxf_h_pc_get (current_cpu));
+ else
+ SETTWI (buf, m32r2f_h_pc_get (current_cpu));
break;
case ACCL_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
! else if (mach == MACH_M32RX)
SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
+ else
+ SETTWI (buf, GETLODI (m32r2f_h_accum_get (current_cpu)));
break;
case ACCH_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
! else if (mach == MACH_M32RX)
SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
+ else
+ SETTWI (buf, GETHIDI (m32r2f_h_accum_get (current_cpu)));
break;
default :
return 0;
***************
*** 109,114 ****
--- 117,123 ----
case BPC_REGNUM :
case BBPSW_REGNUM :
case BBPC_REGNUM :
+ case EVB_REGNUM :
a_m32r_h_cr_set (current_cpu,
m32r_decode_gdb_ctrl_regnum (rn),
GETTWI (buf));
***************
*** 116,136 ****
case PC_REGNUM :
if (mach == MACH_M32R)
m32rbf_h_pc_set (current_cpu, GETTWI (buf));
! else
m32rxf_h_pc_set (current_cpu, GETTWI (buf));
break;
case ACCL_REGNUM :
{
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
! else
val = m32rxf_h_accum_get (current_cpu);
SETLODI (val, GETTWI (buf));
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
! else
m32rxf_h_accum_set (current_cpu, val);
break;
}
case ACCH_REGNUM :
--- 125,151 ----
case PC_REGNUM :
if (mach == MACH_M32R)
m32rbf_h_pc_set (current_cpu, GETTWI (buf));
! else if (mach == MACH_M32RX)
m32rxf_h_pc_set (current_cpu, GETTWI (buf));
+ else
+ m32r2f_h_pc_set (current_cpu, GETTWI (buf));
break;
case ACCL_REGNUM :
{
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
! else if (mach == MACH_M32RX)
val = m32rxf_h_accum_get (current_cpu);
+ else
+ val = m32r2f_h_accum_get (current_cpu);
SETLODI (val, GETTWI (buf));
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
! else if (mach == MACH_M32RX)
m32rxf_h_accum_set (current_cpu, val);
+ else
+ m32r2f_h_accum_set (current_cpu, val);
break;
}
case ACCH_REGNUM :
***************
*** 138,150 ****
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
! else
val = m32rxf_h_accum_get (current_cpu);
SETHIDI (val, GETTWI (buf));
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
! else
m32rxf_h_accum_set (current_cpu, val);
break;
}
default :
--- 153,169 ----
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
! else if (mach == MACH_M32RX)
val = m32rxf_h_accum_get (current_cpu);
+ else
+ val = m32r2f_h_accum_get (current_cpu);
SETHIDI (val, GETTWI (buf));
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
! else if (mach == MACH_M32RX)
m32rxf_h_accum_set (current_cpu, val);
+ else
+ m32r2f_h_accum_set (current_cpu, val);
break;
}
default :
***************
*** 169,174 ****
--- 188,197 ----
case MACH_M32RX :
return m32rxf_h_gr_get (current_cpu, regno);
#endif
+ #ifdef HAVE_CPU_M32R2F
+ case MACH_M32R2 :
+ return m32r2f_h_gr_get (current_cpu, regno);
+ #endif
default :
abort ();
}
***************
*** 189,194 ****
--- 212,222 ----
m32rxf_h_gr_set (current_cpu, regno, newval);
break;
#endif
+ #ifdef HAVE_CPU_M32RXF
+ case MACH_M32R2 :
+ m32r2f_h_gr_set (current_cpu, regno, newval);
+ break;
+ #endif
default :
abort ();
}
***************
*** 207,212 ****
--- 235,244 ----
case MACH_M32RX :
return m32rxf_h_cr_get (current_cpu, regno);
#endif
+ #ifdef HAVE_CPU_M32R2F
+ case MACH_M32R2 :
+ return m32r2f_h_cr_get (current_cpu, regno);
+ #endif
default :
abort ();
}
***************
*** 225,230 ****
--- 257,267 ----
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
m32rxf_h_cr_set (current_cpu, regno, newval);
+ break;
+ #endif
+ #ifdef HAVE_CPU_M32RXF
+ case MACH_M32R2 :
+ m32r2f_h_cr_set (current_cpu, regno, newval);
break;
#endif
default :
Index: sim/m32r/sim-if.c
===================================================================
RCS file: /cvs/src/src/sim/m32r/sim-if.c,v
retrieving revision 1.2
diff -c -r1.2 sim-if.c
*** sim/m32r/sim-if.c 27 Feb 2003 23:26:34 -0000 1.2
--- sim/m32r/sim-if.c 2 Dec 2003 08:56:23 -0000
***************
*** 240,245 ****
--- 240,250 ----
PROFILE_LABEL_WIDTH, "Parallel insns:",
sim_add_commas (buf, sizeof (buf),
CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
+ sim_io_printf (sd, " %-*s %s\n\n",
+ PROFILE_LABEL_WIDTH, "Parallel insns:",
+ sim_add_commas (buf, sizeof (buf),
+ CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
}
}
Index: sim/m32r/sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/m32r/sim-main.h,v
retrieving revision 1.1.1.2
diff -c -r1.1.1.2 sim-main.h
*** sim/m32r/sim-main.h 12 Oct 1999 04:37:53 -0000 1.1.1.2
--- sim/m32r/sim-main.h 2 Dec 2003 08:56:23 -0000
***************
*** 60,65 ****
--- 60,67 ----
M32RBF_CPU_DATA cpu_data;
#elif defined (WANT_CPU_M32RXF)
M32RXF_CPU_DATA cpu_data;
+ #elif defined (WANT_CPU_M32R2F)
+ M32R2F_CPU_DATA cpu_data;
#endif
};
\f
Index: sim/m32r/traps.c
===================================================================
RCS file: /cvs/src/src/sim/m32r/traps.c,v
retrieving revision 1.1.1.3
diff -c -r1.1.1.3 traps.c
*** sim/m32r/traps.c 5 Oct 1999 23:13:56 -0000 1.1.1.3
--- sim/m32r/traps.c 2 Dec 2003 08:56:23 -0000
***************
*** 21,26 ****
--- 21,27 ----
#include "sim-main.h"
#include "targ-vals.h"
+ #define TRAP_FLUSH_CACHE 12
/* The semantic code invokes this for invalid (unrecognized) instructions.
CIA is the address with the invalid insn.
VPC is the virtual pc of the following insn. */
***************
*** 68,79 ****
/* sm not changed */
m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
}
! else
{
m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
/* sm not changed */
m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
}
a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
--- 69,86 ----
/* sm not changed */
m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
}
! else if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32RX)
{
m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
/* sm not changed */
m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
}
+ else
+ {
+ m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
+ /* sm not changed */
+ m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
+ }
a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
***************
*** 131,138 ****
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
{
/* The new pc is the trap vector entry.
! We assume there's a branch there to some handler. */
! USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
return new_pc;
}
--- 138,147 ----
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
{
/* The new pc is the trap vector entry.
! We assume there's a branch there to some handler.
! Use cr5 as EVB (EIT Vector Base) register. */
! /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
! USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
return new_pc;
}
***************
*** 169,177 ****
sim_stopped, SIM_SIGTRAP);
break;
default :
{
! USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
return new_pc;
}
}
--- 178,192 ----
sim_stopped, SIM_SIGTRAP);
break;
+ case TRAP_FLUSH_CACHE:
+ /* Do nothing. */
+ break;
+
default :
{
! /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
! /* Use cr5 as EVB (EIT Vector Base) register. */
! USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
return new_pc;
}
}
[-- Attachment #12: m32r2.s --]
[-- Type: application/octet-stream, Size: 1745 bytes --]
# Test new instructions
.text
.global setpsw
setpsw:
setpsw 0xc1
setpsw 0xff
.text
.global clrpsw
clrpsw:
clrpsw 0xc1
clrpsw 0xff
.text
.global bset
bset:
bset #0,@(4,r1)
bset #1,@(4,r1)
bset #7,@(4,r1)
.text
.global bclr
bclr:
bclr #0,@(4,r1)
bclr #1,@(4,r1)
bclr #7,@(4,r1)
.text
.global btst
btst:
btst #0,fp
btst #1,fp
btst #7,fp
btst #1,fp || mv r0,r2
mv r0,r2 || btst #1,fp
.text
.global divuh
divuh:
divuh fp,fp
.text
.global divb
divb:
divb fp,fp
.text
.global divub
divub:
divub fp,fp
.text
.global remh
remh:
remh fp,fp
.text
.global remuh
remuh:
remuh fp,fp
.text
.global remb
remb:
remb fp,fp
.text
.global remub
remub:
remub fp,fp
.text
.global sll
sll:
sll r0,r1 || sll r2,r3
mul r0,r1 || sll r2,r3
sll r0,r1 || mul r2,r3
ldi r0,#1 || sll r2,r3
sll r0,r1 || ldi r2,#1
.text
.global slli
slli:
slli r0,#1 || slli r2,#31
mul r0,r1 || slli r2,#31
slli r0,#1 || mul r2,r3
ldi r0,#1 || slli r2,#31
slli r0,#1 || ldi r2,#1
.text
.global sra
sra:
sra r0,r1 || sra r2,r3
mul r0,r1 || sra r2,r3
sra r0,r1 || mul r2,r3
ldi r0,#1 || sra r2,r3
sra r0,r1 || ldi r2,#1
.text
.global srai
srai:
srai r0,#1 || srai r2,#31
mul r0,r1 || srai r2,#31
srai r0,#1 || mul r2,r3
ldi r0,#1 || srai r2,#31
srai r0,#1 || ldi r2,#1
.text
.global sra
srl:
srl r0,r1 || srl r2,r3
mul r0,r1 || srl r2,r3
srl r0,r1 || mul r2,r3
ldi r0,#1 || srl r2,r3
srl r0,r1 || ldi r2,#1
.text
.global srai
srli:
srli r0,#1 || srli r2,#31
mul r0,r1 || srli r2,#31
srli r0,#1 || mul r2,r3
ldi r0,#1 || srli r2,#31
srli r0,#1 || ldi r2,#1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] Add new model m32r2 of Renesas M32R.
2003-12-02 11:04 [PATCH] Add new model m32r2 of Renesas M32R Kazuhiro Inaoka
@ 2003-12-03 17:45 ` Nick Clifton
2003-12-03 18:39 ` Frank Ch. Eigler
2003-12-04 1:34 ` Kazuhiro Inaoka
0 siblings, 2 replies; 4+ messages in thread
From: Nick Clifton @ 2003-12-03 17:45 UTC (permalink / raw)
To: Kazuhiro Inaoka; +Cc: cgen, gdb-patches, binutils
Hi Kazuhiro-san,
> The attached patches and files add new model m32r2 of Renesas M32R
> architecture support.
Thank you very much. I have applied the binutils and cgen specific
part of your patches along with a couple of changes to the gas
directory:
* I made the -error-explicit-parallel-conflicts switch actually
generate error messages.
* I added a -big switch and a .big pseudo op along the lines of the
-little switch and .little pseudo op that your patch created.
* I updated the documentation file gas/doc/c-m32r.texi to document
the new support for the M32R2 processor. I also mentioned the new
support in the gas/NEWS file.
* I made the code that decides if sequential instructions should be
converted into parallel instructions use the parallel() function.
The gdb parts of your patches will have to be approved by a GDB
maintainer.
Cheers
Nick
> cgen/ChangeLog
> 2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
>
> * cpu/m32r.cpu : Add new model m32r2.
> Add new instructions.
> Replace occurrences of 'Mitsubishi' with 'Renesas'.
> Changed PIPE attr of push from O to OS.
> Care for Little-endian of M32R.
> * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
> Care for Little-endian of M32R.
> (parse_slo16): signed extension for value.
>
> bfd/ChangeLog
> 2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
>
> * archures.c (bfd_mach_m32r2): New machine types.
> * cpu-m32r.c : New machine types.
> * elf32-m32r.c (m32r_elf_object_p, m32r_elf_final_write_processing,
> m32r_elf_merge_private_bfd_data): New machine types.
>
> gas/ChangeLog
> 2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
>
> * config/tc-m32r.c : Add new machine m32r2.
> Add new instructions.
> (line_separator_chars) : Use '!'.
> * config/tc-m32r.h : Add new machine m32r2.
>
> gas/testsuite/ChangeLog
> 2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
>
> * gas/m32r/m32r2.exp : New file for m32r2.
> * gas/m32r/m32r2.s : Likewise.
> * gas/m32r/m32r2.d : Likewise.
>
> include/ChangeLog
> 2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
>
> * elf/m32r.h : Add new machine type m32r2 and instruction modes.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] Add new model m32r2 of Renesas M32R.
2003-12-03 17:45 ` Nick Clifton
@ 2003-12-03 18:39 ` Frank Ch. Eigler
2003-12-04 1:34 ` Kazuhiro Inaoka
1 sibling, 0 replies; 4+ messages in thread
From: Frank Ch. Eigler @ 2003-12-03 18:39 UTC (permalink / raw)
To: Nick Clifton; +Cc: Kazuhiro Inaoka, cgen, sid
[-- Attachment #1: Type: text/plain, Size: 492 bytes --]
Hi -
On Wed, Dec 03, 2003 at 05:41:37PM +0000, Nick Clifton wrote:
> Hi Kazuhiro-san,
>
> > The attached patches and files add new model m32r2 of Renesas M32R
> > architecture support.
>
> Thank you very much. I have applied the binutils and cgen specific
> part of your patches along with a couple of changes to the gas
> directory:
> [...]
Thanks to both of you.
I'll see if a m32r port of sid is easy to update to this
new chip, and if so, will commit that.
- FChE
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] Add new model m32r2 of Renesas M32R.
2003-12-03 17:45 ` Nick Clifton
2003-12-03 18:39 ` Frank Ch. Eigler
@ 2003-12-04 1:34 ` Kazuhiro Inaoka
1 sibling, 0 replies; 4+ messages in thread
From: Kazuhiro Inaoka @ 2003-12-04 1:34 UTC (permalink / raw)
To: Nick Clifton; +Cc: cgen, gdb-patches, binutils
Hi Nick
Thanks!
Kazuhiro
> Hi Kazuhiro-san,
>
> > The attached patches and files add new model m32r2 of Renesas M32R
> > architecture support.
>
> Thank you very much. I have applied the binutils and cgen specific
> part of your patches along with a couple of changes to the gas
> directory:
>
> * I made the -error-explicit-parallel-conflicts switch actually
> generate error messages.
>
> * I added a -big switch and a .big pseudo op along the lines of the
> -little switch and .little pseudo op that your patch created.
>
> * I updated the documentation file gas/doc/c-m32r.texi to document
> the new support for the M32R2 processor. I also mentioned the new
> support in the gas/NEWS file.
>
> * I made the code that decides if sequential instructions should be
> converted into parallel instructions use the parallel() function.
>
> The gdb parts of your patches will have to be approved by a GDB
> maintainer.
>
> Cheers
> Nick
>
> > cgen/ChangeLog
> > 2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
> >
> > * cpu/m32r.cpu : Add new model m32r2.
> > Add new instructions.
> > Replace occurrences of 'Mitsubishi' with 'Renesas'.
> > Changed PIPE attr of push from O to OS.
> > Care for Little-endian of M32R.
> > * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
> > Care for Little-endian of M32R.
> > (parse_slo16): signed extension for value.
> >
> > bfd/ChangeLog
> > 2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
> >
> > * archures.c (bfd_mach_m32r2): New machine types.
> > * cpu-m32r.c : New machine types.
> > * elf32-m32r.c (m32r_elf_object_p,
m32r_elf_final_write_processing,
> > m32r_elf_merge_private_bfd_data): New machine types.
> >
> > gas/ChangeLog
> > 2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
> >
> > * config/tc-m32r.c : Add new machine m32r2.
> > Add new instructions.
> > (line_separator_chars) : Use '!'.
> > * config/tc-m32r.h : Add new machine m32r2.
> >
> > gas/testsuite/ChangeLog
> > 2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
> >
> > * gas/m32r/m32r2.exp : New file for m32r2.
> > * gas/m32r/m32r2.s : Likewise.
> > * gas/m32r/m32r2.d : Likewise.
> >
> > include/ChangeLog
> > 2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
> >
> > * elf/m32r.h : Add new machine type m32r2 and instruction modes.
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2003-12-04 1:34 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2003-12-02 11:04 [PATCH] Add new model m32r2 of Renesas M32R Kazuhiro Inaoka
2003-12-03 17:45 ` Nick Clifton
2003-12-03 18:39 ` Frank Ch. Eigler
2003-12-04 1:34 ` Kazuhiro Inaoka
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