64-bit instruction word w/ multiple opcodes

64-bit instruction word w/ multiple opcodes

[Brian Mokrzycki]

I apologize if this message is inappropriate for this mailing list,  
but I didn't find an alternative.


This is my first attempt at porting the binutils to a new  
architecture.  I have quite a few questions.  The processor I'm  
targeting is a custom build DSP processor with static 64-bit  
instruction words.  Each 64-bit word is actually encodes two separate  
instructions.  The first 43 bits are used as general integer  
instructions (integer arithmetic, load/stores, branching).  The final  
21 bits encode a floating point operation.  An instruction word will  
always be encoded into 64-bits even if the integer and/or fop  
operation are NOPs.

63----------INT-----------21   20----FP----0


I've been struggling with cgen to describe this correctly.  I would  
like the assembly to show these two operations per line allowing the  
programmer to visualize how things are flowing between these  
functional units.  This idea was taken from m32r port.  An example is  
as follows:

ld r0,r3,r2	||	fadd f2,f3,f4


How should I describe this in cgen?  Since the integer and fp opcodes  
are really independent of each other I could define them as seperate  
ISAs.    THe problem with defining them as one 43 bit and one 21 bit  
ISA is that bfd really likes things to be byte aligned. So that gave  
me problems.  Is there a way to get around this?

I also tried using insn_macros in an attempt to have cgen identify  
multiple mnemonics per line.  This went no where.  Possible?

   Finally, I tried yet another approach by combined all the int & fp  
ops into one ISA.  Each single mnemonic was encoded as a 64-bit word.   
I then edited md_assemble to merge the two together into the final  
word.  Well that seemed to work alright for assembly, but now  
dissassembly is giving me problems.   Multiple instruction mneumonics  
have the same encodings, so it ends up decoding to the first "correct"  
hash it encounters in the dis hash.  Which isn't always correct.

The last method gave me partial success but I'm wondering, is there an  
easier way to do this?

On a separate note.  Is there support for 64-bit instructions?   
Because I had to hack a few places to make that work.

#define CGEN_INSN_INT unsigned long long int
(changed some masking things)
(some buffers needed to be expanded)


-Brian

Re: 64-bit instruction word w/ multiple opcodes

[Dave Brolley]

Brian Mokrzycki wrote:
> I apologize if this message is inappropriate for this mailing list, 
> but I didn't find an alternative.
>
>
> This is my first attempt at porting the binutils to a new 
> architecture.  I have quite a few questions.  The processor I'm 
> targeting is a custom build DSP processor with static 64-bit 
> instruction words.  Each 64-bit word is actually encodes two separate 
> instructions.  The first 43 bits are used as general integer 
> instructions (integer arithmetic, load/stores, branching).  The final 
> 21 bits encode a floating point operation.  An instruction word will 
> always be encoded into 64-bits even if the integer and/or fop 
> operation are NOPs.
>
> 63----------INT-----------21   20----FP----0
You certainly picked an interesting chip for your first attempt!
>
> I've been struggling with cgen to describe this correctly.  I would 
> like the assembly to show these two operations per line allowing the 
> programmer to visualize how things are flowing between these 
> functional units.  This idea was taken from m32r port.  An example is 
> as follows:
>
> ld r0,r3,r2    ||    fadd f2,f3,f4
>
>
> How should I describe this in cgen?  Since the integer and fp opcodes 
> are really independent of each other I could define them as seperate 
> ISAs.    THe problem with defining them as one 43 bit and one 21 bit 
> ISA is that bfd really likes things to be byte aligned. So that gave 
> me problems.  Is there a way to get around this?
The mep port is similar to this in that it combines core and coprocessor 
insns into bundles. It was done using separate ISAs as you have 
suggested. The assembler outputs them in the way you describe, so it may 
be a starting point for you to look at. The issue is, of course the 
43-21 bit alignment. I think you could get around this by defining the 
integer ISA to be 64 bits wide (with an unused 21 bit operand at the end 
of each insn) and the other to be 32 bits wide (with an unused 11 bit 
operand at the start of each insn). After processing the integer insn, 
you would need to reset the PC before processing the floating point insn.
>
> I also tried using insn_macros in an attempt to have cgen identify 
> multiple mnemonics per line.  This went no where.  Possible?
>
>   Finally, I tried yet another approach by combined all the int & fp 
> ops into one ISA.  Each single mnemonic was encoded as a 64-bit word.  
> I then edited md_assemble to merge the two together into the final 
> word.  Well that seemed to work alright for assembly, but now 
> dissassembly is giving me problems.   Multiple instruction mneumonics 
> have the same encodings, so it ends up decoding to the first "correct" 
> hash it encounters in the dis hash.  Which isn't always correct.
Can you give an example of different insn mnemonics which have the same 
encoding?
>
> The last method gave me partial success but I'm wondering, is there an 
> easier way to do this?
>
> On a separate note.  Is there support for 64-bit instructions?  
> Because I had to hack a few places to make that work.
The mep port has 64 bit insns. If you post your changes, they may be 
useful for others down the road.

I hope this helps,
Dave

Re: 64-bit instruction word w/ multiple opcodes

[Brian Mokrzycki]

I've finally gotten back to this and have made some good progress  
using your suggestions.  Currently I have two ISA defined one with 64- 
bits for the integer operations and a 32-bit one for floating point  
operations.  During assembly I divide the incoming string using the  
"II" token and process each instruction separately.  Then before they  
are set to be finished up and sent to bfd for output I bitwise OR the  
32-bit to the lower 32-bits of the 64-bit instruction.  This seems to  
work.

The biggest problem I've had is with disassembly.  Looking at the MEP  
port it seems that it's able to select between ISAs before it calls  
the print_insn function.  I tried the same trick with no luck.  Here's  
what my code looks like...


static int
wvfe_print_insn (CGEN_CPU_DESC cd,
                  bfd_vma pc,
                  disassemble_info *info)
{
   int status;
   int i;
   static CGEN_BITSET * isa_select = NULL;
   int buflen = 8;
   const bfd_byte mask[8] = {0x00, 0x00, 0xe0, 0xFF, 0xFF, 0xFF, 0xFF,  
0xFF};
   bfd_byte buf[8];
   bfd_byte cop_buf[8];
   bfd_byte fop_buf[8];

   if(isa_select == NULL)
     isa_select = cgen_bitset_create (ISA_MAX);

   // Read the Instruction
   status = (*info->read_memory_func) (pc, buf, buflen, info);

   if(status != 0) {
     (*info->memory_error_func) (status, pc, info);
     return -1;
   }
   for (i = 0; i < buflen; i++) {
     cop_buf[i] = buf[i] & mask[i];
     fop_buf[i] = buf[i] & (~mask[i]);
   }

   cd->isas = isa_select;

   cgen_bitset_set(isa_select, ISA_WVFE_COP);
   status = print_insn(cd, pc, info, cop_buf, buflen);

   (*info->fprintf_func) (info->stream, "\t|| ");

   cgen_bitset_set(isa_select, ISA_WVFE_FOP);
   // Feed in only the first 4 bytes for the 32-bit FOP instruction
   status = print_insn(cd, pc, info, &(fop_buf[0]), 4);

   // Will be fixed to report correct length
   return 8;
}

It seems that changing cd->isas to be ISA_WVFE_COP or ISA_WVFE_FOP  
only makes no difference in which list of instructions it compares  
against.  I wasn't able to find anything in the MEP code that was  
doing anything substantially different.  So how do I select a specific  
ISA?

-Brian


On Sep 24, 2008, at 9:41 AM, Dave Brolley wrote:

> Brian Mokrzycki wrote:
>> I apologize if this message is inappropriate for this mailing list,  
>> but I didn't find an alternative.
>>
>>
>> This is my first attempt at porting the binutils to a new  
>> architecture.  I have quite a few questions.  The processor I'm  
>> targeting is a custom build DSP processor with static 64-bit  
>> instruction words.  Each 64-bit word is actually encodes two  
>> separate instructions.  The first 43 bits are used as general  
>> integer instructions (integer arithmetic, load/stores, branching).   
>> The final 21 bits encode a floating point operation.  An  
>> instruction word will always be encoded into 64-bits even if the  
>> integer and/or fop operation are NOPs.
>>
>> 63----------INT-----------21   20----FP----0
> You certainly picked an interesting chip for your first attempt!
>>
>> I've been struggling with cgen to describe this correctly.  I would  
>> like the assembly to show these two operations per line allowing  
>> the programmer to visualize how things are flowing between these  
>> functional units.  This idea was taken from m32r port.  An example  
>> is as follows:
>>
>> ld r0,r3,r2    ||    fadd f2,f3,f4
>>
>>
>> How should I describe this in cgen?  Since the integer and fp  
>> opcodes are really independent of each other I could define them as  
>> seperate ISAs.    THe problem with defining them as one 43 bit and  
>> one 21 bit ISA is that bfd really likes things to be byte aligned.  
>> So that gave me problems.  Is there a way to get around this?
> The mep port is similar to this in that it combines core and  
> coprocessor insns into bundles. It was done using separate ISAs as  
> you have suggested. The assembler outputs them in the way you  
> describe, so it may be a starting point for you to look at. The  
> issue is, of course the 43-21 bit alignment. I think you could get  
> around this by defining the integer ISA to be 64 bits wide (with an  
> unused 21 bit operand at the end of each insn) and the other to be  
> 32 bits wide (with an unused 11 bit operand at the start of each  
> insn). After processing the integer insn, you would need to reset  
> the PC before processing the floating point insn.
>>
>> I also tried using insn_macros in an attempt to have cgen identify  
>> multiple mnemonics per line.  This went no where.  Possible?
>>
>>  Finally, I tried yet another approach by combined all the int & fp  
>> ops into one ISA.  Each single mnemonic was encoded as a 64-bit  
>> word.  I then edited md_assemble to merge the two together into the  
>> final word.  Well that seemed to work alright for assembly, but now  
>> dissassembly is giving me problems.   Multiple instruction  
>> mneumonics have the same encodings, so it ends up decoding to the  
>> first "correct" hash it encounters in the dis hash.  Which isn't  
>> always correct.
> Can you give an example of different insn mnemonics which have the  
> same encoding?
>>
>> The last method gave me partial success but I'm wondering, is there  
>> an easier way to do this?
>>
>> On a separate note.  Is there support for 64-bit instructions?   
>> Because I had to hack a few places to make that work.
> The mep port has 64 bit insns. If you post your changes, they may be  
> useful for others down the road.
>
> I hope this helps,
> Dave
>
>