* Re: Question about cpu description
[not found] <F122OBN8xK2efVXGmZS0000b16c@hotmail.com>
@ 2002-09-03 7:38 ` Ben Elliston
0 siblings, 0 replies; only message in thread
From: Ben Elliston @ 2002-09-03 7:38 UTC (permalink / raw)
To: 姹 缈; +Cc: cgen
Hi.
>>>>> "dam" == dam wang <gb2312> writes:
dam> How do CGEN know what the vitual cpu would do when one Ins was excuted. I
dam> mean, when I write the description file, nothing that describe the action
dam> of each Ins(at least I haven't found it till after I read the exited m32r
dam> description file.) is included.
The CPU description includes a semantics definition that describes
that the instruction does when it is executed. For example, from the
M32R description:
(dni addv3 "addv3"
()
"addv3 $dr,$sr,$simm16"
(+ OP1_8 OP2_8 dr sr simm16)
(parallel ()
(set dr (add sr simm16))
(set condbit (add-oflag sr simm16 (const 0))))
()
)
So, `dr' is set to the sum of `sr' and `simm16' and the condbit is set
accordingly. The instruction semantics are defined using a register
transfer language similar to GCC -- you can read more about it in the
CGEN manual. There is an entire chapter dedicated to CGEN RTL.
Ben
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2002-09-03 7:38 ` Question about cpu description Ben Elliston
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