From: Doug Evans <dje@transmeta.com>
To: "Frank Ch. Eigler" <fche@redhat.com>
Cc: Manuel Kessler <mlkessle@cip.physik.uni-wuerzburg.de>,
cgen@sources.redhat.com
Subject: Re: make CGEN a less moving target?
Date: Wed, 11 Dec 2002 13:50:00 -0000 [thread overview]
Message-ID: <15863.45845.671543.75854@xris-athlon.transmeta.com> (raw)
In-Reply-To: <20021211164238.C16403@redhat.com>
Frank Ch. Eigler writes:
> Hi -
>
> > > The most important value is the base-insn-size. This should be
> > > large enough to include all opcode-like bits in the longest
> > > instruction, so most likely 16 or even 32 for this chip. [...]
> >
> > If the definition of base-insn-size has been changed to this that's a bummer.
> > When did this go in?
>
> I believe this is a practical description of what actually tends
> to work with the opcodes/sim/sid runtimes, and does not relate to
> any recent patches.
So how about rephrase it as:
This is what the h/w first fetches to decode an insn.
For non-liw architectures this is the size of the smallest instruction.
next prev parent reply other threads:[~2002-12-11 21:50 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-12-10 8:48 Johan Rydberg
2002-12-10 9:33 ` Doug Evans
2002-12-10 17:06 ` Johan Rydberg
2002-12-11 2:39 ` Manuel Kessler
2002-12-11 4:18 ` Frank Ch. Eigler
2002-12-11 13:36 ` Doug Evans
2002-12-11 13:42 ` Frank Ch. Eigler
2002-12-11 13:50 ` Doug Evans [this message]
2002-12-11 13:57 ` Frank Ch. Eigler
2002-12-11 14:25 ` Doug Evans
2002-12-11 10:08 ` Doug Evans
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