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From: David Carney <dfcarney@net-itech.com>
To: cgen@sources.redhat.com
Subject: variable width instructions
Date: Fri, 20 Dec 2002 14:59:00 -0000	[thread overview]
Message-ID: <200212201757.54789.dfcarney@net-itech.com> (raw)

I'm trying to write a .cpu file for a simple, non-pipelined (CISC) chip.  The 
instructions and data are all 16 bits (little endian).  Defining the 
instruction fields was relatively straight forward, until I realised that 
instructions involving 'immediate' datum are, in fact, 32 bits...

My question is: how I should go about defining the instruction fields for this 
architecture?  I.e. what value should I use for the "start" fields in 
"(define-ifield ...)" for the msb so that instruction fields are compatible 
for both 16-bit and (the effectively) 32-bit instructions (15 or 31) ?

My confusion stems from observing the line:

	(dnf f-i32       "32 bit immediate"      (SIGN-OPT) 16 32)

in fr30.cpu.  Doesn't the "16 32" denote that the start of the opcode is at 
bit 16, but the length is 32?  For my ISA I need something equivalent to 
"start" = -1, "length" = 16.  How do I go about this?

Dave Carney


             reply	other threads:[~2002-12-20 22:59 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2002-12-20 14:59 David Carney [this message]
2002-12-20 18:23 ` Frank Ch. Eigler
2002-12-21 21:13 ` Doug Evans
2003-02-07 14:40 ` Again: " Manuel Kessler
2003-02-07 21:06   ` Jan Zizka

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