From: "Frank Ch. Eigler" <fche@redhat.com>
To: Hans-Peter Nilsson <hans-peter.nilsson@axis.com>
Cc: cgen@sourceware.org
Subject: Re: [RFA:] Fix breakage of manually building SID CPU
Date: Wed, 15 Mar 2006 20:11:00 -0000 [thread overview]
Message-ID: <20060315201107.GA22198@redhat.com> (raw)
In-Reply-To: <200603151923.k2FJNEPH028873@ignucius.se.axis.com>
Hi -
> But it's not. A delayed branch doesn't (necessarily or usually)
> run in parallel with the delayed instruction or the one after
> the delayed one.
One could sort of consider the delayed update to PC running in
parallel with the next instruction, sort of. I don't recall all
aspects of the design/notational decisions now. The work was
certainly done for a processor that was "worst" of all worlds in terms
of VLIW and open pipelines. Association with the cpu "parallel" field
may have been for simplicity, using that as a mode selector instead of
searching through the entire rtl for occurrences of (delay).
See also: http://sourceware.org/ml/cgen/2003-q1/msg00004.html
- FChE
prev parent reply other threads:[~2006-03-15 20:11 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-01-23 3:31 Hans-Peter Nilsson
2006-01-30 17:21 ` Dave Brolley
2006-03-14 13:34 ` Hans-Peter Nilsson
2006-03-14 16:46 ` Dave Brolley
2006-03-14 17:03 ` Hans-Peter Nilsson
2006-03-14 17:17 ` Frank Ch. Eigler
2006-03-14 21:24 ` Hans-Peter Nilsson
2006-03-14 22:04 ` Dave Brolley
2006-03-14 22:48 ` Frank Ch. Eigler
2006-03-14 23:05 ` Dave Brolley
2006-03-15 0:20 ` Hans-Peter Nilsson
2006-03-15 1:24 ` Hans-Peter Nilsson
2006-03-15 17:08 ` Dave Brolley
2006-03-15 17:14 ` Doug Evans
2006-03-15 18:18 ` Dave Brolley
2006-03-15 19:23 ` Hans-Peter Nilsson
2006-03-15 19:49 ` Dave Brolley
2006-03-15 20:11 ` Frank Ch. Eigler [this message]
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