Re: how can one achieve pipelined operation?

["Frank Ch. Eigler" <fche@redhat.com>]

HI -

On Wed, Jul 01, 2009 at 08:05:10PM -0700, Doug Evans wrote:
> [...]
> >An exposed pipeline is reasonably easily modelled with deferred write
> >queues in a sid-based simulator; see the mep port.
>
> Thanks.  The semantics for each instruction are generated from cgen, 
> but  the pipeline (i.e. instruction fetch, execute, retire) is handcrafted.
> [Right?]

We have not had to model some details of an ordinary interlocked
pipeline (e.g., a separate "fetch" stage) since they do not affect the
visible execution of a normal program, only performance.  For cycle
counting purposes, cgen has some support (functional unit
parametrization), though by nature simple counting models are gross
exaggerations of real complex CPUs.

For unusual pipelines where some interlocks were missing (so a "write"
of some sort in one pipeline stage could be briefly invisible to a
"read" in another functional unit), assembly programs *are* exposed to
the operation of the pipeline.  So, in sid, the deferred-write-queue
mechanism was built to model that, as driven by the
   (delay N (set ... ...))
directive in cgen semantics.

I don't know which of these two different aspects you need.

- FChE