Re: how can one achieve pipelined operation?

[Dave Korn <dave.korn.cygwin@googlemail.com>]

Doug Evans wrote:
> Frank Ch. Eigler wrote:
>> Hi -
>>
>>  
>>> I have been working on a port for a while now, and I think everything is
>>> working except the pipeline.  I have tried changing the values of
>>> issue and
>>> done in the functional unit description and I have added a pipeline
>>> statement to define-model.  What do I need to do to achieve pipelined
>>> operation and/or is there an existing example?
>>>     
>>
>> An exposed pipeline is reasonably easily modelled with deferred write
>> queues in a sid-based simulator; see the mep port.
>>
>>   
> 
> Thanks.  The semantics for each instruction are generated from cgen,
> but  the pipeline (i.e. instruction fetch, execute, retire) is handcrafted.
> [Right?]
> 
> Joseph: I think that's the way to go for right now.
> 

  I'm kinda new to cgen and was planning to try soemthing similar.  My first
thought was that I should actually try and explicitly model the different
stages of the pipeline as separate units in my model, and actually pass
instruction operands as outputs from one to the next as inputs, along with a
few control signals like 'stall' and 'ready', with the u-exec unit at the end
of the chain.  Wouldn't that work?

    cheers,
      DaveK