From: Doug Evans <dje@sebabeach.org>
To: cgen@sourceware.org
Subject: [commit] support for instruction with words > 32 bits
Date: Mon, 23 Nov 2009 01:03:00 -0000 [thread overview]
Message-ID: <20091123010254.04E476E3DE@sebabeach.org> (raw)
Hi. This patch adds beginnings for support for instructions with
words > 32 bits.
[e.g. for architectures where it's preferable to record insns in 64 bits ints]
2009-11-22 Doug Evans <dje@sebabeach.org>
* mach.scm (<derived-arch-data>): New member large-insn-word?.
(/adata-set-derived!): Set it.
(adata-large-insn-word?): New function.
* sim-arch.scm (/gen-cpuall-includes): Don't #include cgen-engine.h
here.
* sim-cpu.scm (cgen-cpu.h): #include it here.
(/gen-cpu-defines): Define CGEN_INSN_WORD.
(/gen-no-scache-semantic-fn): Use CGEN_INSN_WORD instead of
CGEN_INSN_INT.
* sim-decode.scm (/gen-idesc-decls): Ditto.
(/gen-extract-case, /gen-decode-fn): Ditto.
* sim-model.scm (/gen-model-insn-fn): Ditto.
* sim.scm (gen-argbuf-type): Ditto.
reply other threads:[~2009-11-23 1:03 UTC|newest]
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