* how can one achieve pipelined operation? @ 2009-06-25 20:54 Joseph A 2009-07-01 10:50 ` Frank Ch. Eigler 0 siblings, 1 reply; 9+ messages in thread From: Joseph A @ 2009-06-25 20:54 UTC (permalink / raw) To: cgen I have been working on a port for a while now, and I think everything is working except the pipeline. I have tried changing the values of issue and done in the functional unit description and I have added a pipeline statement to define-model. What do I need to do to achieve pipelined operation and/or is there an existing example? Joseph -- View this message in context: http://www.nabble.com/how-can-one-achieve-pipelined-operation--tp24210860p24210860.html Sent from the Sourceware - cgen list mailing list archive at Nabble.com. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: how can one achieve pipelined operation? 2009-06-25 20:54 how can one achieve pipelined operation? Joseph A @ 2009-07-01 10:50 ` Frank Ch. Eigler 2009-07-02 3:05 ` Doug Evans 0 siblings, 1 reply; 9+ messages in thread From: Frank Ch. Eigler @ 2009-07-01 10:50 UTC (permalink / raw) To: Joseph A; +Cc: cgen Hi - > I have been working on a port for a while now, and I think everything is > working except the pipeline. I have tried changing the values of issue and > done in the functional unit description and I have added a pipeline > statement to define-model. What do I need to do to achieve pipelined > operation and/or is there an existing example? An exposed pipeline is reasonably easily modelled with deferred write queues in a sid-based simulator; see the mep port. - FChE ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: how can one achieve pipelined operation? 2009-07-01 10:50 ` Frank Ch. Eigler @ 2009-07-02 3:05 ` Doug Evans 2009-07-02 12:09 ` Dave Korn 2009-07-02 12:29 ` Frank Ch. Eigler 0 siblings, 2 replies; 9+ messages in thread From: Doug Evans @ 2009-07-02 3:05 UTC (permalink / raw) To: Frank Ch. Eigler; +Cc: Joseph A, cgen Frank Ch. Eigler wrote: > Hi - > > >> I have been working on a port for a while now, and I think everything is >> working except the pipeline. I have tried changing the values of issue and >> done in the functional unit description and I have added a pipeline >> statement to define-model. What do I need to do to achieve pipelined >> operation and/or is there an existing example? >> > > An exposed pipeline is reasonably easily modelled with deferred write > queues in a sid-based simulator; see the mep port. > > Thanks. The semantics for each instruction are generated from cgen, but the pipeline (i.e. instruction fetch, execute, retire) is handcrafted. [Right?] Joseph: I think that's the way to go for right now. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: how can one achieve pipelined operation? 2009-07-02 3:05 ` Doug Evans @ 2009-07-02 12:09 ` Dave Korn 2009-07-02 12:29 ` Frank Ch. Eigler 1 sibling, 0 replies; 9+ messages in thread From: Dave Korn @ 2009-07-02 12:09 UTC (permalink / raw) To: Doug Evans; +Cc: Frank Ch. Eigler, Joseph A, cgen Doug Evans wrote: > Frank Ch. Eigler wrote: >> Hi - >> >> >>> I have been working on a port for a while now, and I think everything is >>> working except the pipeline. I have tried changing the values of >>> issue and >>> done in the functional unit description and I have added a pipeline >>> statement to define-model. What do I need to do to achieve pipelined >>> operation and/or is there an existing example? >>> >> >> An exposed pipeline is reasonably easily modelled with deferred write >> queues in a sid-based simulator; see the mep port. >> >> > > Thanks. The semantics for each instruction are generated from cgen, > but the pipeline (i.e. instruction fetch, execute, retire) is handcrafted. > [Right?] > > Joseph: I think that's the way to go for right now. > I'm kinda new to cgen and was planning to try soemthing similar. My first thought was that I should actually try and explicitly model the different stages of the pipeline as separate units in my model, and actually pass instruction operands as outputs from one to the next as inputs, along with a few control signals like 'stall' and 'ready', with the u-exec unit at the end of the chain. Wouldn't that work? cheers, DaveK ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: how can one achieve pipelined operation? 2009-07-02 3:05 ` Doug Evans 2009-07-02 12:09 ` Dave Korn @ 2009-07-02 12:29 ` Frank Ch. Eigler 2009-07-02 16:45 ` Joseph A 1 sibling, 1 reply; 9+ messages in thread From: Frank Ch. Eigler @ 2009-07-02 12:29 UTC (permalink / raw) To: Doug Evans; +Cc: Joseph A, cgen HI - On Wed, Jul 01, 2009 at 08:05:10PM -0700, Doug Evans wrote: > [...] > >An exposed pipeline is reasonably easily modelled with deferred write > >queues in a sid-based simulator; see the mep port. > > Thanks. The semantics for each instruction are generated from cgen, > but the pipeline (i.e. instruction fetch, execute, retire) is handcrafted. > [Right?] We have not had to model some details of an ordinary interlocked pipeline (e.g., a separate "fetch" stage) since they do not affect the visible execution of a normal program, only performance. For cycle counting purposes, cgen has some support (functional unit parametrization), though by nature simple counting models are gross exaggerations of real complex CPUs. For unusual pipelines where some interlocks were missing (so a "write" of some sort in one pipeline stage could be briefly invisible to a "read" in another functional unit), assembly programs *are* exposed to the operation of the pipeline. So, in sid, the deferred-write-queue mechanism was built to model that, as driven by the (delay N (set ... ...)) directive in cgen semantics. I don't know which of these two different aspects you need. - FChE ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: how can one achieve pipelined operation? 2009-07-02 12:29 ` Frank Ch. Eigler @ 2009-07-02 16:45 ` Joseph A 2009-07-12 2:27 ` Frank Ch. Eigler 0 siblings, 1 reply; 9+ messages in thread From: Joseph A @ 2009-07-02 16:45 UTC (permalink / raw) To: cgen As was suggested I have been trying to implement a pipeline with the (delay N (set ... ...)) directive using the directions given in the [RFA:] Fix breakage of manually building SID CPU thread, however my port has multiple ISAs. I get two errors which say "error: invalid initialization of reference of type '%ISA1%::write_stacks&' from expression of type '%CPU%::write_stacks'" and "error: invalid initialization of reference of type '%ISA2%::write_stacks&' from expression of type '%CPU%::write_stacks'". Also, the machine generated reset() and writeback() functions are empty. Did I miss something stupid? -- View this message in context: http://www.nabble.com/how-can-one-achieve-pipelined-operation--tp24210860p24310149.html Sent from the Sourceware - cgen list mailing list archive at Nabble.com. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: how can one achieve pipelined operation? 2009-07-02 16:45 ` Joseph A @ 2009-07-12 2:27 ` Frank Ch. Eigler 2009-07-30 20:12 ` Joseph A 0 siblings, 1 reply; 9+ messages in thread From: Frank Ch. Eigler @ 2009-07-12 2:27 UTC (permalink / raw) To: Joseph A; +Cc: cgen Hi - On Thu, Jul 02, 2009 at 09:44:54AM -0700, Joseph A wrote: > As was suggested I have been trying to implement a pipeline with the (delay N > (set ... ...)) directive using the directions given in the [RFA:] Fix > breakage of manually building SID CPU thread, however my port has multiple > ISAs. OK. > I get two errors which say "error: invalid initialization of > reference of type '%ISA1%::write_stacks&' from expression of type > '%CPU%::write_stacks'" and "error: invalid initialization of > reference of type '%ISA2%::write_stacks&' from expression of type > '%CPU%::write_stacks'". Also, the machine generated reset() and > writeback() functions are empty. These don't sound familiar to me. I can only advise that you refer to the sid simulator pieces generated & hand-written for other exposed-pipeline ports (mt, sh/*). - FChE ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: how can one achieve pipelined operation? 2009-07-12 2:27 ` Frank Ch. Eigler @ 2009-07-30 20:12 ` Joseph A 2009-07-30 20:19 ` Frank Ch. Eigler 0 siblings, 1 reply; 9+ messages in thread From: Joseph A @ 2009-07-30 20:12 UTC (permalink / raw) To: cgen > I get two errors which say "error: invalid initialization of > reference of type '%ISA1%::write_stacks&' from expression of type > '%CPU%::write_stacks'" and "error: invalid initialization of > reference of type '%ISA2%::write_stacks&' from expression of type > '%CPU%::write_stacks'". Problem solved. These two errors were caused by an incorrect makefile as well as incorrect code. In my %CPU%.h file I had declared write_stacks as %CPU%::write_stacks write_stacks. Instead I needed to declare two separate stacks, %ISA1%::write_stacks write_stacks1 and %ISA2%::write_stacks write_stacks2. I also discovered that I had not told CGEN to generate the files %CPU%-%ISAX%-defs.h. This caused me to get an incomplete definition error when I tried to make the altered code. I fixed this by going into the makefile in src/sid/component/cgen-cpu/%CPU% and altering it such that it would cause CGEN to generate the defs files, using the sh and mt ports as examples. -- View this message in context: http://www.nabble.com/how-can-one-achieve-pipelined-operation--tp24210860p24746519.html Sent from the Sourceware - cgen list mailing list archive at Nabble.com. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: how can one achieve pipelined operation? 2009-07-30 20:12 ` Joseph A @ 2009-07-30 20:19 ` Frank Ch. Eigler 0 siblings, 0 replies; 9+ messages in thread From: Frank Ch. Eigler @ 2009-07-30 20:19 UTC (permalink / raw) To: Joseph A; +Cc: cgen Hi - > Problem solved. [...] Well done, thanks for letting us know. - FChE ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2009-07-30 20:19 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2009-06-25 20:54 how can one achieve pipelined operation? Joseph A 2009-07-01 10:50 ` Frank Ch. Eigler 2009-07-02 3:05 ` Doug Evans 2009-07-02 12:09 ` Dave Korn 2009-07-02 12:29 ` Frank Ch. Eigler 2009-07-02 16:45 ` Joseph A 2009-07-12 2:27 ` Frank Ch. Eigler 2009-07-30 20:12 ` Joseph A 2009-07-30 20:19 ` Frank Ch. Eigler
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