[RFC] FR60/80 support.

[RFC] FR60/80 support.

[Masaki Muranaka]

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Hello,

Recently I'm trying to add FR60 and FR80 support based on FR30.
I've already succeed to assemble with gas and disassemble with objdump.

I'd like to contribute it but I'm not sure if my code is acceptable quality, because I'm new to cgen hack.

Could anyone review attached patch and give comment?
I'll post whole patch (includes gas/binutils) after this review.


--
Masaki Muranaka
Monami software


[-- Attachment #2: fr60-80support.diff --]
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? Makefile
? config.log
? config.status
? fr60-80support.diff
? gas-build.sh
? tmp-doc
? tmp-opc
? tmp-sid
? doc/Makefile
Index: cpu/fr30.cpu
===================================================================
RCS file: /cvs/src/src/cgen/cpu/fr30.cpu,v
retrieving revision 1.1
diff -u -p -r1.1 fr30.cpu
--- cpu/fr30.cpu	5 Jul 2001 12:45:47 -0000	1.1
+++ cpu/fr30.cpu	7 Jul 2009 00:16:31 -0000
@@ -12,7 +12,7 @@
   (comment "Fujitsu FR30")
   (default-alignment forced)
   (insn-lsb0? #f)
-  (machs fr30)
+  (machs fr30 fr60 fr80)
   (isas fr30)
 )
 
@@ -34,73 +34,110 @@
   (word-bitsize 32)
 )
 
+(define-cpu
+  ; cpu names must be distinct from the architecture name and machine names.
+  ; The "b" suffix stands for "base" and is the convention.
+  ; The "f" suffix stands for "family" and is the convention.
+  (name fr60bf)
+  (comment "Fujitsu FR60 base family")
+  (endian big)
+  (word-bitsize 32)
+)
+
+(define-cpu
+  ; cpu names must be distinct from the architecture name and machine names.
+  ; The "b" suffix stands for "base" and is the convention.
+  ; The "f" suffix stands for "family" and is the convention.
+  (name fr80bf)
+  (comment "Fujitsu FR80 base family")
+  (endian big)
+  (word-bitsize 32)
+)
+
 (define-mach
   (name fr30)
-  (comment "Generic FR30 cpu")
+  (comment "Fujitsu FR30")
   (cpu fr30bf)
+  (isas fr30)
+)
+(define-mach
+  (name fr60)
+  (comment "Fujitsu FR60")
+  (cpu fr60bf)
+  (isas fr30)
+)
+(define-mach
+  (name fr80)
+  (comment "Fujitsu FR80")
+  (cpu fr80bf)
+  (isas fr30)
 )
 \f
 ; Model descriptions.
 ;
-(define-model
-  (name fr30-1) (comment "fr30-1") (attrs)
-  (mach fr30)
-
-  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
-
-  ; `state' is a list of variables for recording model state
-  (state
-   ; bit mask of h-gr registers loaded from memory by previous insn
-   (load-regs UINT)
-   ; bit mask of h-gr registers loaded from memory by current insn
-   (load-regs-pending UINT)
-   )
-
-  (unit u-exec "Execution Unit" ()
-	1 1 ; issue done
-	() ; state
-	((Ri INT -1) (Rj INT -1)) ; inputs
-	((Ri INT -1)) ; outputs
-	() ; profile action (default)
-	)
-  (unit u-cti "Branch Unit" ()
-	1 1 ; issue done
-	() ; state
-	((Ri INT -1)) ; inputs
-	((pc)) ; outputs
-	() ; profile action (default)
-	)
-  (unit u-load "Memory Load Unit" ()
-	1 1 ; issue done
-	() ; state
-	((Rj INT -1)
-	 ;(ld-mem AI)
-	 ) ; inputs
-	((Ri INT -1)) ; outputs
-	() ; profile action (default)
-	)
-  (unit u-store "Memory Store Unit" ()
-	1 1 ; issue done
-	() ; state
-	((Ri INT -1) (Rj INT -1)) ; inputs
-	() ; ((st-mem AI)) ; outputs
-	() ; profile action (default)
-	)
-  (unit u-ldm "LDM Memory Load Unit" ()
-	1 1 ; issue done
-	() ; state
-	((reglist INT)) ; inputs
-	() ; outputs
-	() ; profile action (default)
-	)
-  (unit u-stm "STM Memory Store Unit" ()
-	1 1 ; issue done
-	() ; state
-	((reglist INT)) ; inputs
-	() ; outputs
-	() ; profile action (default)
-	)
-)
+(define-pmacro (define-fr30-series-model name1)
+  (define-model
+    (name name1) (comment (.str name1)) (attrs)
+    (mach fr30)
+
+    (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
+
+					; `state' is a list of variables for recording model state
+    (state
+					; bit mask of h-gr registers loaded from memory by previous insn
+     (load-regs UINT)
+					; bit mask of h-gr registers loaded from memory by current insn
+     (load-regs-pending UINT)
+     )
+
+    (unit u-exec "Execution Unit" ()
+	  1 1 ; issue done
+	  () ; state
+	  ((Ri INT -1) (Rj INT -1)) ; inputs
+	  ((Ri INT -1)) ; outputs
+	  () ; profile action (default)
+	  )
+    (unit u-cti "Branch Unit" ()
+	  1 1 ; issue done
+	  () ; state
+	  ((Ri INT -1)) ; inputs
+	  ((pc)) ; outputs
+	  () ; profile action (default)
+	  )
+    (unit u-load "Memory Load Unit" ()
+	  1 1 ; issue done
+	  () ; state
+	  ((Rj INT -1)
+					;(ld-mem AI)
+	   ) ; inputs
+	  ((Ri INT -1)) ; outputs
+	  () ; profile action (default)
+	  )
+    (unit u-store "Memory Store Unit" ()
+	  1 1 ; issue done
+	  () ; state
+	  ((Ri INT -1) (Rj INT -1)) ; inputs
+	  () ; ((st-mem AI)) ; outputs
+	  () ; profile action (default)
+	  )
+    (unit u-ldm "LDM Memory Load Unit" ()
+	  1 1 ; issue done
+	  () ; state
+	  ((reglist INT)) ; inputs
+	  () ; outputs
+	  () ; profile action (default)
+	  )
+    (unit u-stm "STM Memory Store Unit" ()
+	  1 1 ; issue done
+	  () ; state
+	  ((reglist INT)) ; inputs
+	  () ; outputs
+	  () ; profile action (default)
+	  )
+    ))
+(define-fr30-series-model fr30-1)
+(define-fr30-series-model fr60-1)
+(define-fr30-series-model fr80-1)
 \f
 ; The instruction fetch/execute cycle.
 ;
@@ -287,7 +324,7 @@
 (define-hardware
   (name h-cr)
   (comment "coprocessor registers")
-  (attrs)
+  (attrs (MACH fr30,fr60))
   (type register WI (16))
   (indices extern-keyword cr-names)
 )
@@ -648,7 +685,7 @@
 		 (set mode tmp (op mode (mem mode arg2) arg1))
 		 (set-z-and-n tmp)
 		 (set mode (mem mode arg2) tmp))
-       ((les-units fr30-1))
+       ((les-units fr30-1) (les-unit fr60-1) (les-unit fr80-1))
   )
 )
 
@@ -673,7 +710,7 @@
 	   (and QI
 		 (or  QI u4 (const #xf0))
 		 (mem QI Ri)))
-     ((les-units fr30-1))
+     ((les-units fr30-1) (les-unit fr60-1) (les-unit fr80-1))
 )
 
 (dni borl
@@ -682,7 +719,7 @@
      "borl $u4,@$Ri"
      (+ OP1_9 OP2_0 u4 Ri)
      (set QI (mem QI Ri) (or QI u4 (mem QI Ri)))
-     ((les-units fr30-1))
+     ((les-units fr30-1) (les-unit fr60-1) (les-unit fr80-1))
 )
 
 (dni beorl
@@ -691,7 +728,7 @@
      "beorl $u4,@$Ri"
      (+ OP1_9 OP2_8 u4 Ri)
      (set QI (mem QI Ri) (xor QI u4 (mem QI Ri)))
-     ((les-units fr30-1))
+     ((les-units fr30-1) (les-unit fr60-1) (les-unit fr80-1))
 )
 
 ; Binary logical instruction to high half of byte in memory
@@ -705,7 +742,7 @@
 	   (and QI
 		 (or QI (sll QI u4 (const 4)) (const #x0f))
 		 (mem QI Ri)))
-     ((les-units fr30-1))
+     ((les-units fr30-1) (les-unit fr60-1) (les-unit fr80-1))
 )
 
 (define-pmacro (binary-or-op-mh name insn opc1 opc2 op arg1 arg2)
@@ -718,7 +755,7 @@
 	     (insn QI
 		   (sll QI arg1 (const 4))
 		   (mem QI arg2)))
-       ((les-units fr30-1))
+       ((les-units fr30-1) (les-unit fr60-1) (les-unit fr80-1))
   )
 )
 
@@ -1546,7 +1583,7 @@
 ;
 (dni ldres
      "ldres @Ri+,#u4"
-     ()
+     ((MACH fr30,fr60))
      "ldres @$Ri+,$u4"
      (+ OP1_B OP2_C u4 Ri)
      (set Ri (add Ri (const 4)))
@@ -1555,7 +1592,7 @@
 
 (dni stres
      "stres #u4,@Ri+"
-     ()
+     ((MACH fr30,fr60))
      "stres $u4,@$Ri+"
      (+ OP1_B OP2_D u4 Ri)
      (set Ri (add Ri (const 4)))
@@ -1567,7 +1604,7 @@
 (define-pmacro (cop-stub name insn opc1 opc2 opc3 arg1 arg2)
   (dni name
        (.str insn " u4c,ccc,CRj," arg1 "," arg2)
-       (NOT-IN-DELAY-SLOT)
+       (NOT-IN-DELAY-SLOT (MACH fr30,fr60))
        (.str insn " $u4c,$ccc,$" arg1 ",$" arg2)
        (+ opc1 opc2 opc3 u4c ccc arg1 arg2)
        (nop) ; STUB
@@ -1843,3 +1880,33 @@
 	       (set (mem UQI Rj) tmp))
      ((fr30-1 (unit u-load) (unit u-store)))
 )
+
+;; bit search instructions
+;; they are supported by FR80
+(dni srch0
+     "srch0 Ri"
+     ((MACH fr80))
+     "srch0 $Ri"
+     (+ OP1_9 OP2_7 OP3_C Ri)
+     (c-raw-call WI "fr30_bitsearch0" Ri)
+     ()
+)
+
+(dni srch1
+     "srch1 Ri"
+     ((MACH fr80))
+     "srch1 $Ri"
+     (+ OP1_9 OP2_7 OP3_D Ri)
+     (c-raw-call WI "fr30_bitsearch1" Ri)
+     ()
+)
+
+
+(dni srchc
+     "srchc Ri"
+     ((MACH fr80))
+     "srchc $Ri"
+     (+ OP1_9 OP2_7 OP3_E Ri)
+     (c-raw-call WI "fr30_bitsearchc" Ri)
+     ()
+)

Re: [RFC] FR60/80 support.

[Doug Evans]

Masaki Muranaka wrote:
> Hello,
>
> Recently I'm trying to add FR60 and FR80 support based on FR30.
> I've already succeed to assemble with gas and disassemble with objdump.
>
> I'd like to contribute it but I'm not sure if my code is acceptable quality, because I'm new to cgen hack.
>
> Could anyone review attached patch and give comment?
> I'll post whole patch (includes gas/binutils) after this review.
>
>
> --
> Masaki Muranaka
> Monami software
>
>   

Hi.

The patch is basically fine.
I have a few minor comments.

The comments in this part are pushed over a bit too far, they wrap on my 
screen when there's no need.

+                                       ; `state' is a list of variables 
for recording model state
+    (state
+                                       ; bit mask of h-gr registers 
loaded from memory by previous insn
+     (load-regs UINT)
+                                       ; bit mask of h-gr registers 
loaded from memory by current insn
+     (load-regs-pending UINT)
+     )

I think you want (set Ri (c-raw-call WI "..." Ri)).
[I realize the fr30 simulator has been deleted from the gdb tree.]

+(dni srch0
+     "srch0 Ri"
+     ((MACH fr80))
+     "srch0 $Ri"
+     (+ OP1_9 OP2_7 OP3_C Ri)
+     (c-raw-call WI "fr30_bitsearch0" Ri)
+     ()
+)
+
+(dni srch1
+     "srch1 Ri"
+     ((MACH fr80))
+     "srch1 $Ri"
+     (+ OP1_9 OP2_7 OP3_D Ri)
+     (c-raw-call WI "fr30_bitsearch1" Ri)
+     ()
+)
+
+
+(dni srchc
+     "srchc Ri"
+     ((MACH fr80))
+     "srchc $Ri"
+     (+ OP1_9 OP2_7 OP3_E Ri)
+     (c-raw-call WI "fr30_bitsearchc" Ri)
+     ()
+)