From: Petronela Agache <petronela.silvia@gmail.com>
To: cgen@sourceware.org, cgen@sources.redhat.com
Subject: dni format description
Date: Thu, 05 Aug 2010 08:23:00 -0000 [thread overview]
Message-ID: <AANLkTimO+yiNchA2pkVn0PBYKsLxJj6P12VTo=Hzc_Pi@mail.gmail.com> (raw)
Hello,
My name is Petronela, i would like to get more info about the format
field from pmacros. For example the following insn is used in
m32r.cpu:
(dni addx "addx"
((PIPE OS) (IDOC ALU))
"addx $dr,$sr"
(+ OP1_0 OP2_9 dr sr)
(parallel ()
(set dr (addc dr sr condbit))
(set condbit (add-cflag dr sr condbit)))
()
)
What (+ OP1_0 OP2_9 dr sr) means ? OP1_* and OP2_* are defined in the
following way:
(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
("0" "1" "2" "3" "4" "5" "6" "7"
"8" "9" "10" "11" "12" "13" "14" "15")
)
(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
("0" "1" "2" "3" "4" "5" "6" "7"
"8" "9" "10" "11" "12" "13" "14" "15")
)
My understanding is that destination register is always R0 and source
register is always R9 for this type of insn. Is this correct ? Does
this not restrict the hardware usage ? Since this insn can be executed
on all R* registers.
Thank you
WARNING: multiple messages have this Message-ID
From: Petronela Agache <petronela.silvia@gmail.com>
To: cgen@sourceware.org, cgen@sources.redhat.com
Subject: dni format description
Date: Thu, 05 Aug 2010 12:36:00 -0000 [thread overview]
Message-ID: <AANLkTimO+yiNchA2pkVn0PBYKsLxJj6P12VTo=Hzc_Pi@mail.gmail.com> (raw)
Message-ID: <20100805123600.8YlF2d_Fo0vtwOCOFynY7rvAWo-go3mgCTF_bRuDK7w@z> (raw)
Hello,
My name is Petronela, i would like to get more info about the format
field from pmacros. For example the following insn is used in
m32r.cpu:
(dni addx "addx"
((PIPE OS) (IDOC ALU))
"addx $dr,$sr"
(+ OP1_0 OP2_9 dr sr)
(parallel ()
(set dr (addc dr sr condbit))
(set condbit (add-cflag dr sr condbit)))
()
)
What (+ OP1_0 OP2_9 dr sr) means ? OP1_* and OP2_* are defined in the
following way:
(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
("0" "1" "2" "3" "4" "5" "6" "7"
"8" "9" "10" "11" "12" "13" "14" "15")
)
(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
("0" "1" "2" "3" "4" "5" "6" "7"
"8" "9" "10" "11" "12" "13" "14" "15")
)
My understanding is that destination register is always R0 and source
register is always R9 for this type of insn. Is this correct ? Does
this not restrict the hardware usage ? Since this insn can be executed
on all R* registers.
Thank you
next reply other threads:[~2010-08-05 8:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-08-05 8:23 Petronela Agache [this message]
2010-08-05 12:36 ` Petronela Agache
2010-08-24 4:34 ` Jean-Marc Saffroy
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