From: Sergey Belyashov <sergey.belyashov@gmail.com>
To: cgen@sourceware.org
Subject: Re: Writing .cpu file for Z80
Date: Wed, 25 Mar 2020 00:20:33 +0300 [thread overview]
Message-ID: <CAOe0RDxiJD3pYUDx1N-=EYjZkzSyGWrR6WbGs7Jh=yan9uXL0A@mail.gmail.com> (raw)
In-Reply-To: <CAOe0RDxvHb73a9cWmr4UsQUj5PpirA-ZMPm2NEuu_KLv0b4vdA@mail.gmail.com>
Hi,
Today I try to implement 0xCB prefixed instructions. I add next
instructions:
(dnf f-0 "whole byte 0" ((MACH z80) all-isas) 7 8)
(dnf f-1 "whole byte 1" ((MACH z80) all-isas) 15 8)
(dnf f-1x "byte 1 field x, bits 7-6" ((MACH z80) all-isas) 15 2)
(dnf f-1y "byte 1 field y, bits 5-3" ((MACH z80) all-isas) 13 3)
(dnf f-1z "byte 1 field z, bits 2-0" ((MACH z80) all-isas) 10 3)
(dni rlc-mhl "rotate left cyclic" (all-isas) "rlc (hl)" (+ (f-0 #xCB)
(f-1x 0) (f-1y 0) (f-1z 6)) () ())
(dni rlc-r "rotate left cyclic" (all-isas) "rlc $rs1" (+ (f-0 #xCB)
(f-1x 0) (f-1y 0) rs1) () ())
(dni rrc-r "rotate right cyclic" (all-isas) "rrc $rs1" (+ (f-0 #xCB)
(f-1x 0) (f-1y 1) rs1) () ())
And disassembler disassemble all CB prefixed instructions as RLC <r>. So it
looks like explicit field value is not work. Next I see, what is generated
for these instructions in the z80-opc.c file:
/* retn */
{
{ 0, 0, 0, 0 },
{ { MNEM, 0 } },
& ifmt_retn, { 0x132 }
},
/* rlc $rs1 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RS1), 0 } },
& ifmt_rlc_r, { 0xcb }
},
/* rlc (hl) */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', '(', 'h', 'l', ')', 0 } },
& ifmt_rlc_mhl, { 0xd1 }
},
Why fields of different bytes are OR'ed?!?
Next, I try to specify following decode-splits for ISA:
(decode-splits
(f-y () ((s-reg8 (0 1 2 3 4 5 7)) (s-mhl (6))))
(f-z () ((s-reg8 (0 1 2 3 4 5 7)) (s-mhl (6))))
)
But CGEN fails with error:
machs: all
isas: all
options:
trace:
diags:
Including file ../../opcodes/../cpu/simplify.inc ...
ERROR: Wrong type argument in position 2: 3
No backtrace available.
decode-splits is present only one arm.cpu file, but it commented out. Is it
works?
Best regards,
Sergey Belyashov
вт, 24 мар. 2020 г. в 00:44, Sergey Belyashov <sergey.belyashov@gmail.com>:
> Hi,
> I trying to write .cpu file for Z80. Now I stopped in place, how to
> implement multibyte opcodes. Z80 instructions may have size from one byte
> to four bytes:
> <opcode> [<imm8>|<imm16>]
> <0xED> <opcode> [<imm8>|<imm16>]
> <0xCB> <opcode>
> <0xDD/0xFD> <0xCB> <disp8> <opcode>
> <0xDD/0xFD> <opcode> [<imm8>|<disp8>|<imm16>]
> <0xDD/0xFD> <opcode> <disp8> <imm8>
>
> First format is implemented, now I try second one. Starting from simple
> instruction RETN (ED 45):
> (dnf f-0 "whole byte 0" ((MACH z80) all-isas) 7 8)
> (dnf f-1 "whole byte 1" ((MACH z80) all-isas) 15 8)
> (dni retn "return from NMI handler" (all-isas UNCOND-CTI) "retn" (+
> (f-0 #xED) (f-1 #x45)) () ())
>
> But disassembler do not disassemble 0xED 0x45 sequence. I try declare
> opcode as one 16-bit field, but CGEN fails:
> > Error: Instruction has opcode bits outside of its mask.
> > This usually means some kind of error in the instruction's ifield list.
> > base mask: 0xffff, base value: 0xed45
> > field list: (f-xx 15 16)
>
> What I'm doing wrong?
>
> whole .cpu file is available here:
> https://github.com/b-s-a/binutils-gdb/tree/z80-cgen/cpu
>
> Best regards,
> Sergey Belyashov
>
next prev parent reply other threads:[~2020-03-24 21:20 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-23 21:44 Sergey Belyashov
2020-03-24 21:20 ` Sergey Belyashov [this message]
-- strict thread matches above, loose matches on Subject: below --
2020-02-21 14:51 Sergey Belyashov
2020-02-22 15:11 ` Frank Ch. Eigler
2020-02-22 19:19 ` Sergey Belyashov
2020-02-23 0:03 ` Frank Ch. Eigler
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