From: Alan Lehotsky <apl@alum.mit.edu>
To: cgen@sources.redhat.com
Subject: contemplating CGEN for VLIW architecture
Date: Wed, 20 Feb 2002 06:54:00 -0000 [thread overview]
Message-ID: <p04330100b89964fb3501@[192.168.1.254]> (raw)
I'm evaluating a possible port to a VLIW microsequencer (256 bit microword, 25 fields
per micro-instruction).
I guess the good news is that there's ONLY one instruction format :-)
Any experience out there with such a wide instruction? I remember seeing some patches a while back
to deal with instruction formats >> 32 bits.
I guess I'm also wondering if I can build an assembler that looks more like an expression language,
viz something like
REGA = REGB + REGC, if R7 > R8 jump FAIL, REGZ=0x100;
where commas separate the various micro-ops, and the expressions are from the minimal set of + - ^ | &
separated by white space, etc.
Or is gas ONLY going to work with a traditional
OPCODE OPERANDS,....
style?
Regards,
Al Lehotsky
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next reply other threads:[~2002-02-20 14:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-02-20 6:54 Alan Lehotsky [this message]
2002-02-20 6:59 ` matthew green
2002-02-20 8:01 ` John Healy
2002-02-20 7:59 ` Frank Ch. Eigler
2002-02-20 9:18 ` Doug Evans
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