contemplating CGEN for VLIW architecture

contemplating CGEN for VLIW architecture

[Alan Lehotsky]

I'm evaluating a possible port to a VLIW microsequencer (256 bit microword, 25 fields
per micro-instruction).  

I guess the good news is that there's ONLY one instruction format :-)

Any experience out there with such a wide instruction?  I remember seeing some patches a while back
to deal with instruction formats >> 32 bits.

I guess I'm also wondering if I can build an assembler that looks more like an expression language,
viz something like


	REGA = REGB + REGC,  if R7 > R8 jump FAIL, REGZ=0x100;

where commas separate the various micro-ops, and the expressions are from the minimal set of + - ^ | &
separated by white space, etc.

Or is gas ONLY going to work with a traditional

	OPCODE	OPERANDS,....

style?

Regards,
Al Lehotsky
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re: contemplating CGEN for VLIW architecture

[matthew green]

   I'm evaluating a possible port to a VLIW microsequencer (256 bit microword, 25 fields
   per micro-instruction).  
   
   I guess the good news is that there's ONLY one instruction format :-)
   
   Any experience out there with such a wide instruction?  I remember seeing some patches a while back
   to deal with instruction formats >> 32 bits.

cgen supports > 32 bits.  dunno how _much_ further but i think it should
work today...

   
   I guess I'm also wondering if I can build an assembler that looks more like an expression language,
   viz something like
   
   
   	REGA = REGB + REGC,  if R7 > R8 jump FAIL, REGZ=0x100;
   
   where commas separate the various micro-ops, and the expressions are from the minimal set of + - ^ | &
   separated by white space, etc.
   
   Or is gas ONLY going to work with a traditional
   
   	OPCODE	OPERANDS,....
   
   style?


last i looked, the guts of the generated gas really seemed to assume
the latter unfortunately.


.mrg.

Re: contemplating CGEN for VLIW architecture

[John Healy]

As far as I know, the issue is not that cgen can't handle instructions longer than 32 bits, but that all
decodable bits must be within the top 32 bits.   If I understand what is written below correctly, each
element in the VLIW bundle will be 25 bits long so in that respect, I think you'll be ok.

John



matthew green wrote:

>    I'm evaluating a possible port to a VLIW microsequencer (256 bit microword, 25 fields
>    per micro-instruction).
>
>    I guess the good news is that there's ONLY one instruction format :-)
>
>    Any experience out there with such a wide instruction?  I remember seeing some patches a while back
>    to deal with instruction formats >> 32 bits.
>
> cgen supports > 32 bits.  dunno how _much_ further but i think it should
> work today...
>
>
>    I guess I'm also wondering if I can build an assembler that looks more like an expression language,
>    viz something like
>
>
>         REGA = REGB + REGC,  if R7 > R8 jump FAIL, REGZ=0x100;
>
>    where commas separate the various micro-ops, and the expressions are from the minimal set of + - ^ | &
>    separated by white space, etc.
>
>    Or is gas ONLY going to work with a traditional
>
>         OPCODE  OPERANDS,....
>
>    style?
>
> last i looked, the guts of the generated gas really seemed to assume
> the latter unfortunately.
>
> .mrg.

Re: contemplating CGEN for VLIW architecture

[Frank Ch. Eigler]

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Hi -

On Wed, Feb 20, 2002 at 09:44:45AM -0500, Alan Lehotsky wrote:
> I'm evaluating a possible port to a VLIW microsequencer (256 bit
> microword, 25 fields per micro-instruction).  

It may be best to model this as a list of independent subinstructions,
one for each logical operation.  Let each have its own cgen isa tag.
(Let another layer take care of bitfield packing / unpacking.)

Otherwise, you might have to ask cgen to expand the cartesian product
of all possible opcode tuples, to come up with the total list of
cgen-level instructions.

(Let some other layer take care of bitwise packing / unpacking.)

The 32-bit limit you mention relates to something a little different:
the width of the bitmask used to identify a given single cgen instruction.
In this case, if you break up the VLIW word into N subinstructions, the
32-bit limit may end up not affecting you.


> I guess I'm also wondering if I can build an assembler that looks more
> like an expression language, viz something like
> 	REGA = REGB + REGC,  if R7 > R8 jump FAIL, REGZ=0x100;
> [...]

Mucho worko, amigo.


- FChE

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contemplating CGEN for VLIW architecture

[Doug Evans]

Alan Lehotsky writes:
 > I guess I'm also wondering if I can build an assembler that looks more like an expression language,
 > viz something like
 > 
 > 
 > 	REGA = REGB + REGC,  if R7 > R8 jump FAIL, REGZ=0x100;
 > 
 > where commas separate the various micro-ops, and the expressions are from the minimal set of + - ^ | &
 > separated by white space, etc.
 > 
 > Or is gas ONLY going to work with a traditional
 > 
 > 	OPCODE	OPERANDS,....
 > 
 > style?

Maybe write a separate language that converts one to the other?
Support "if R7 > R8 jump FAIL" on top,
and pass the result to gas which recognizes the "opcode operands,..." style.