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From: jerzy dyrda <>
To:, "Gian Maria" <>
Subject: Re: STM32F107 on STM3210C-EVAL
Date: Mon, 28 Mar 2011 10:47:00 -0000	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <23118906-1707f2ce17e92d08d3084915122281bc@pkn7.m5r2.onet>

Hello all,

On Monday 28 March 2011 11:51:45 wrote:
> There is only one thing left - the RCC differences. In RM there is a
> seperate section about RCC config for CL. But at the first look it seems
> that registers are compatible.
RCC registers are extended to support 2 extra PPL's with appropriate divider and multiplier.
Main differences is that source of PLL clock it isn't anymore taken directly from HSE or HSE/2 clock 
but it's introduced new divider PREDIV1 thus PLLSRC bit in RCC_CFGR register has partially 
different meaning. And another issue is external crystal. It value is 25MHz not 8 MHz like in 
STM3210E what causes need of using second PLL to produce CPU 72MHz.

HSE == 25MHz   /  PREDIV2 == 5 -> 5MHz   *  PLLMUL2 == 8 ->  
40MHz / PREDIV1 == 5 -> 8MHz * PLLMUL == 9 -> 72MHz = SYSCLK

It's looks ugly but above method it's used in ST source code for STM3210C evaluation board.

Best regards

  reply	other threads:[~2011-03-28 10:47 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-03-22 19:15 Gian Maria
2011-03-23 10:51 ` John Dallaway
2011-03-26 11:07   ` Ilija Kocho
2011-03-28  9:55 ` qber_
2011-03-28 10:47   ` jerzy dyrda [this message]
2011-03-28 19:13     ` R: " Gian Maria
2011-03-28 11:34   ` Ilija Kocho
2011-04-14 10:59   ` mlazcoz
2011-03-23 10:30 qber_

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