From: Rutger Hofman <rutger@cs.vu.nl>
To: Ross Younger <wry@ecoscentric.com>
Cc: Jonathan Larmour <jifl@jifvik.org>,
eCos developers <ecos-devel@ecos.sourceware.org>
Subject: Re: NAND technical review
Date: Wed, 07 Oct 2009 12:11:00 -0000 [thread overview]
Message-ID: <4ACC8640.6080605@cs.vu.nl> (raw)
In-Reply-To: <4ACB4B58.2040804@ecoscentric.com>
Ross Younger wrote:
[snip]
> Getting data into and out of the chip involves a simple protocol sequence.
>
> Commands are single bytes; addresses are sequences of a few bytes depending
> on the chip size and the operation invoked.
>
> For example, to read a page of data on the spec sheet I have to hand is:
> * Write 0x00 into the command latch
> * Write the four address bytes in turn into the address latch
> * Write 0x30 into the command latch
> * Chip signals Busy; wait for it to signal Ready
> * Read out (up to) 2112 bytes of data.
AFAIK, there are two kinds of chips on the market: Large-page chips (2K
data pages) and Small-page chips (512B pages). These speak a different
command language, but in their wiring they are the same. The large-page
chips are (nearly) ONFI-compliant, the Small-page chip command language
is different. Ancient chips aside, if a chip gives its Device Type Byte,
NAND flash code can look up in its tables what the chip parameters are
(page size, block size, number of blocks, 8 or 16 bit data bus, etc).
Miracle: Device Type Bytes are shared across manufacturers, so the table
is limited in size.
I saw an annoucement of 4K-page chips, but the datasheets are
confidential. Is there anybody who can comment on these?
> However, not all chips are quite the same. The ONFI initiative is an attempt
> to standardise chip protocols and most new chips should comply with it. A
> number of chips on the market are _nearly_ ONFI-compliant: deviations
> typically occur over the format of the ReadID response and that of an
> address. I believe that older chips did their own thing entirely.
[snip]
> 3. Driver model --------------------------------------------------------
>
> The major architectural difference between the two NAND layers is in their
> driver models and the degree of abstraction enforced.
>
> In Rutger's layer, controllers and chips are both formally abstracted. The
> application talks to the Abstract NAND Chip, which has (hard-coded) the
> basic sequences of commands, addresses and data required to talk to a NAND
> chip. This layer talks to a controller driver, which provides the nuts and
> bolts of reading and writing to the device. The chip driver is also called
> by the ANC layer, and provides the really chip-specific parts.
>
> The call flow looks something like this (best viewed in fixed-width font):
>
> Application --(H)-> ANC --(L)-> Controller driver
> \
> \-(C)-> Chip driver
The code attempts at both flexibility and code reuse. Its structure is
as follows:
Application --(H)-> ANC --(H2)-> Controller Common --(L)-> Controller
device-specific --(L)-> Chip
= ANC just wants to hide the presence of multiple controllers and
multiple chips, in any degree of heterogeneity.
= Controller Common implements the command languages for Large-page
chips and Small-page chips, does ECC generation/checking/repair. Its API
is much like the ANC's API: page_read, page_write, block_erase, but on a
specific controller+chip.
= Controller device-specific is (usually) the only part that must be
ported for a new controller/board/setup. Its API is in terms of the
commands described by Ross: push a command on the chip's bus, push/read
data on the chip's bus etc. The sample GPIO driver that I bundled shows
how little work can be involved in doing a port. I think that support
for hardware ECC of some controllers may add more to the device-specific
code than the command implementation!
= Chip has support for ONFI, Large-page, and Small page. Only for chips
that don't fit in these categories (and there will be museums that have
them) require writing a chip driver.
I realize that support for various chip and ECC types increases the
code. It will be trivial to add a few #ifdef's to disable unneeded code
for your configuration; the .cdl can specify what is needed (like: only
large-page 'regular' chips, which means: no small-page, no ONFI
interrogation).
[snip]
> - E's high-level driver interface makes it harder to add new functions
> later, necessitating a change to that API (H2 above). R's does not; the
> requisite logic would only need to be added to the ANC.
'ANC' should read: Controller Common code.
> ... (As a case in point, support
> for hardware ECC is currently work-in-progress within eCosCentric, and does
> require such a change, but now is not the right time to discuss that.)
Use of the hardware ECC support for R's BlackFin's on-board ECC was
included in R from the start. The interface between Common Controller
and device-specific controller code is designed to support this flexibly.
> It would perhaps be interesting to compare the complexities of drivers for
> the two models, but it's not readily apparent how we would do that fairly.
>
> Perhaps porting a driver from one NAND layer to the other would be a useful
> exercise, and would also allow us to compare code sizes. Any suggestions or
> (he says hopefully) volunteers? I've got a lot on my plate this month...
Yes, this would definitely be interesting. Would there be benefits in
R's attempts at ease-of-port and code reuse.
> (b) Availability of drivers
>
> R provides support for:
> - One board: BlackFin EZ-Kit BF548 (which is not in anoncvs?)
> - One chip: the ST Micro 0xG chip (large page, x8 and x16 present but
> presumably only tested on the x8 chip on the BlackFin board?)
Correction: any 'regular' chip, of which the ST Micro is an example.
I tested on my synth target with x8 and x16 chips, also different ones
in one 'board'. I tested with various page sizes, also different ones on
one 'board'.
> - A synthetic controller/chip package
> - A template for a GPIO-based controller (untested, intended as an example only)
>
> I seem to remember rumours of the existence of a driver for a further
> chip+board combination, but I haven't seen it.
See Jurgen Lambrecht's response.
[snip]
> 5. Works in progress -----------------------------------------------------
>
> I can of course only comment on eCosCentric's plans, but the following work
> is in the pipeline:
>
> * Expansion of the device interface to better allow efficient hardware ECC
> support (in progress)
> * Hardware ECC for the STM3210E board driver
> * Performance tuning of software ECC and of NAND low-level drivers
> * Partition addressing: make addressing relative to the start of the
> partition, once and for all
> * Simple raw NAND "filesystem" for use by RedBoot (see
> http://ecos.sourceware.org/ml/ecos-devel/2009-07/msg00004.html et seq; those
> are the latest public mails but not the latest version of my thinking, which
> I will update in due course)
> * More RedBoot NAND utility commands
> * Support for booting Linux off NAND and for sharing a (YAFFS) NAND-resident
> filesystem
> * Part-page read support (would provide a big speed-up to parts of YAFFS2
> inbandTags mode as needed by small-page devices like that on the STM3210E)
R is designed with support for hardware ECC in mind.
R has part-read and part-write support. One thing that has always
puzzled me is how this interacts with ECC. ECC often works on a complete
subpage, like 256 bytes on a 2KB page chip; then I understand. But what
if the read/write is not of such a subpage?
Rutger
next prev parent reply other threads:[~2009-10-07 12:11 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-02 15:51 Jonathan Larmour
2009-10-06 13:51 ` Ross Younger
2009-10-07 3:12 ` Jonathan Larmour
2009-10-07 16:22 ` Rutger Hofman
2009-10-08 7:15 ` Jürgen Lambrecht
2009-10-15 3:53 ` Jonathan Larmour
2009-10-15 11:54 ` Jürgen Lambrecht
2009-10-15 3:49 ` Jonathan Larmour
2009-10-15 14:36 ` Rutger Hofman
2009-10-16 1:32 ` Jonathan Larmour
2009-10-19 9:56 ` Ross Younger
2009-10-19 14:21 ` Rutger Hofman
2009-10-20 3:21 ` Jonathan Larmour
2009-10-20 12:19 ` Rutger Hofman
2009-10-21 1:45 ` Jonathan Larmour
2009-10-21 12:15 ` Rutger Hofman
2009-10-23 14:06 ` Jonathan Larmour
2009-10-23 15:25 ` Rutger Hofman
2009-10-23 18:03 ` Rutger Hofman
2009-10-27 20:02 ` Rutger Hofman
2009-11-10 7:03 ` Jonathan Larmour
2010-12-11 19:18 ` John Dallaway
2010-12-22 14:54 ` Rutger Hofman
2009-10-15 15:43 ` Rutger Hofman
[not found] ` <4ACDF868.7050706@ecoscentric.com>
2009-10-09 8:27 ` Ross Younger
2009-10-13 2:21 ` Jonathan Larmour
2009-10-13 13:35 ` Rutger Hofman
2009-10-16 4:04 ` Jonathan Larmour
2009-10-19 14:51 ` Rutger Hofman
2009-10-20 4:28 ` Jonathan Larmour
2009-10-07 9:40 ` Jürgen Lambrecht
2009-10-07 16:27 ` Rutger Hofman
2009-10-13 2:44 ` Jonathan Larmour
2009-10-13 6:35 ` Jürgen Lambrecht
2009-10-15 3:55 ` Jonathan Larmour
2009-10-13 12:59 ` Rutger Hofman
2009-10-15 4:41 ` Jonathan Larmour
2009-10-15 14:55 ` Rutger Hofman
2009-10-16 1:45 ` Jonathan Larmour
2009-10-19 10:53 ` Ross Younger
2009-10-20 1:40 ` Jonathan Larmour
2009-10-20 10:17 ` Ross Younger
2009-10-21 2:06 ` Jonathan Larmour
2009-10-22 10:05 ` Ross Younger
2009-11-10 5:15 ` Jonathan Larmour
2009-11-10 10:38 ` Ross Younger
2009-11-10 11:28 ` Ethernet over SPI driver for ENC424J600 Ilija Stanislevik
2009-11-10 12:16 ` Chris Holgate
2009-11-12 18:32 ` NAND technical review Ross Younger
2009-10-13 14:19 ` Rutger Hofman
2009-10-13 19:58 ` Lambrecht Jürgen
2009-10-07 12:11 ` Rutger Hofman [this message]
2009-10-08 12:31 ` Ross Younger
2009-10-08 8:16 ` Jürgen Lambrecht
2009-10-12 1:13 ` Jonathan Larmour
2009-10-16 7:29 ` Simon Kallweit
2009-10-16 13:53 ` Jonathan Larmour
2009-10-19 15:02 ` Rutger Hofman
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