* [ECOS] AT91 on EB55 DSR is started only once
2005-05-18 9:49 ` [ECOS] AT91 on EB55 DSR is started only once Marcel Ovidiu Achim
@ 2005-05-18 10:11 ` Marcel Ovidiu Achim
2005-05-19 4:25 ` Nick Garnett
1 sibling, 0 replies; 3+ messages in thread
From: Marcel Ovidiu Achim @ 2005-05-18 10:11 UTC (permalink / raw)
To: marcel.achim; +Cc: ecos-discuss, ecos-discuss
Dear all,
I am experiencing some weird behaviour when trying to setup a timer
interrupt on an EB55 board.
I attached the relevant code below.
What happens is that the DSR is started only once after init from main,
and then never again, although the
timer interrupt is shown to occur (on an ascilloscope).
By accident I discovered that this can be fixed if I insert the
following line in the DSR:
HAL_READ_UINT32( AT91_TC1 + AT91_TC_SR, i );
Although the read seems to have no impact of the content of the SR
register,
it seems to magically have the DSR activated again.
I could live fine with that, but then other external interrupts seem to
considerably bring down overall system performance.
What am I overseeing here? Can anyone please help?
Thanks,
void main() {
...
// Create interrupt for Timer3 with prio 10
cyg_interrupt_create(
CYGNUM_HAL_INTERRUPT_TIMER3,
10,
0,
Timer_ISR,
Timer_DSR,
&handle_timer_isr,
&isr
);
cyg_interrupt_attach(handle_timer_isr);
// AIC Source Mode Register. TC3 interupt on a positive edge of the
TC3 timer.
HAL_WRITE_UINT32( AT91_AIC + AT91_AIC_SMR9, AT91_AIC_SMR_EDGE_POS);
// AIC Source Mode Register. IRQ0 positive edge-triggerd
HAL_WRITE_UINT32( AT91_AIC + AT91_AIC_SMR29, AT91_AIC_SMR_EDGE_POS);
// AIC Source Mode Register. IRQ1 positive edge-triggerd
HAL_WRITE_UINT32( AT91_AIC + AT91_AIC_SMR28, 0x00000060);
//
// CLOCK CONFIGURATION
//
// Generate interrupt on RC compare
HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_IER, AT91_TC_IER_CPC);
// Fill RC register with a value
HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_RC, 0x00003FFF);
// TC command register. Set the frequency for the timer, enabel Wave
Mode and
// on RC compare reset the timer and start it again.
HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_CMR,
AT91_TC_CMR_CLKS_MCK2
| AT91_TC_CMR_WAVE
| AT91_TC_CMR_CPCTRG
| AT91_TC_CMR_ACPC_TOGGLE
);
// Enable and start the timer
HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_CCR, 0x01 + 0x04);
...
// Enable interrupts
cyg_interrupt_enable();
}
cyg_uint32 Timer_ISR(cyg_vector_t vector, cyg_addrword_t data)
{
// Block this interrupt from occurring until DSR completed
cyg_interrupt_mask (vector);
// Ack the interrupt so other routines can be serviced
cyg_interrupt_acknowledge(vector);
// Proceed to DSR
return CYG_ISR_CALL_DSR;
}
void Timer_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t
data)
{
int i=0;
if ( some_global_condition ) {
execute_code();
}
HAL_READ_UINT32( AT91_TC1 + AT91_TC_SR, i );
// Allow this interrupt to occur again
cyg_interrupt_unmask (vector);
}
--
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [ECOS] AT91 on EB55 DSR is started only once
2005-05-18 9:49 ` [ECOS] AT91 on EB55 DSR is started only once Marcel Ovidiu Achim
2005-05-18 10:11 ` Marcel Ovidiu Achim
@ 2005-05-19 4:25 ` Nick Garnett
1 sibling, 0 replies; 3+ messages in thread
From: Nick Garnett @ 2005-05-19 4:25 UTC (permalink / raw)
To: Marcel Ovidiu Achim; +Cc: ecos-discuss
Marcel Ovidiu Achim <marcel.achim@ovidius-ib.de> writes:
> Dear all,
>
> I am experiencing some weird behaviour when trying to setup a timer
> interrupt on an EB55 board.
> I attached the relevant code below.
> What happens is that the DSR is started only once after init from main,
> and then never again, although the
> timer interrupt is shown to occur (on an ascilloscope).
> By accident I discovered that this can be fixed if I insert the
> following line in the DSR:
>
> HAL_READ_UINT32( AT91_TC1 + AT91_TC_SR, i );
>
> Although the read seems to have no impact of the content of the SR
> register,
> it seems to magically have the DSR activated again.
The timers need the SR register to be read to clear the interrupt,
although this does not seem to be documented. Take a look at the code
in eCos that sets up timer0 to generate clock interrupts.
> I could live fine with that, but then other external interrupts seem to
> considerably bring down overall system performance.
> What am I overseeing here? Can anyone please help?
I'm afraid I cannot help with these other interrupts, but I doubt that
they have anything to do with your timer. Try turning on assertions
and find out where they are coming from.
--
Nick Garnett eCos Kernel Architect
http://www.ecoscentric.com The eCos and RedBoot experts
--
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
^ permalink raw reply [flat|nested] 3+ messages in thread