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From: bugzilla-daemon@bugs.ecos.sourceware.org
To: ecos-patches@ecos.sourceware.org
Subject: [Bug 1000910] New port: Ethernet over SPI driver for ENC424J600
Date: Thu, 17 Feb 2011 10:43:00 -0000	[thread overview]
Message-ID: <20110217104348.DFB962F78001@mail.ecoscentric.com> (raw)
In-Reply-To: <bug-1000910-104@http.bugs.ecos.sourceware.org/>

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Ilija Stanislevik <ilijas@siva.com.mk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Attachment #1033|0                           |1
        is obsolete|                            |

--- Comment #11 from Ilija Stanislevik <ilijas@siva.com.mk> 2011-02-17 10:43:46 GMT ---
Created an attachment (id=1132)
 --> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1132)
Patch to ecos.db, ChangeLog and STM3210eval HAL

STM3210e_eval HAL:

STM3210e_eval HAL defined resources used for SPI Ethernet driver are now
parented in SPI Ethernet driver.

User enters port and pin to which interrupt from SPI Ethernet controller is
connected. Default values are intentionally made unacceptable, so the user is
given a chance to think and enter data which match his hardware situation.

Interrupt vector is automatically calculated based on pin entered.

User can select to which of the STM32's SPI buses is connected the Ethernet
chip. Only the buses which are enabled in SPI driver are available for
selection. This option requires at least one SPI bus to be enabled. If none is
enabled, the "requires" mechanism automatically enables bus 1. I find this safe
enough because if there is only this SPI device in the system, it is highly
likely that it is connected to bus 1. If someone adds more SPI devices, or a
device to another SPI bus, he/she will be aware of the possibilities and will
enable and select correct buses. Using the same logic, the chip select number
defaults to 0 (indicating the first cs from the list defined in SPI driver),
which I made the lowest legal_value. I wasn't able to establish a hard upper
limit, so I put one which I deem fair enough.

SPI bus pin toggle rate is required to be 50MHz, which accommodates for
enc424j600's SPI 14MHZ rate.

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  parent reply	other threads:[~2011-02-17 10:43 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <bug-1000910-104@http.bugs.ecos.sourceware.org/>
2011-02-17  9:49 ` bugzilla-daemon
2011-02-17 10:43 ` bugzilla-daemon [this message]
2011-10-27 14:22 ` bugzilla-daemon
2011-10-27 14:41 ` bugzilla-daemon
2011-10-27 14:43 ` bugzilla-daemon
2012-04-02 20:21 ` bugzilla-daemon
2012-04-05  6:22 ` bugzilla-daemon
2012-04-05 15:52 ` bugzilla-daemon
2012-04-20  8:00 ` bugzilla-daemon
2012-04-20  8:07 ` bugzilla-daemon
2012-05-04 16:36 ` bugzilla-daemon
2012-05-04 16:37 ` bugzilla-daemon
2012-05-04 16:37 ` bugzilla-daemon
2012-05-04 16:38 ` bugzilla-daemon
2012-05-04 16:38 ` bugzilla-daemon
2012-05-04 16:39 ` bugzilla-daemon
2012-05-04 16:40 ` bugzilla-daemon
2012-05-07 16:43 ` bugzilla-daemon
2012-05-10 15:48 ` bugzilla-daemon

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