* [Bug 1001837] New: Rich FlexBus RAM layout
@ 2013-04-30 13:22 bugzilla-daemon
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Bug ID: 1001837
Summary: Rich FlexBus RAM layout
Product: eCos
Version: CVS
Target: freescale_twr_k60n512 (Freescale Kinetis TWR-K60N512)
Architecture/Host Cortex-M
OS:
Status: NEW
Severity: enhancement
Priority: low
Component: Patches and contributions
Assignee: unassigned@bugs.ecos.sourceware.org
Reporter: ilijak@siva.com.mk
CC: ecos-patches@ecos.sourceware.org
Created attachment 2219
--> http://bugs.ecos.sourceware.org/attachment.cgi?id=2219&action=edit
FlexBus RAM variant support.
Rich FlexBus RAM layout to thr FlexBus Ram provides similar properties like
ones for DDRAM with respect to caching. Memory is partitioned in 3 partitions:
Code, data and non-cached.
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--- Comment #1 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2220
--> http://bugs.ecos.sourceware.org/attachment.cgi?id=2220&action=edit
TWR-K60N512-FXM rich FlexBus RAM implementation.
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--- Comment #2 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2221
--> http://bugs.ecos.sourceware.org/attachment.cgi?id=2221&action=edit
A small patch to Micron PSRAM.
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Ilija Kocho <ilijak@siva.com.mk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #2219|0 |1
is obsolete| |
--- Comment #3 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2222
--> http://bugs.ecos.sourceware.org/attachment.cgi?id=2222&action=edit
FlexBus RAM variant support. 130502
I use opportunity to update FlexNVM configuration with 512KiB FlexNVM devices
found on K70FX512.
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Ilija Kocho <ilijak@siva.com.mk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #2220|0 |1
is obsolete| |
--- Comment #4 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2223
--> http://bugs.ecos.sourceware.org/attachment.cgi?id=2223&action=edit
TWR-K60N512-FXM rich FlexBus RAM implementation. 130502
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Mike Jones <mjones@linear.com> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |mjones@linear.com
--- Comment #5 from Mike Jones <mjones@linear.com> ---
I am trying to understand the memory layout. It appears that:
0x60C00000 Non-Cached Data RAM 4MB
0x60400000 Cached Data RAM 8MB
0x60000000 Code RAM 4MB
Stacks seem to be in the middle one, because a variable on the stack is at
0x604008D8. This is the variable getting corrupted as discussed in #101764, the
MMC/SPI patch.
From CDL comments, it appears you can't DMA to cached data. If the SPI driver
uses DMA, I believe it will DMA to arrays on the stack in the cached area.
Do you think this could be the source of my SPI problems that only occur on
FXM? That DMA to the stack area is messing up the stack leading to the bad
address pointers.
Is there a way to disable this cache?
There is a value CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP, but I am guessing that is
not for the 8MB cached data.
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--- Comment #6 from Ilija Kocho <ilijak@siva.com.mk> ---
Hi Mike
(In reply to comment #5)
The current CVS version of FlexBus memory is not partitioned so it is all
either cached or non cached. Here I apply partitioning scheme that was
developed for DDRAM (Bug 1001606). This support is generic, it works on all
Kinetis devices with FlexBus but caching schemes effectively apply only on
devices with on-chip cache. At present only K70 and 120/150MHz K60 lines have
cache.
> I am trying to understand the memory layout. It appears that:
>
> 0x60C00000 Non-Cached Data RAM 4MB
> 0x60400000 Cached Data RAM 8MB
> 0x60000000 Code RAM 4MB
>
> Stacks seem to be in the middle one, because a variable on the stack is at
> 0x604008D8.
All data, for Platform startup types that employ FXM normally resides in the
middle partition: stack, static, global, heap.
Code for RAM startup resides in "Code RAM".
> This is the variable getting corrupted as discussed in #101764,
> the MMC/SPI patch.
>
I assume you are still with 100MHz K60 which hasn't cache.
> From CDL comments, it appears you can't DMA to cached data.
Not necessarily. You can DMA but then you must sync/invalidate cache lines on
every transaction. Non-cached memory is a convenience when you have freedom
where to store the buffers.
> If the SPI
> driver uses DMA, I believe it will DMA to arrays on the stack in the cached
> area.
With current drivers employing eDMA (that'd DSPI) the Transfer Control
Descriptors (TCD) must not be in cached memory. For performance reasons best
place is internal SRAM. On TWR-K60N512-FXM with the old scheme they reside in
FXM because CYGHWR_HAL_NONCACHED is not active unless system has cache memory
(which is fixed with this bug). However, assuming that you have 100MHz K60 this
will not break your code and will only affect SPI/MMC performance. Besides
TCDs, the DSPI driver has internal transmit buffer which also must not be
cached. There are no other limitations regarding caching.
>
> Do you think this could be the source of my SPI problems that only occur on
> FXM? That DMA to the stack area is messing up the stack leading to the bad
> address pointers.
Having in mind previous consideration the cache should be excluded as
non-existent. But if you are using stack (AKA automatic variables) for buffers
it very likely may be the problem.
>
> Is there a way to disable this cache?
> There is a value CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP, but I am guessing that
> is not for the 8MB cached data.
Yes it is, (provided that you have one). Here is the scheme:
Partition | Cache control
-----------------------------------+------------------------------------
0x60C00000 Non-Cached Data RAM 4MB | non applicable
0x60400000 Cached Data RAM 8MB | CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
0x60000000 Code RAM 4MB | CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
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--- Comment #7 from Mike Jones <mjones@linear.com> ---
I assume from Ilija's comments that DMA bypasses the cache, hence the need to
invalidate it.
When I disable CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP, I get a conflict saying
startup mode must be WRITETHRU, which it is , but is also disabled (conflict
comes from CYGPKG_HAL_FREESCALE_EDMA). Perhaps this is a bug. My purpose in
disabling it to make it consistent with the 100Mhz device's behavior, and make
sure there is no side effect from enabling a feature the device does not
support. The conflict did not prevent my app from running.
I assume the TCD limitation is because the eDMA logic in the device is
connected tightly with the memory bus logic and can't route through the cache,
similar to how DMA works directly on memory without the cache.
I put breakpoints in the SPI dma setup to see where the buffers reside in
memory and they reside in Cache Data RAM just above 0x60400000. I will attach a
couple of screen shots with the location. I assume some code will need to be
added to invalidate the cache if the code is not already present somewhere,
move to another segment without cache, or require turning off caching. Perhaps
someone knows if there is cache invalidation code already. For now, I am ok
because there is no caching for my 100Mhz device.
I believe that whatever is overwriting the device variable is not related to
FXM based on what I learned here. There is also evidence that the stack is
corrupt in other places because the debugger is not giving a complete stack
trace. So I will take the discussion back to the MCC/SPI bug if I discover
more.
Thanks
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--- Comment #8 from Mike Jones <mjones@linear.com> ---
Created attachment 2224
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SPI rx data_buf
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--- Comment #9 from Mike Jones <mjones@linear.com> ---
Created attachment 2225
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SPI tx data_buf on stack
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Mike Jones <mjones@linear.com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #2224|SPI rx data_buf |SPI rx data_buf on stack
description| |
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--- Comment #10 from Mike Jones <mjones@linear.com> ---
Ilija,
I have one more question on FXD. Do we know for sure if the refresh spec is met
for the default configuration under all patterns of memory access?
Is there a setting that would eliminate this as a potential source of problems
so that I can run my app that way and see if my problem goes away?
Mike
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--- Comment #11 from Ilija Kocho <ilijak@siva.com.mk> ---
(In reply to comment #7)
[snip]
>
> When I disable CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP, I get a conflict saying
> startup mode must be WRITETHRU, which it is , but is also disabled (conflict
> comes from CYGPKG_HAL_FREESCALE_EDMA). Perhaps this is a bug.
This is a bug indeed and I am going to fix it. Can you please open a dedicated
bug?
[snip]
Thanks
Ilija
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--- Comment #12 from Ilija Kocho <ilijak@siva.com.mk> ---
(In reply to comment #7)
> I assume from Ilija's comments that DMA bypasses the cache, hence the need
> to invalidate it.
>
[snip]
> I assume the TCD limitation is because the eDMA logic in the device is
> connected tightly with the memory bus logic and can't route through the
> cache, similar to how DMA works directly on memory without the cache.
eDMA has no access to cache, but the problem could be (also) solved with cache
synchronisation/invalidation. However, it would require extra CPU time and
since TCD typically occupy little memory (even cumulative), for best
performance I have chosen to put them in SRAM [by default].
Same discussion applies to Ethernet buffer descriptors.
[snip]
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--- Comment #13 from Mike Jones <mjones@linear.com> ---
I did not see a CDL item for SPI TCD location. Where do I find it?
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--- Comment #14 from Ilija Kocho <ilijak@siva.com.mk> ---
(In reply to comment #10)
> Ilija,
>
> I have one more question on FXD. Do we know for sure if the refresh spec is
> met for the default configuration under all patterns of memory access?
I haven't performed any verification myself, but I haven't experienced hardware
problems with current settings.
>
> Is there a setting that would eliminate this as a potential source of
> problems so that I can run my app that way and see if my problem goes away?
If you are willing to play with FlexBus/RAM settings you have CDL controls for
FlexBus and Micron PSRAM registers. Look for /Chip select 0/ and /External
memory devices/ under /FlexBus/
Ilija
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--- Comment #15 from Ilija Kocho <ilijak@siva.com.mk> ---
(In reply to comment #13)
> I did not see a CDL item for SPI TCD location. Where do I find it?
Look under /Non cachable/ or /Non cached/ RAM memory regions.
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--- Comment #16 from Mike Jones <mjones@linear.com> ---
Created attachment 2227
--> http://bugs.ecos.sourceware.org/attachment.cgi?id=2227&action=edit
FXM Specific Exception
This test case will generate an exception on FXM hardware that cannot be
generated on non-FXM hardware. It manifests like the description in Bug 1001764
- Enhancement of MMC/SD over SPI driver. The zip contains an ecm file, code,
and all patches used.
When the application is run, a loop will open a file on an SD card, develop
strings with snprintf, write them to the file, flush the filesystem, and close
the file. When it is run, the problem always occurs when the variable "dev" in
the SPI code is 0xFFFFFFFF and results in an exception 5. It has to be run for
many minutes to cause failure, but typically it will fail in less than 10 mins.
Ilija,
If you have time to run this, it might eliminate or confirm if the problem is
related/unrelated to hardware reliability. Once we know it is not related to
bad hardware, perhaps we can form some theories about the cause of the
exception.
Please note that all I2C code is commented out, so this only uses FXM and SD
card and should run on any FXM hardware with SD support. I ran it on a K60
100Mhz, so there is no cache. I have disabled the cache in the ecm as well.
I put the attachment here rather than the SPI bug because I cannot reproduce it
on non-FXM hardware. If it really is a MMC bug, we can move it.
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--- Comment #17 from Mike Jones <mjones@linear.com> ---
The MMC problem was narrowed down to a problem with MMC/SPI DMA and FXM.
Disabling DMA works around the problem.
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From: bugzilla-daemon @ 2013-05-18 19:14 UTC (permalink / raw)
To: ecos-patches
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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001837
--- Comment #18 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2236
--> http://bugs.ecos.sourceware.org/attachment.cgi?id=2236&action=edit
TWR-K60N512-FXM rich FlexBus RAM add on 130518 incremental to 2223
This patch adds requirement for FXM memory for TWR-K60N512-FXM when necessary.
Incremental to Attachment 2223.
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* [Bug 1001837] Rich FlexBus RAM layout
2013-04-30 13:22 [Bug 1001837] New: Rich FlexBus RAM layout bugzilla-daemon
` (18 preceding siblings ...)
2013-05-18 19:14 ` bugzilla-daemon
@ 2013-06-01 22:46 ` bugzilla-daemon
2013-06-01 22:50 ` bugzilla-daemon
` (2 subsequent siblings)
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From: bugzilla-daemon @ 2013-06-01 22:46 UTC (permalink / raw)
To: ecos-patches
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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001837
Ilija Kocho <ilijak@siva.com.mk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #2222|0 |1
is obsolete| |
Attachment #2224|0 |1
is obsolete| |
Attachment #2225|0 |1
is obsolete| |
Attachment #2227|0 |1
is obsolete| |
--- Comment #19 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2245
--> http://bugs.ecos.sourceware.org/attachment.cgi?id=2245&action=edit
FlexBus RAM variant support. 130602
Synchronised with attachment 2244 to bug 1001815.
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* [Bug 1001837] Rich FlexBus RAM layout
2013-04-30 13:22 [Bug 1001837] New: Rich FlexBus RAM layout bugzilla-daemon
` (19 preceding siblings ...)
2013-06-01 22:46 ` bugzilla-daemon
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2013-06-01 22:54 ` bugzilla-daemon
2013-06-02 17:12 ` bugzilla-daemon
22 siblings, 0 replies; 24+ messages in thread
From: bugzilla-daemon @ 2013-06-01 22:50 UTC (permalink / raw)
To: ecos-patches
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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001837
Ilija Kocho <ilijak@siva.com.mk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #2223|0 |1
is obsolete| |
Attachment #2236|0 |1
is obsolete| |
--- Comment #20 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2246
--> http://bugs.ecos.sourceware.org/attachment.cgi?id=2246&action=edit
TWR-K60N512-FXM rich FlexBus RAM implementation. 130602
Synchronised with attachment 2245.
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* [Bug 1001837] Rich FlexBus RAM layout
2013-04-30 13:22 [Bug 1001837] New: Rich FlexBus RAM layout bugzilla-daemon
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2013-06-01 22:50 ` bugzilla-daemon
@ 2013-06-01 22:54 ` bugzilla-daemon
2013-06-02 17:12 ` bugzilla-daemon
22 siblings, 0 replies; 24+ messages in thread
From: bugzilla-daemon @ 2013-06-01 22:54 UTC (permalink / raw)
To: ecos-patches
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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001837
--- Comment #21 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2247
--> http://bugs.ecos.sourceware.org/attachment.cgi?id=2247&action=edit
TWR-K70F120M enforce WRITETHRU caching when DMA is used.
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* [Bug 1001837] Rich FlexBus RAM layout
2013-04-30 13:22 [Bug 1001837] New: Rich FlexBus RAM layout bugzilla-daemon
` (21 preceding siblings ...)
2013-06-01 22:54 ` bugzilla-daemon
@ 2013-06-02 17:12 ` bugzilla-daemon
22 siblings, 0 replies; 24+ messages in thread
From: bugzilla-daemon @ 2013-06-02 17:12 UTC (permalink / raw)
To: ecos-patches
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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001837
Ilija Kocho <ilijak@siva.com.mk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |RESOLVED
Resolution|--- |CURRENTRELEASE
--- Comment #22 from Ilija Kocho <ilijak@siva.com.mk> ---
Checked in.
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