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* [Bug target/102218] New: 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm
@ 2021-09-06 14:29 tnfchris at gcc dot gnu.org
2022-05-26 11:01 ` [Bug target/102218] " tnfchris at gcc dot gnu.org
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: tnfchris at gcc dot gnu.org @ 2021-09-06 14:29 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102218
Bug ID: 102218
Summary: 128-bit atomic compare and exchange does not honor
memory model on AArch64 and Arm
Product: gcc
Version: 9.0
Status: UNCONFIRMED
Keywords: wrong-code
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: tnfchris at gcc dot gnu.org
Target Milestone: ---
AArch64 and Arm libatomic do no support 128-bit atomics and so use the pthreads
fallback code on atomic operations.
The fallback code for atomic compare and exchange does the following
pre_seq_barrier (smodel);
magic = protect_start (mptr);
and for correctness relies on the target implementing pre_seq_barrier.
AArch64 and Arm however do not provide an implementation or pre_seq_barrier and
post_seq_barrier and the default implementations are just empty functions:
static inline void __attribute__((always_inline, artificial))
pre_seq_barrier(int model)
{
}
However for correctness on __ATOMIC_SEQ_CST a barrier needs to be emitted here
which isn't happening on any GCC version.
^ permalink raw reply [flat|nested] 6+ messages in thread* [Bug target/102218] 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm 2021-09-06 14:29 [Bug target/102218] New: 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm tnfchris at gcc dot gnu.org @ 2022-05-26 11:01 ` tnfchris at gcc dot gnu.org 2022-08-08 13:38 ` cvs-commit at gcc dot gnu.org ` (3 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: tnfchris at gcc dot gnu.org @ 2022-05-26 11:01 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102218 Tamar Christina <tnfchris at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Ever confirmed|0 |1 Last reconfirmed| |2022-05-26 Status|UNCONFIRMED |ASSIGNED Assignee|unassigned at gcc dot gnu.org |tnfchris at gcc dot gnu.org ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/102218] 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm 2021-09-06 14:29 [Bug target/102218] New: 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm tnfchris at gcc dot gnu.org 2022-05-26 11:01 ` [Bug target/102218] " tnfchris at gcc dot gnu.org @ 2022-08-08 13:38 ` cvs-commit at gcc dot gnu.org 2022-08-08 13:38 ` cvs-commit at gcc dot gnu.org ` (2 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: cvs-commit at gcc dot gnu.org @ 2022-08-08 13:38 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102218 --- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Tamar Christina <tnfchris@gcc.gnu.org>: https://gcc.gnu.org/g:e6a8ae900b4141bbce1451da8f173d441662782d commit r13-1988-ge6a8ae900b4141bbce1451da8f173d441662782d Author: Tamar Christina <tamar.christina@arm.com> Date: Mon Aug 8 14:37:00 2022 +0100 AArch64: Fix 128-bit sequential consistency atomic operations. The AArch64 implementation of 128-bit atomics is broken. For 128-bit atomics we rely on pthread barriers to correct guard the address in the pointer to get correct memory ordering. However for 128-bit atomics the address under the lock is different from the original pointer. This means that one of the values under the atomic operation is not protected properly and so we fail during when the user has requested sequential consistency as there's no barrier to enforce this requirement. As such users have resorted to adding an #ifdef GCC <emit barrier> #endif around the use of these atomics. This corrects the issue by issuing a barrier only when __ATOMIC_SEQ_CST was requested. To remedy this performance hit I think we should revisit using a similar approach to out-line-atomics for the 128-bit atomics. Note that I believe I need the empty file due to the include_next chain but I am not entirely sure. I have hand verified that the barriers are inserted for atomic seq cst. libatomic/ChangeLog: PR target/102218 * config/aarch64/aarch64-config.h: New file. * config/aarch64/host-config.h: New file. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/102218] 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm 2021-09-06 14:29 [Bug target/102218] New: 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm tnfchris at gcc dot gnu.org 2022-05-26 11:01 ` [Bug target/102218] " tnfchris at gcc dot gnu.org 2022-08-08 13:38 ` cvs-commit at gcc dot gnu.org @ 2022-08-08 13:38 ` cvs-commit at gcc dot gnu.org 2022-12-20 10:45 ` ktkachov at gcc dot gnu.org 2022-12-21 9:51 ` tnfchris at gcc dot gnu.org 4 siblings, 0 replies; 6+ messages in thread From: cvs-commit at gcc dot gnu.org @ 2022-08-08 13:38 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102218 --- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Tamar Christina <tnfchris@gcc.gnu.org>: https://gcc.gnu.org/g:5471f55f001af412e1125b04972ebaab9d4f7337 commit r13-1989-g5471f55f001af412e1125b04972ebaab9d4f7337 Author: Tamar Christina <tamar.christina@arm.com> Date: Mon Aug 8 14:37:42 2022 +0100 AArch32: Fix 128-bit sequential consistency atomic operations. Similar to AArch64 the Arm implementation of 128-bit atomics is broken. For 128-bit atomics we rely on pthread barriers to correct guard the address in the pointer to get correct memory ordering. However for 128-bit atomics the address under the lock is different from the original pointer. This means that one of the values under the atomic operation is not protected properly and so we fail during when the user has requested sequential consistency as there's no barrier to enforce this requirement. As such users have resorted to adding an #ifdef GCC <emit barrier> #endif around the use of these atomics. This corrects the issue by issuing a barrier only when __ATOMIC_SEQ_CST was requested. I have hand verified that the barriers are inserted for atomic seq cst. libatomic/ChangeLog: PR target/102218 * config/arm/host-config.h (pre_seq_barrier, post_seq_barrier, pre_post_seq_barrier): Require barrier on __ATOMIC_SEQ_CST. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/102218] 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm 2021-09-06 14:29 [Bug target/102218] New: 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm tnfchris at gcc dot gnu.org ` (2 preceding siblings ...) 2022-08-08 13:38 ` cvs-commit at gcc dot gnu.org @ 2022-12-20 10:45 ` ktkachov at gcc dot gnu.org 2022-12-21 9:51 ` tnfchris at gcc dot gnu.org 4 siblings, 0 replies; 6+ messages in thread From: ktkachov at gcc dot gnu.org @ 2022-12-20 10:45 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102218 ktkachov at gcc dot gnu.org changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |ktkachov at gcc dot gnu.org --- Comment #3 from ktkachov at gcc dot gnu.org --- Does this need to be backported to other release versions as it's a wrong-code bug? ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/102218] 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm 2021-09-06 14:29 [Bug target/102218] New: 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm tnfchris at gcc dot gnu.org ` (3 preceding siblings ...) 2022-12-20 10:45 ` ktkachov at gcc dot gnu.org @ 2022-12-21 9:51 ` tnfchris at gcc dot gnu.org 4 siblings, 0 replies; 6+ messages in thread From: tnfchris at gcc dot gnu.org @ 2022-12-21 9:51 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102218 --- Comment #4 from Tamar Christina <tnfchris at gcc dot gnu.org> --- (In reply to ktkachov from comment #3) > Does this need to be backported to other release versions as it's a > wrong-code bug? Yes Ideally. I did ask for backport but was only approved for master. ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-12-21 9:51 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-09-06 14:29 [Bug target/102218] New: 128-bit atomic compare and exchange does not honor memory model on AArch64 and Arm tnfchris at gcc dot gnu.org 2022-05-26 11:01 ` [Bug target/102218] " tnfchris at gcc dot gnu.org 2022-08-08 13:38 ` cvs-commit at gcc dot gnu.org 2022-08-08 13:38 ` cvs-commit at gcc dot gnu.org 2022-12-20 10:45 ` ktkachov at gcc dot gnu.org 2022-12-21 9:51 ` tnfchris at gcc dot gnu.org
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