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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/103861] [i386] vectorize v2qi vectors
Date: Tue, 11 Jan 2022 18:24:10 +0000	[thread overview]
Message-ID: <bug-103861-4-ZgaRk51ym3@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-103861-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103861

--- Comment #11 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:820ac79e8448ad6c631e1387ba51a93dcf2b4e89

commit r12-6488-g820ac79e8448ad6c631e1387ba51a93dcf2b4e89
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Tue Jan 11 19:23:15 2022 +0100

    i386: Introduce V2QImode vector cmove for -msse4.1 [PR103861]

    This patch also moves V2HI and V4QImode vector conditional moves
    to SSE4.1 targets.  Vector cmoves are implemented with SSE logic functions
    without -msse4.1, and they are hardly worthwile for narrow vector modes.
    More important, we would like to keep vector logic functions for GPR
    registers, and the current RTX description of 32-bit vector modes logic
    insns does not include the necessary CC reg clobber.  Solve these issues by
    restricting vector cmove insns for these modes to -msse4.1, where logic
    instructions are avoided, and pblend insn is used instead.

    A follow-up patch will add clobbers and necessary splits to 32-bit
    vector mode logic insns, and in a future patch, ix86_sse_movcc will be
    improved to use expand_simple_{unop,binop} to emit logic insns, allowing
    us to re-enable 16-bit and 32-bit narrow vector cmoves for -msse2.

    2022-01-11  Uroš Bizjak  <ubizjak@gmail.com>

    gcc/ChangeLog:

            PR target/103861
            * config/i386/mmx.md (vcond<mode><mode>):
            Use VI_16_32 mode iterator.  Enable for TARGET_SSE4_1.
            (vcondu<mode><mode>): Ditto.
            (vcond_mask_<mode><mode>): Ditto.
            (mmx_pblendvb_v8qi): Rename from mmx_pblendvb64.
            (mmx_pblendvb_<mode>): Rename from mmx_pblendvb32.
            Use VI_16_32 mode iterator.
            * config/i386/i386-expand.c (ix86_expand_sse_movcc):
            Update for rename.  Handle V2QImode.
            (expand_vec_perm_blend): Update for rename.

    gcc/testsuite/ChangeLog:

            PR target/103861
            * g++.target/i386/pr100637-1b.C (dg-options):
            Use -msse4 instead of -msse2.
            * g++.target/i386/pr100637-1w.C (dg-options): Ditto.
            * g++.target/i386/pr103861-1.C: New test.
            * gcc.target/i386/pr100637-4b.c (dg-options):
            Use -msse4 instead of -msse2.
            * gcc.target/i386/pr103861-4.c: New test.

  parent reply	other threads:[~2022-01-11 18:24 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-29 18:09 [Bug target/103861] New: " ubizjak at gmail dot com
2021-12-29 18:13 ` [Bug target/103861] " ubizjak at gmail dot com
2021-12-29 18:15 ` ubizjak at gmail dot com
2021-12-29 18:21 ` ubizjak at gmail dot com
2021-12-29 20:36 ` pinskia at gcc dot gnu.org
2022-01-02 20:13 ` cvs-commit at gcc dot gnu.org
2022-01-04 13:59 ` rguenth at gcc dot gnu.org
2022-01-04 14:14 ` ubizjak at gmail dot com
2022-01-04 18:44 ` cvs-commit at gcc dot gnu.org
2022-01-05 22:17 ` cvs-commit at gcc dot gnu.org
2022-01-10 20:00 ` cvs-commit at gcc dot gnu.org
2022-01-11 18:24 ` cvs-commit at gcc dot gnu.org [this message]
2022-01-12 19:03 ` cvs-commit at gcc dot gnu.org
2022-01-13 19:49 ` cvs-commit at gcc dot gnu.org
2023-10-27  3:28 ` cvs-commit at gcc dot gnu.org

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