[Bug middle-end/103870] New: ARM: Wrong branch instruction with optimization O2 and higher

[Bug middle-end/103870] New: ARM: Wrong branch instruction with optimization O2 and higher

[petro.karashchenko at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103870

            Bug ID: 103870
           Summary: ARM: Wrong branch instruction with optimization O2 and
                    higher
           Product: gcc
           Version: 10.3.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: petro.karashchenko at gmail dot com
  Target Milestone: ---

Code test.c:

void f(void)
{
  double a = 2.2204460492503131e-16;
  int b = 1;
  int c = 0;

  while (a > 0)
  {
    if (++c >= 10)
    {
      b *= 2;
      c = 0;
    }

    if (b > 1)
    {
      a *= b;
    }
  }
}
----------
arm-none-eabi-gcc -save-temps -Wall -Wextra -c -march=armv7e-m -mtune=cortex-m7
-mthumb -mfpu=fpv5-d16 -mfloat-abi=hard test.c -O0
----------
Generated assembly:
        .arch armv7e-m
        .fpu fpv5-d16
        .eabi_attribute 28, 1
        .eabi_attribute 20, 1
        .eabi_attribute 21, 1
        .eabi_attribute 23, 3
        .eabi_attribute 24, 1
        .eabi_attribute 25, 1
        .eabi_attribute 26, 1
        .eabi_attribute 30, 6
        .eabi_attribute 34, 1
        .eabi_attribute 18, 4
        .file   "test2.c"
        .text
        .align  1
        .global f
        .syntax unified
        .thumb
        .thumb_func
        .type   f, %function
f:
        @ args = 0, pretend = 0, frame = 16
        @ frame_needed = 1, uses_anonymous_args = 0
        @ link register save eliminated.
        push    {r7}
        sub     sp, sp, #20
        add     r7, sp, #0
        mov     r2, #0
        ldr     r3, .L5
        strd    r2, [r7, #8]
        movs    r3, #1
        str     r3, [r7, #4]
        movs    r3, #0
        str     r3, [r7]
        b       .L2
.L4:
        ldr     r3, [r7]
        adds    r3, r3, #1
        str     r3, [r7]
        ldr     r3, [r7]
        cmp     r3, #9
        ble     .L3
        ldr     r3, [r7, #4]
        lsls    r3, r3, #1
        str     r3, [r7, #4]
        movs    r3, #0
        str     r3, [r7]
.L3:
        ldr     r3, [r7, #4]
        cmp     r3, #1
        ble     .L2
        ldr     r3, [r7, #4]
        vmov    s15, r3 @ int
        vcvt.f64.s32    d7, s15
        vldr.64 d6, [r7, #8]
        vmul.f64        d7, d6, d7
        vstr.64 d7, [r7, #8]
.L2:
        vldr.64 d7, [r7, #8]
        vcmpe.f64       d7, #0
        vmrs    APSR_nzcv, FPSCR
        bgt     .L4
        nop
        nop
        adds    r7, r7, #20
        mov     sp, r7
        @ sp needed
        ldr     r7, [sp], #4
        bx      lr
.L6:
        .align  2
.L5:
        .word   1018167296
        .size   f, .-f
        .ident  "GCC: (GNU Arm Embedded Toolchain 10.3-2021.10) 10.3.1 20210824
(release)"
----------
arm-none-eabi-gcc -save-temps -Wall -Wextra -c -march=armv7e-m -mtune=cortex-m7
-mthumb -mfpu=fpv5-d16 -mfloat-abi=hard test.c -Os
----------
Generated assembly:
        .arch armv7e-m
        .fpu fpv5-d16
        .eabi_attribute 28, 1
        .eabi_attribute 20, 1
        .eabi_attribute 21, 1
        .eabi_attribute 23, 3
        .eabi_attribute 24, 1
        .eabi_attribute 25, 1
        .eabi_attribute 26, 1
        .eabi_attribute 30, 4
        .eabi_attribute 34, 1
        .eabi_attribute 18, 4
        .file   "test2.c"
        .text
        .align  1
        .global f
        .syntax unified
        .thumb
        .thumb_func
        .type   f, %function
f:
        @ args = 0, pretend = 0, frame = 0
        @ frame_needed = 0, uses_anonymous_args = 0
        @ link register save eliminated.
        vldr.64 d7, .L10
        movs    r3, #0
        movs    r2, #1
.L5:
        adds    r3, r3, #1
        cmp     r3, #9
        ble     .L2
        lsls    r2, r2, #1
        movs    r3, #0
.L3:
        vmov    s13, r2 @ int
        vcvt.f64.s32    d6, s13
        vmul.f64        d7, d7, d6
        b       .L4
.L2:
        cmp     r2, #1
        bne     .L3
.L4:
        vcmpe.f64       d7, #0
        vmrs    APSR_nzcv, FPSCR
        bgt     .L5
        bx      lr
.L11:
        .align  3
.L10:
        .word   0
        .word   1018167296
        .size   f, .-f
        .ident  "GCC: (GNU Arm Embedded Toolchain 10.3-2021.10) 10.3.1 20210824
(release)"
----------

The problem appears with condition "if (b > 1)". If -O0 is applied then code
        ldr     r3, [r7, #4]
        cmp     r3, #1
        ble     .L2
is generate that "ble" instruction code is used, however with -Os we are
getting
        cmp     r2, #1
        bne     .L3
code generated that use "bne" instruction code. The case is that with code
above "b *= 2;" at some point "b" overflows and becomes equal to zero. The
"ble" instruction code will catch this however "bne" will not. So usage of
"bne" is inappropriate for "if (b > 1)" condition that is intended to truncate
negative values and zero.

[Bug middle-end/103870] ARM: Wrong branch instruction with optimization O2 and higher

[petro.karashchenko at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103870

--- Comment #1 from Petro Karashchenko <petro.karashchenko at gmail dot com> ---
I would expect "bgt" instruction instead of "bne" in such case.

[Bug middle-end/103870] ARM: Wrong branch instruction with optimization O2 and higher

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103870

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |INVALID

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Use either -fwrapv or have the math done as unsigned int so you can detect
signed integer overflow (which is undefined). You could also use builtins too.