[Bug target/104921] New: aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[Bug target/104921] New: aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921

            Bug ID: 104921
           Summary: aarch64: Assembler failure with vbfmlalbq_lane_f32
                    intrinsic
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: acoplan at gcc dot gnu.org
  Target Milestone: ---

The following fails:

$ cat t.c
#include <arm_neon.h>
float32x4_t
foo(float32x4_t x, bfloat16x8_t a, bfloat16x4_t b)
{
    asm("" ::: "v0", "v1", "v2", "v3", "v4", "v5");
    return vbfmlalbq_lane_f32 (x, a, b, 0);
}
$ ./aarch64-linux-gnu-gcc -c t.c -O2 -march=armv8.2-a+bf16
/tmp/ccwCbu7Y.s: Assembler messages:
/tmp/ccwCbu7Y.s:15: Error: register number out of range 0 to 15 at operand 3 --
`bfmlalb v0.4s,v7.8h,v16.h[0]'

it looks like the problem exists since the intrinsic was added in GCC 10.

[Bug target/104921] aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2022-12-09

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.

[Bug target/104921] aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(define_insn "aarch64_bfmlal<bt>_lane<q>v4sf"
  [(set (match_operand:V4SF 0 "register_operand" "=w")
        (plus: V4SF (match_operand:V4SF 1 "register_operand" "0")
                    (unspec:V4SF [(match_operand:V8BF 2 "register_operand" "w")
                                  (match_operand:VBF 3 "register_operand" "w")
                                  (match_operand:SI 4 "const_int_operand" "n")]
                     BF_MLA)))]
  "TARGET_BF16_SIMD"
{
  operands[4] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[4]));
  return "bfmlal<bt>\\t%0.4s, %2.8h, %3.h[%4]";
}
  [(set_attr "type" "neon_fp_mla_s_scalar_q")]
)


Operand 3 should have be:
(match_operand:VBF 3 "register_operand" "x")

[Bug target/104921] aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The following patterns has the same problem too:
(define_insn "aarch64_bfdot_lane<VBF:isquadop><VDQSF:mode>"
  [(set (match_operand:VDQSF 0 "register_operand" "=w")
        (plus:VDQSF
          (unspec:VDQSF
           [(match_operand:<VDQSF:VBFMLA_W> 2 "register_operand" "w")
            (match_operand:VBF 3 "register_operand" "w")
            (match_operand:SI 4 "const_int_operand" "n")]
            UNSPEC_BFDOT)
          (match_operand:VDQSF 1 "register_operand" "0")))]
  "TARGET_BF16_SIMD"
{
  int nunits = GET_MODE_NUNITS (<VBF:MODE>mode).to_constant ();
  int lane = INTVAL (operands[4]);
  operands[4] = gen_int_mode (ENDIAN_LANE_N (nunits / 2, lane), SImode);
  return "bfdot\t%0.<VDQSF:Vtype>, %2.<VDQSF:Vbfdottype>, %3.2h[%4]";
}
  [(set_attr "type" "neon_dot<VDQSF:q>")]

That is operand 3 should be using "x" constraint.

[Bug target/104921] aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |acoplan at gcc dot gnu.org

--- Comment #4 from Alex Coplan <acoplan at gcc dot gnu.org> ---
I'll take a look at this

[Bug target/104921] aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED

[Bug target/104921] aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Alex Coplan <acoplan@gcc.gnu.org>:

https://gcc.gnu.org/g:277e1f30a5e4e634304a7b8a532825119f0ea47f

commit r13-5718-g277e1f30a5e4e634304a7b8a532825119f0ea47f
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Mon Feb 6 14:32:21 2023 +0000

    aarch64: Fix up bfmlal lane pattern [PR104921]

    As the testcase shows, this pattern had an incorrect constraint leading
    to GCC's output getting rejected by the assembler.

    This patch fixes the constraint accordingly.

    The test is split into two: one that can run without bf16 support from
    the assembler and another that checks that the output actually assembles
    when such support is available.

    Bootstrapped/regtested on aarch64-linux-gnu.

    OK for GCC 13? Or better to wait for next stage 1? What about backports?

    Thanks,
    Alex

    gcc/ChangeLog:

            PR target/104921
            * config/aarch64/aarch64-simd.md (aarch64_bfmlal<bt>_lane<q>v4sf):
            Use correct constraint for operand 3.

    gcc/testsuite/ChangeLog:

            PR target/104921
            * gcc.target/aarch64/pr104921-1.c: New test.
            * gcc.target/aarch64/pr104921-2.c: New test.
            * gcc.target/aarch64/pr104921.x: Include file for new tests.

[Bug target/104921] aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by Alex Coplan
<acoplan@gcc.gnu.org>:

https://gcc.gnu.org/g:5b99b0f1ee65ad50b5e6d3a57aace616273cc814

commit r12-9190-g5b99b0f1ee65ad50b5e6d3a57aace616273cc814
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Mon Feb 6 14:32:21 2023 +0000

    aarch64: Fix up bfmlal lane pattern [PR104921]

    As the testcase shows, this pattern had an incorrect constraint leading
    to GCC's output getting rejected by the assembler.

    This patch fixes the constraint accordingly.

    The test is split into two: one that can run without bf16 support from
    the assembler and another that checks that the output actually assembles
    when such support is available.

    gcc/ChangeLog:

            PR target/104921
            * config/aarch64/aarch64-simd.md (aarch64_bfmlal<bt>_lane<q>v4sf):
            Use correct constraint for operand 3.

    gcc/testsuite/ChangeLog:

            PR target/104921
            * gcc.target/aarch64/pr104921-1.c: New test.
            * gcc.target/aarch64/pr104921-2.c: New test.
            * gcc.target/aarch64/pr104921.x: Include file for new tests.

    (cherry picked from commit 277e1f30a5e4e634304a7b8a532825119f0ea47f)

[Bug target/104921] aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-11 branch has been updated by Alex Coplan
<acoplan@gcc.gnu.org>:

https://gcc.gnu.org/g:ed3b4de8a648da4e574fb64344e90b6460946511

commit r11-10536-ged3b4de8a648da4e574fb64344e90b6460946511
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Mon Feb 6 14:32:21 2023 +0000

    aarch64: Fix up bfmlal lane pattern [PR104921]

    As the testcase shows, this pattern had an incorrect constraint leading
    to GCC's output getting rejected by the assembler.

    This patch fixes the constraint accordingly.

    The test is split into two: one that can run without bf16 support from
    the assembler and another that checks that the output actually assembles
    when such support is available.

    gcc/ChangeLog:

            PR target/104921
            * config/aarch64/aarch64-simd.md (aarch64_bfmlal<bt>_lane<q>v4sf):
            Use correct constraint for operand 3.

    gcc/testsuite/ChangeLog:

            PR target/104921
            * gcc.target/aarch64/pr104921-1.c: New test.
            * gcc.target/aarch64/pr104921-2.c: New test.
            * gcc.target/aarch64/pr104921.x: Include file for new tests.

    (cherry picked from commit 277e1f30a5e4e634304a7b8a532825119f0ea47f)

[Bug target/104921] aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Alex Coplan
<acoplan@gcc.gnu.org>:

https://gcc.gnu.org/g:617377cc1641e4f63617b192e224bc96dfbbd324

commit r10-11222-g617377cc1641e4f63617b192e224bc96dfbbd324
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Mon Feb 6 14:32:21 2023 +0000

    aarch64: Fix up bfmlal lane pattern [PR104921]

    As the testcase shows, this pattern had an incorrect constraint leading
    to GCC's output getting rejected by the assembler.

    This patch fixes the constraint accordingly.

    The test is split into two: one that can run without bf16 support from
    the assembler and another that checks that the output actually assembles
    when such support is available.

    gcc/ChangeLog:

            PR target/104921
            * config/aarch64/aarch64-simd.md (aarch64_bfmlal<bt>_lane<q>v4sf):
            Use correct constraint for operand 3.

    gcc/testsuite/ChangeLog:

            PR target/104921
            * gcc.target/aarch64/pr104921-1.c: New test.
            * gcc.target/aarch64/pr104921-2.c: New test.
            * gcc.target/aarch64/pr104921.x: Include file for new tests.

    (cherry picked from commit 277e1f30a5e4e634304a7b8a532825119f0ea47f)

[Bug target/104921] aarch64: Assembler failure with vbfmlalbq_lane_f32 intrinsic

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #9 from Alex Coplan <acoplan at gcc dot gnu.org> ---
Fixed.