[Bug target/105123] New: wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[Bug target/105123] New: wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

            Bug ID: 105123
           Summary: wrong code with -m32 -mtune=i686 and
                    __builtin_shuffle()
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Keywords: wrong-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz
  Target Milestone: ---
              Host: x86_64-pc-linux-gnu
            Target: x86_64-pc-linux-gnu

Created attachment 52733
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=52733&action=edit
reduced testcase

Output:
$ x86_64-pc-linux-gnu-gcc -m32 -mtune=i686 testcase.c
$ ./a.out 
Aborted

v[] is { 0, 0, 0, 0 }

$ x86_64-pc-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=/repo/gcc-trunk/binary-latest-amd64/bin/x86_64-pc-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/repo/gcc-trunk/binary-trunk-r12-7935-20220331110233-g90533de067d-checking-yes-rtl-df-extra-amd64/bin/../libexec/gcc/x86_64-pc-linux-gnu/12.0.1/lto-wrapper
Target: x86_64-pc-linux-gnu
Configured with: /repo/gcc-trunk//configure --enable-languages=c,c++
--enable-valgrind-annotations --disable-nls --enable-checking=yes,rtl,df,extra
--with-cloog --with-ppl --with-isl --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=x86_64-pc-linux-gnu
--with-ld=/usr/bin/x86_64-pc-linux-gnu-ld
--with-as=/usr/bin/x86_64-pc-linux-gnu-as --disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-r12-7935-20220331110233-g90533de067d-checking-yes-rtl-df-extra-amd64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 12.0.1 20220331 (experimental) (GCC)

[Bug target/105123] wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[marxin at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

Martin Liška <marxin at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |needs-bisection
                 CC|                            |jakub at gcc dot gnu.org,
                   |                            |marxin at gcc dot gnu.org
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2022-04-01
     Ever confirmed|0                           |1

--- Comment #1 from Martin Liška <marxin at gcc dot gnu.org> ---
Started in between 4.8.x and 4.9.

[Bug target/105123] wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Yeah, I'll bisect.

[Bug target/105123] [9/10/11/12 Regression] wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|needs-bisection             |
   Target Milestone|---                         |9.5
           Priority|P3                          |P2
            Summary|wrong code with -m32        |[9/10/11/12 Regression]
                   |-mtune=i686 and             |wrong code with -m32
                   |__builtin_shuffle()         |-mtune=i686 and
                   |                            |__builtin_shuffle()

--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Started with r0-127375-gdd908cc5d8ee9e775c45b5a7078e1276f321d134

[Bug target/105123] [9/10/11/12 Regression] wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |jakub at gcc dot gnu.org
             Status|NEW                         |ASSIGNED

[Bug target/105123] [9/10/11/12 Regression] wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Created attachment 52735
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=52735&action=edit
gcc12-pr105123.patch

Untested fix.
The problem was expansion of a (dead) statement
  _1 = {u.0_3, u.0_3, u.0_3, u.0_3};
where the expansion overwrote the pseudo containing u.0_3:
(insn 10 9 11 (parallel [
            (set (reg:SI 83 [ u.0_3 ])
                (ashift:SI (reg:SI 83 [ u.0_3 ])
                    (const_int 16 [0x10])))
            (clobber (reg:CC 17 flags))
        ]) "pr105123.c":6:31 -1
     (nil))

(insn 11 10 12 (parallel [
            (set (reg:SI 83 [ u.0_3 ])
                (ior:SI (reg:SI 83 [ u.0_3 ])
                    (reg:SI 83 [ u.0_3 ])))
            (clobber (reg:CC 17 flags))
        ]) "pr105123.c":6:31 -1
     (nil))

(insn 12 11 13 (parallel [
            (set (reg:SI 83 [ u.0_3 ])
                (ashift:SI (reg:SI 83 [ u.0_3 ])
                    (const_int 16 [0x10])))
            (clobber (reg:CC 17 flags))
        ]) "pr105123.c":6:31 -1
     (nil))

(insn 13 12 14 (parallel [
            (set (reg:SI 83 [ u.0_3 ])
                (ior:SI (reg:SI 83 [ u.0_3 ])
                    (reg:SI 83 [ u.0_3 ])))
            (clobber (reg:CC 17 flags))
        ]) "pr105123.c":6:31 -1
     (nil))

(insn 14 13 15 (clobber (reg:V4HI 110)) "pr105123.c":6:31 -1
     (nil))

(insn 15 14 16 (set (subreg:SI (reg:V4HI 110) 0)
        (reg:SI 83 [ u.0_3 ])) "pr105123.c":6:31 -1
     (nil))

(insn 16 15 17 (set (subreg:SI (reg:V4HI 110) 4)
        (reg:SI 83 [ u.0_3 ])) "pr105123.c":6:31 -1
     (nil))

[Bug target/105123] [9/10/11/12 Regression] wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:e1a74058b784c845e84a0cf1997b54b984df483d

commit r12-7973-ge1a74058b784c845e84a0cf1997b54b984df483d
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sun Apr 3 21:50:43 2022 +0200

    i386: Fix up ix86_expand_vector_init_general [PR105123]

    The following testcase is miscompiled on ia32.
    The problem is that at -O0 we end up with:
      vector(4) short unsigned int _1;
      short unsigned int u.0_3;
    ...
      _1 = {u.0_3, u.0_3, u.0_3, u.0_3};
    statement (dead) which is wrongly expanded.
    elt is (subreg:HI (reg:SI 83 [ u.0_3 ]) 0), tmp_mode SImode,
    so after convert_mode we start with word (reg:SI 83 [ u.0_3 ]).
    The intent is to manually broadcast that value to 2 SImode parts,
    but because we pass word as target to expand_simple_binop, it will
    overwrite (reg:SI 83 [ u.0_3 ]) and we end up with 0:
       10: {r83:SI=r83:SI<<0x10;clobber flags:CC;}
       11: {r83:SI=r83:SI|r83:SI;clobber flags:CC;}
       12: {r83:SI=r83:SI<<0x10;clobber flags:CC;}
       13: {r83:SI=r83:SI|r83:SI;clobber flags:CC;}
       14: clobber r110:V4HI
       15: r110:V4HI#0=r83:SI
       16: r110:V4HI#4=r83:SI
    as the two ors do nothing and two shifts each by 16 left shift it all
    away.
    The following patch fixes that by using NULL_RTX target, so we expand it as
       10: {r110:SI=r83:SI<<0x10;clobber flags:CC;}
       11: {r111:SI=r110:SI|r83:SI;clobber flags:CC;}
       12: {r112:SI=r83:SI<<0x10;clobber flags:CC;}
       13: {r113:SI=r112:SI|r83:SI;clobber flags:CC;}
       14: clobber r114:V4HI
       15: r114:V4HI#0=r111:SI
       16: r114:V4HI#4=r113:SI
    instead.

    Another possibility would be to pass NULL_RTX only when word == elt
    and word otherwise, where word would necessarily be a pseudo from the first
    shift after passing NULL_RTX there once or pass NULL_RTX for the shift and
    word for ior.

    2022-04-03  Jakub Jelinek  <jakub@redhat.com>

            PR target/105123
            * config/i386/i386-expand.cc (ix86_expand_vector_init_general):
Avoid
            using word as target for expand_simple_binop when doing ASHIFT and
            IOR.

            * gcc.target/i386/pr105123.c: New test.

[Bug target/105123] [9/10/11/12 Regression] wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-11 branch has been updated by Jakub Jelinek
<jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:ecc6450668326e52d019b3c298f2c61734ee32c2

commit r11-9755-gecc6450668326e52d019b3c298f2c61734ee32c2
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sun Apr 3 21:50:43 2022 +0200

    i386: Fix up ix86_expand_vector_init_general [PR105123]

    The following testcase is miscompiled on ia32.
    The problem is that at -O0 we end up with:
      vector(4) short unsigned int _1;
      short unsigned int u.0_3;
    ...
      _1 = {u.0_3, u.0_3, u.0_3, u.0_3};
    statement (dead) which is wrongly expanded.
    elt is (subreg:HI (reg:SI 83 [ u.0_3 ]) 0), tmp_mode SImode,
    so after convert_mode we start with word (reg:SI 83 [ u.0_3 ]).
    The intent is to manually broadcast that value to 2 SImode parts,
    but because we pass word as target to expand_simple_binop, it will
    overwrite (reg:SI 83 [ u.0_3 ]) and we end up with 0:
       10: {r83:SI=r83:SI<<0x10;clobber flags:CC;}
       11: {r83:SI=r83:SI|r83:SI;clobber flags:CC;}
       12: {r83:SI=r83:SI<<0x10;clobber flags:CC;}
       13: {r83:SI=r83:SI|r83:SI;clobber flags:CC;}
       14: clobber r110:V4HI
       15: r110:V4HI#0=r83:SI
       16: r110:V4HI#4=r83:SI
    as the two ors do nothing and two shifts each by 16 left shift it all
    away.
    The following patch fixes that by using NULL_RTX target, so we expand it as
       10: {r110:SI=r83:SI<<0x10;clobber flags:CC;}
       11: {r111:SI=r110:SI|r83:SI;clobber flags:CC;}
       12: {r112:SI=r83:SI<<0x10;clobber flags:CC;}
       13: {r113:SI=r112:SI|r83:SI;clobber flags:CC;}
       14: clobber r114:V4HI
       15: r114:V4HI#0=r111:SI
       16: r114:V4HI#4=r113:SI
    instead.

    Another possibility would be to pass NULL_RTX only when word == elt
    and word otherwise, where word would necessarily be a pseudo from the first
    shift after passing NULL_RTX there once or pass NULL_RTX for the shift and
    word for ior.

    2022-04-03  Jakub Jelinek  <jakub@redhat.com>

            PR target/105123
            * config/i386/i386-expand.c (ix86_expand_vector_init_general):
Avoid
            using word as target for expand_simple_binop when doing ASHIFT and
            IOR.

            * gcc.target/i386/pr105123.c: New test.

    (cherry picked from commit e1a74058b784c845e84a0cf1997b54b984df483d)

[Bug target/105123] [9/10 Regression] wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[9/10/11/12 Regression]     |[9/10 Regression] wrong
                   |wrong code with -m32        |code with -m32 -mtune=i686
                   |-mtune=i686 and             |and __builtin_shuffle()
                   |__builtin_shuffle()         |

--- Comment #7 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed for 11.3+ and 12.1+ so far.

[Bug target/105123] [9/10 Regression] wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Jakub Jelinek
<jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:e18956892bf35e13771e1360f07670d422c3e5e7

commit r10-10703-ge18956892bf35e13771e1360f07670d422c3e5e7
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sun Apr 3 21:50:43 2022 +0200

    i386: Fix up ix86_expand_vector_init_general [PR105123]

    The following testcase is miscompiled on ia32.
    The problem is that at -O0 we end up with:
      vector(4) short unsigned int _1;
      short unsigned int u.0_3;
    ...
      _1 = {u.0_3, u.0_3, u.0_3, u.0_3};
    statement (dead) which is wrongly expanded.
    elt is (subreg:HI (reg:SI 83 [ u.0_3 ]) 0), tmp_mode SImode,
    so after convert_mode we start with word (reg:SI 83 [ u.0_3 ]).
    The intent is to manually broadcast that value to 2 SImode parts,
    but because we pass word as target to expand_simple_binop, it will
    overwrite (reg:SI 83 [ u.0_3 ]) and we end up with 0:
       10: {r83:SI=r83:SI<<0x10;clobber flags:CC;}
       11: {r83:SI=r83:SI|r83:SI;clobber flags:CC;}
       12: {r83:SI=r83:SI<<0x10;clobber flags:CC;}
       13: {r83:SI=r83:SI|r83:SI;clobber flags:CC;}
       14: clobber r110:V4HI
       15: r110:V4HI#0=r83:SI
       16: r110:V4HI#4=r83:SI
    as the two ors do nothing and two shifts each by 16 left shift it all
    away.
    The following patch fixes that by using NULL_RTX target, so we expand it as
       10: {r110:SI=r83:SI<<0x10;clobber flags:CC;}
       11: {r111:SI=r110:SI|r83:SI;clobber flags:CC;}
       12: {r112:SI=r83:SI<<0x10;clobber flags:CC;}
       13: {r113:SI=r112:SI|r83:SI;clobber flags:CC;}
       14: clobber r114:V4HI
       15: r114:V4HI#0=r111:SI
       16: r114:V4HI#4=r113:SI
    instead.

    Another possibility would be to pass NULL_RTX only when word == elt
    and word otherwise, where word would necessarily be a pseudo from the first
    shift after passing NULL_RTX there once or pass NULL_RTX for the shift and
    word for ior.

    2022-04-03  Jakub Jelinek  <jakub@redhat.com>

            PR target/105123
            * config/i386/i386-expand.c (ix86_expand_vector_init_general):
Avoid
            using word as target for expand_simple_binop when doing ASHIFT and
            IOR.

            * gcc.target/i386/pr105123.c: New test.

    (cherry picked from commit e1a74058b784c845e84a0cf1997b54b984df483d)

[Bug target/105123] [9/10 Regression] wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

--- Comment #9 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Jakub Jelinek
<jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:a78199c69f794a4ccacd123adbe1aaa29b077fa1

commit r9-10144-ga78199c69f794a4ccacd123adbe1aaa29b077fa1
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sun Apr 3 21:50:43 2022 +0200

    i386: Fix up ix86_expand_vector_init_general [PR105123]

    The following testcase is miscompiled on ia32.
    The problem is that at -O0 we end up with:
      vector(4) short unsigned int _1;
      short unsigned int u.0_3;
    ...
      _1 = {u.0_3, u.0_3, u.0_3, u.0_3};
    statement (dead) which is wrongly expanded.
    elt is (subreg:HI (reg:SI 83 [ u.0_3 ]) 0), tmp_mode SImode,
    so after convert_mode we start with word (reg:SI 83 [ u.0_3 ]).
    The intent is to manually broadcast that value to 2 SImode parts,
    but because we pass word as target to expand_simple_binop, it will
    overwrite (reg:SI 83 [ u.0_3 ]) and we end up with 0:
       10: {r83:SI=r83:SI<<0x10;clobber flags:CC;}
       11: {r83:SI=r83:SI|r83:SI;clobber flags:CC;}
       12: {r83:SI=r83:SI<<0x10;clobber flags:CC;}
       13: {r83:SI=r83:SI|r83:SI;clobber flags:CC;}
       14: clobber r110:V4HI
       15: r110:V4HI#0=r83:SI
       16: r110:V4HI#4=r83:SI
    as the two ors do nothing and two shifts each by 16 left shift it all
    away.
    The following patch fixes that by using NULL_RTX target, so we expand it as
       10: {r110:SI=r83:SI<<0x10;clobber flags:CC;}
       11: {r111:SI=r110:SI|r83:SI;clobber flags:CC;}
       12: {r112:SI=r83:SI<<0x10;clobber flags:CC;}
       13: {r113:SI=r112:SI|r83:SI;clobber flags:CC;}
       14: clobber r114:V4HI
       15: r114:V4HI#0=r111:SI
       16: r114:V4HI#4=r113:SI
    instead.

    Another possibility would be to pass NULL_RTX only when word == elt
    and word otherwise, where word would necessarily be a pseudo from the first
    shift after passing NULL_RTX there once or pass NULL_RTX for the shift and
    word for ior.

    2022-04-03  Jakub Jelinek  <jakub@redhat.com>

            PR target/105123
            * config/i386/i386.c (ix86_expand_vector_init_general): Avoid
            using word as target for expand_simple_binop when doing ASHIFT and
            IOR.

            * gcc.target/i386/pr105123.c: New test.

    (cherry picked from commit e1a74058b784c845e84a0cf1997b54b984df483d)

[Bug target/105123] [9/10 Regression] wrong code with -m32 -mtune=i686 and __builtin_shuffle()

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105123

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #10 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed.