[Bug target/105354] New: __builtin_shuffle for alignr generates suboptimal code unless SSSE3 is enabled

[Bug target/105354] New: __builtin_shuffle for alignr generates suboptimal code unless SSSE3 is enabled

[john_platts at hotmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105354

            Bug ID: 105354
           Summary: __builtin_shuffle for alignr generates suboptimal code
                    unless SSSE3 is enabled
           Product: gcc
           Version: 11.2.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: john_platts at hotmail dot com
  Target Milestone: ---

The below code generates suboptimal code if SSE2 is enabled but SSSE3 is not
enabled:
#include <cstdint>

typedef std::uint8_t Simd128U8VectT __attribute__((__vector_size__(16)));

template<int RotateAmt>
static inline Simd128U8VectT RotateRightByByteAmt(Simd128U8VectT vect) noexcept
{
    constexpr int NormalizedRotateAmt = RotateAmt & 15;

    if constexpr(NormalizedRotateAmt == 0)
        return vect;
    else
        return __builtin_shuffle(vect, vect, (Simd128U8VectT){
            NormalizedRotateAmt, NormalizedRotateAmt + 1,
            NormalizedRotateAmt + 2, NormalizedRotateAmt + 3,
            NormalizedRotateAmt + 4, NormalizedRotateAmt + 5,
            NormalizedRotateAmt + 6, NormalizedRotateAmt + 7,
            NormalizedRotateAmt + 8, NormalizedRotateAmt + 9,
            NormalizedRotateAmt + 10, NormalizedRotateAmt + 11,
            NormalizedRotateAmt + 12, NormalizedRotateAmt + 13,
            NormalizedRotateAmt + 14, NormalizedRotateAmt + 15 });
}

auto func1(Simd128U8VectT vect) noexcept {
    return RotateRightByByteAmt<5>(vect);
}

Here is the code that is generated on GCC 11 if the -O2 -mssse3 options are
specified:
func1(unsigned char __vector(16)):
        palignr xmm0, xmm0, 5
        ret

Here is the code that is generated on GCC 11 if the -O2 option is specified but
the -mssse3 option is not specified on 64-bit x86 platforms:
func1(unsigned char __vector(16)):
        sub     rsp, 144
        movd    ecx, xmm0
        movaps  XMMWORD PTR [rsp+8], xmm0
        movzx   edx, BYTE PTR [rsp+20]
        movzx   ecx, cl
        movaps  XMMWORD PTR [rsp+24], xmm0
        movzx   eax, BYTE PTR [rsp+35]
        sal     rdx, 8
        movaps  XMMWORD PTR [rsp+40], xmm0
        or      rdx, rax
        movzx   eax, BYTE PTR [rsp+50]
        movaps  XMMWORD PTR [rsp+56], xmm0
        sal     rdx, 8
        movaps  XMMWORD PTR [rsp+72], xmm0
        or      rdx, rax
        movzx   eax, BYTE PTR [rsp+65]
        movaps  XMMWORD PTR [rsp+88], xmm0
        sal     rdx, 8
        movaps  XMMWORD PTR [rsp+104], xmm0
        or      rdx, rax
        movzx   eax, BYTE PTR [rsp+80]
        movaps  XMMWORD PTR [rsp-104], xmm0
        sal     rdx, 8
        movaps  XMMWORD PTR [rsp-88], xmm0
        movzx   edi, BYTE PTR [rsp-85]
        or      rdx, rax
        movzx   eax, BYTE PTR [rsp+95]
        movaps  XMMWORD PTR [rsp-72], xmm0
        sal     rdx, 8
        movaps  XMMWORD PTR [rsp-56], xmm0
        or      rdx, rax
        movzx   eax, BYTE PTR [rsp+110]
        movaps  XMMWORD PTR [rsp-40], xmm0
        sal     rdx, 8
        movaps  XMMWORD PTR [rsp-24], xmm0
        or      rdx, rax
        movzx   eax, BYTE PTR [rsp-100]
        movaps  XMMWORD PTR [rsp+120], xmm0
        movzx   esi, BYTE PTR [rsp+125]
        movaps  XMMWORD PTR [rsp-8], xmm0
        sal     rdx, 8
        sal     rax, 8
        or      rdx, rsi
        or      rax, rdi
        movzx   edi, BYTE PTR [rsp-70]
        sal     rax, 8
        or      rax, rdi
        movzx   edi, BYTE PTR [rsp-55]
        sal     rax, 8
        or      rax, rdi
        sal     rax, 8
        or      rax, rcx
        movzx   ecx, BYTE PTR [rsp-25]
        sal     rax, 8
        or      rax, rcx
        movzx   ecx, BYTE PTR [rsp-10]
        sal     rax, 8
        or      rax, rcx
        movzx   ecx, BYTE PTR [rsp+5]
        mov     QWORD PTR [rsp-120], rdx
        sal     rax, 8
        or      rax, rcx
        mov     QWORD PTR [rsp-112], rax
        movdqa  xmm0, XMMWORD PTR [rsp-120]
        add     rsp, 144
        ret

Here is a more optimal implementation of the above code on 64-bit x86 platforms
when SSE2 is enabled but SSSE3 is not enabled:
func1(unsigned char __vector(16)):
        movdqa  xmm1, xmm0
        psrldq  xmm1, 5
        pslldq  xmm0, 11
        por     xmm0, xmm1
        ret

[Bug target/105354] __builtin_shuffle for alignr generates suboptimal code unless SSSE3 is enabled

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105354

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Severity|normal                      |enhancement
             Target|                            |x86_64-linux-gnu

[Bug target/105354] __builtin_shuffle for alignr generates suboptimal code unless SSSE3 is enabled

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105354

Hongtao.liu <crazylht at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |crazylht at gmail dot com

--- Comment #1 from Hongtao.liu <crazylht at gmail dot com> ---
Yes, and I think it's only available for simd128u8, not for simd128u16/u32/u64.

[Bug target/105354] __builtin_shuffle for alignr generates suboptimal code unless SSSE3 is enabled

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105354

--- Comment #2 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Hongtao.liu from comment #1)
> Yes, and I think it's only available for simd128u8, not for
> simd128u16/u32/u64.

No, under sse2 the optimization is also availble for simd128u16, directly
generates pshufd/shufpd for simd128u32/u64.

[Bug target/105354] __builtin_shuffle for alignr generates suboptimal code unless SSSE3 is enabled

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105354

--- Comment #3 from Hongtao.liu <crazylht at gmail dot com> ---
Created attachment 52893
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=52893&action=edit
Patch pending for GCC13

Now, we can also generate

foo3:
.LFB3:
        .cfi_startproc
        movdqa  .LC1(%rip), %xmm2
        pslldq  $9, %xmm1
        psrldq  $5, %xmm0
        pand    %xmm2, %xmm0
        pandn   %xmm1, %xmm2
        por     %xmm2, %xmm0
        ret
.LC1:
        .byte   -1
        .byte   -1
        .byte   -1
        .byte   -1
        .byte   -1
        .byte   -1
        .byte   -1
        .byte   -1
        .byte   -1
        .byte   -1
        .byte   0
        .byte   0
        .byte   0
        .byte   0
        .byte   0
        .byte   0
        .align 16

for

v16qi
foo3 (v16qi a, v16qi b)
{
  return __builtin_shufflevector (a, b, 5, 6, 7, 8, 9, 10, 11, 12,
                                  13, 14, 17, 18, 19, 20, 21, 22);
}

[Bug target/105354] __builtin_shuffle for alignr generates suboptimal code unless SSSE3 is enabled

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105354

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:fcda0efccad41eba9134c1bd9d024a93d93fb82f

commit r13-210-gfcda0efccad41eba9134c1bd9d024a93d93fb82f
Author: liuhongt <hongtao.liu@intel.com>
Date:   Wed Apr 27 16:24:44 2022 +0800

    Implement permutation with pslldq + psrldq + por when pshufb is not
available.

    pand/pandn may be used to clear upper/lower bits of the operands, in
    that case there will be 4-5 instructions for permutation, and it's
    still better than scalar codes.

    gcc/ChangeLog:

            PR target/105354
            * config/i386/i386-expand.cc
            (expand_vec_perm_pslldq_psrldq_por): New function.
            (ix86_expand_vec_perm_const_1): Try
            expand_vec_perm_pslldq_psrldq_por for both 3-instruction and
            4/5-instruction sequence.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr105354-1.c: New test.
            * gcc.target/i386/pr105354-2.c: New test.

[Bug target/105354] __builtin_shuffle for alignr generates suboptimal code unless SSSE3 is enabled

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105354

--- Comment #5 from Hongtao.liu <crazylht at gmail dot com> ---
Fixed in GCC13.

[Bug target/105354] __builtin_shuffle for alignr generates suboptimal code unless SSSE3 is enabled

[chfast at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105354

Paweł Bylica <chfast at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |chfast at gmail dot com

--- Comment #6 from Paweł Bylica <chfast at gmail dot com> ---
Confirmed fixed. https://godbolt.org/z/rEqcMqKaz