[Bug target/106586] New: riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[Bug target/106586] New: riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

            Bug ID: 106586
           Summary: riscv32 still broke with zba_zbb_zbc_zbs, ICE in
                    do_SUBST in C++ code
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pinskia at gcc dot gnu.org
  Target Milestone: ---
            Target: riscv

/home/apinski/src/toolchain-riscv/riscv-build/./gcc/xgcc -shared-libgcc
-B/home/apinski/src/toolchain-riscv/riscv-build/./gcc -nostdinc++
-L/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/libstdc++-v3/src
-L/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/libstdc++-v3/src/.libs
-L/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/libstdc++-v3/libsupc++/.libs
-nostdinc
-B/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/newlib/
-isystem
/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/newlib/targ-include
-isystem /home/apinski/src/toolchain-riscv/src/newlib/libc/include
-B/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/libgloss/riscv32
-L/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/libgloss/libnosys
-L/home/apinski/src/toolchain-riscv/src/libgloss/riscv32
-B/home/apinski/src/toolchain-riscv/riscv-build/../marvelldpu-tools/riscv32-marvelldpu-elf/bin/
-B/home/apinski/src/toolchain-riscv/riscv-build/../marvelldpu-tools/riscv32-marvelldpu-elf/lib/
-isystem
/home/apinski/src/toolchain-riscv/riscv-build/../marvelldpu-tools/riscv32-marvelldpu-elf/include
-isystem
/home/apinski/src/toolchain-riscv/riscv-build/../marvelldpu-tools/riscv32-marvelldpu-elf/sys-include
-L/home/apinski/src/toolchain-riscv/riscv-build/./ld
-I/home/apinski/src/toolchain-riscv/src/libstdc++-v3/../libgcc
-I/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/libstdc++-v3/include/riscv32-marvelldpu-elf
-I/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/libstdc++-v3/include
-I/home/apinski/src/toolchain-riscv/src/libstdc++-v3/libsupc++ -std=gnu++11
-fno-implicit-templates -Wall -Wextra -Wwrite-strings -Wcast-qual -Wabi=2
-fdiagnostics-show-location=once -ffunction-sections -fdata-sections
-frandom-seed=cow-sstream-inst.lo -g -O2 -c
../../../../../src/libstdc++-v3/src/c++11/cow-sstream-inst.cc -o
cow-sstream-inst.o -freport-bug
during RTL pass: combine
In file included from
/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/libstdc++-v3/include/sstream:1218,
                 from
../../../../../src/libstdc++-v3/src/c++11/sstream-inst.cc:34,
                 from
../../../../../src/libstdc++-v3/src/c++11/cow-sstream-inst.cc:30:
/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/libstdc++-v3/include/bits/sstream.tcc:
In member function ‘void std::basic_stringbuf<_CharT, _Traits,
_Alloc>::_M_pbump(char_type*, char_type*, off_type) [with _CharT = char;
_Traits = std::char_traits<char>; _Alloc = std::allocator<char>]’:
/home/apinski/src/toolchain-riscv/riscv-build/riscv32-marvelldpu-elf/libstdc++-v3/include/bits/sstream.tcc:286:5:
internal compiler error: in do_SUBST, at combine.cc:701
  286 |     }
      |     ^
0x8e268f do_SUBST
        ../../src/gcc/combine.cc:700
0x1918186 subst
        ../../src/gcc/combine.cc:5579
0x191807a subst
        ../../src/gcc/combine.cc:5532
0x191807a subst
        ../../src/gcc/combine.cc:5532
0x191b4e7 try_combine
        ../../src/gcc/combine.cc:3299
0x1921c2b combine_instructions
        ../../src/gcc/combine.cc:1410
0x1921c2b rest_of_handle_combine
        ../../src/gcc/combine.cc:14978
0x1921c2b execute
        ../../src/gcc/combine.cc:15023
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Preprocessed source stored into /tmp/ccozqEz0.out file, please attach this to
your bugreport.

Will attach the preprocessed source in a few minutes.

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Created attachment 53439
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=53439&action=edit
bzip2 testcase

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Reducing ...

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Reduced testcase:
void f(int);
void     g(long long __off)
{
  const int max = (1u << 31) - 1;
  while (__off > max)
    {
      f(max);
    }
}

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5a0adffb5ce..b4a08de6b93 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -426,7 +426,9 @@ riscv_build_integer_1 (struct riscv_integer_op
codes[RISCV_MAX_INTEGER_OPS],
         sign-extended (negative) representation (-1 << 31) for the
         value, if we want to build (1 << 31) in SImode.  This will
         then expand to an LUI instruction.  */
-      if (mode == SImode && value == (HOST_WIDE_INT_1U << 31))
+      if (TARGET_64BIT
+         && mode == SImode
+         && value == (HOST_WIDE_INT_1U << 31))
        codes[0].value = (HOST_WIDE_INT_M1U << 31);

       return 1;


Fixes that ICE but there is still another ICE with the same reduced testcase:
0xd9898c wi::int_traits<std::pair<rtx_def*, machine_mode> >::decompose(long*,
unsigned int, std::pair<rtx_def*, machine_mode> const&)
        ../../src/gcc/rtl.h:2288
0x1136bf7 wide_int_ref_storage<false,
false>::wide_int_ref_storage<std::pair<rtx_def*, machine_mode>
>(std::pair<rtx_def*, machine_mode> const&, unsigned int)
        ../../src/gcc/wide-int.h:1034
0x1136bf7 generic_wide_int<wide_int_ref_storage<false, false>
>::generic_wide_int<std::pair<rtx_def*, machine_mode> >(std::pair<rtx_def*,
machine_mode> const&, unsigned int)
        ../../src/gcc/wide-int.h:790
0x1136bf7 wi::binary_traits<std::pair<rtx_def*, machine_mode>,
std::pair<rtx_def*, machine_mode>, wi::int_traits<std::pair<rtx_def*,
machine_mode> >::precision_type, wi::int_traits<std::pair<rtx_def*,
machine_mode> >::precision_type>::result_type wi::add<std::pair<rtx_def*,
machine_mode>, std::pair<rtx_def*, machine_mode> >(std::pair<rtx_def*,
machine_mode> const&, std::pair<rtx_def*, machine_mode> const&)
        ../../src/gcc/wide-int.h:2442
0x1136bf7 simplify_const_binary_operation(rtx_code, machine_mode, rtx_def*,
rtx_def*)
        ../../src/gcc/simplify-rtx.cc:5004
0x113de58 simplify_context::simplify_binary_operation(rtx_code, machine_mode,
rtx_def*, rtx_def*)
        ../../src/gcc/simplify-rtx.cc:2569
0x10d1b75 simplify_binary_operation(rtx_code, machine_mode, rtx_def*, rtx_def*)
        ../../src/gcc/rtl.h:3475
0x10d1b75 simplify_while_replacing
        ../../src/gcc/recog.cc:686
0x10d1b75 validate_replace_rtx_1
        ../../src/gcc/recog.cc:890
0x10fefb4 note_uses(rtx_def**, void (*)(rtx_def**, void*), void*)
        ../../src/gcc/rtlanal.cc:2065
0x10cd9b2 validate_replace_src_group(rtx_def*, rtx_def*, rtx_insn*)
        ../../src/gcc/recog.cc:979
0x1945e30 try_replace_reg
        ../../src/gcc/cprop.cc:752
0x1946509 constprop_register
        ../../src/gcc/cprop.cc:1023
0x194688b do_local_cprop
        ../../src/gcc/cprop.cc:1208
0x194688b local_cprop_pass
        ../../src/gcc/cprop.cc:1271
0x194688b one_cprop_pass
        ../../src/gcc/cprop.cc:1772
0x194688b execute_rtl_cprop
        ../../src/gcc/cprop.cc:1926
0x194688b execute
        ../../src/gcc/cprop.cc:1966
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

Still debugging this.

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
           Assignee|unassigned at gcc dot gnu.org      |pinskia at gcc dot gnu.org
             Status|UNCONFIRMED                 |ASSIGNED
   Last reconfirmed|                            |2022-08-11

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Mine. The problem here is INT_MIN is always sign extended to HWI. So there
needs to be a mask setting. Looking into how to handle INT_MIN better for
32bits.

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
There is much more changes needed for ZBS support to work correctly for 32bit.
And some to get it to good state for 64bits.
I will be fixing all of them but first I need to setup a test env.

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[jiawei at iscas dot ac.cn]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

jiawei <jiawei at iscas dot ac.cn> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jiawei at iscas dot ac.cn

--- Comment #7 from jiawei <jiawei at iscas dot ac.cn> ---
I had roll back the RISC-V commit and found that this modification cause this
building failure.

https://gcc.gnu.org/git/?p=gcc.git;a=blobdiff;f=gcc/config/riscv/riscv.h;h=6f7f4d3fbdcfa6c8ca03604fbe5817aad6278e2e;hp=5083a1c24b08233810dd3b2aa4278b3ef8a75791;hb=4e72ccad80d69a76d149fba59603b8173fffe8fe;hpb=d19b4342c19e5a7fd84888aa06ebc106438d0c46

But I am not sure what's wrong with it, any suggestions?

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #8 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to jiawei from comment #7)
> I had roll back the RISC-V commit and found that this modification cause
> this building failure.
> 
> https://gcc.gnu.org/git/?p=gcc.git;a=blobdiff;f=gcc/config/riscv/riscv.h;
> h=6f7f4d3fbdcfa6c8ca03604fbe5817aad6278e2e;
> hp=5083a1c24b08233810dd3b2aa4278b3ef8a75791;
> hb=4e72ccad80d69a76d149fba59603b8173fffe8fe;
> hpb=d19b4342c19e5a7fd84888aa06ebc106438d0c46
> 
> But I am not sure what's wrong with it, any suggestions?

Yes the problem is a bit complex, the problem is representation of INT_MIN is
sign extended (always) and HOST_WIDE_INT is always 64bit.
Anyways the fix is to improve the predicate to be correct and fix the
constraints too. I am working towards that but I am doing some other cleanups
along the way to the backend so the riscv backend looks more like a modern
backend.

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #9 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Here is a testcase which shows a similar issue where bseti is not used (ignore
the 1<<31 being undefined/unspecified issue):
int f(int a, int b)
{
  b = 31;
  int tt = sizeof(b)*8 - 1;
  return a | (((__typeof__(b))1) << (b & tt));
}

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #10 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
There is still some missing sign extend of the const_int.
(insn 17 16 18 4 (set (reg:SI 77)
        (mem/u/c:SI (lo_sum:SI (reg/f:SI 78)
                (symbol_ref/u:SI ("*.LC0") [flags 0x82])) [0  S4 A32]))
"t89.c":5:16 140 {*movsi_internal}
     (expr_list:REG_DEAD (reg/f:SI 78)
        (expr_list:REG_EQUAL (const_int 2147483648 [0x80000000])
            (nil))))


Notice the REG_EQUAL.

I think the issue is inside riscv_build_integer_1.

Specifically this:
      alt_cost = 1 + riscv_build_integer_1 (alt_codes, value - low_part, mode);

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #11 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
There was a few issues dealing with not doing trunc_int_for_mode in some cases.

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #12 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Created attachment 53463
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=53463&action=edit
Patch (which might depend on other patches)

I have a full fix now. The problem I mentioned is a few different issues.
First is SINGLE_BIT_MASK_OPERAND is not correct for 32bit for INT_MAX.
single_bit_mask_operand and not_single_bit_mask_operand should be using
SINGLE_BIT_MASK_OPERAND now too to correct for that also.

Next issue is riscv_build_integer_1 should not special case SImode for
!TARAGET_64BIT, it is already correct.

The next issue is riscv_build_integer_1 needs to do trunc_int_for_mode. And
then riscv_move_integer should do that also.
Last but not least riscv_emit_int_compare forgot to do trunc_int_for_mode also.

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #13 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
All patches I have pushed to refs/users/pinskia/heads/riscvbit this includes
all cleanups I did to the backend. I will finish up the patches (add testcases
and run the testsuite) in the next few days.

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

--- Comment #14 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Andrew Pinski <pinskia@gcc.gnu.org>:

https://gcc.gnu.org/g:2c721ea9473ad7615bb47b66509097bd254bb839

commit r13-2188-g2c721ea9473ad7615bb47b66509097bd254bb839
Author: Andrew Pinski <apinski@marvell.com>
Date:   Mon Aug 15 22:25:13 2022 +0000

    [RISCV] Fix PR 106586: riscv32 vs ZBS

    The problem here is two fold. With RISCV32, 32bit
    const_int are always signed extended to 64bit in HWI.
    So that means for SINGLE_BIT_MASK_OPERAND, it should
    mask off the upper bits to see it is a single bit
    for !TARGET_64BIT.
    Plus there are a few locations which forget to call
    trunc_int_for_mode when generating a SImode constant
    so they are not sign extended correctly for HWI.
    The predicates single_bit_mask_operand and
    not_single_bit_mask_operand need get the same handling
    as SINGLE_BIT_MASK_OPERAND so just use SINGLE_BIT_MASK_OPERAND.

    OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with
    --with-arch=rvNimafdc_zba_zbb_zbc_zbs where N is replaced with 32 or 64.

    Thanks,
    Andrew Pinski

    gcc/ChangeLog:

            PR target/106586
            * config/riscv/predicates.md (single_bit_mask_operand):
            Use SINGLE_BIT_MASK_OPERAND instead of directly calling pow2p_hwi.
            (not_single_bit_mask_operand): Likewise.
            * config/riscv/riscv.cc (riscv_build_integer_1): Don't special case
            1<<31 for 32bits as it is already handled.
            Call trunc_int_for_mode on the upper part after the subtraction.
            (riscv_move_integer): Call trunc_int_for_mode before generating
            the integer just make sure the constant has been sign extended
            corectly.
            (riscv_emit_int_compare): Call trunc_int_for_mode after doing the
            addition for the new rhs.
            * config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): If !TARGET64BIT,
            then mask off the upper 32bits of the HWI as it will be sign
extended.

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
   Target Milestone|---                         |13.0
         Resolution|---                         |FIXED

--- Comment #15 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Fixed.