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* [Bug c/107364] New: ICE on Via Nehemiah with --march=native
@ 2022-10-23 10:47 orzel at freehackers dot org
2022-10-23 23:58 ` [Bug target/107364] [10/11/12/13 Regression] " pinskia at gcc dot gnu.org
` (18 more replies)
0 siblings, 19 replies; 20+ messages in thread
From: orzel at freehackers dot org @ 2022-10-23 10:47 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
Bug ID: 107364
Summary: ICE on Via Nehemiah with --march=native
Product: gcc
Version: 10.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: orzel at freehackers dot org
Target Milestone: ---
The cpu is very old:
chopin /etc # cat /proc/cpuinfo
processor : 0
vendor_id : CentaurHauls
cpu family : 6
model : 9
model name : VIA Nehemiah
stepping : 3
cpu MHz : 997.000
cache size : 64 KB
fdiv_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu de pse tsc msr cx8 mtrr pge cmov mmx fxsr sse cpuid rng
rng_en
bugs : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds
swapgs itlb_multihit mmio_unknown
bogomips : 1999.03
clflush size : 32
cache_alignment : 32
address sizes : 32 bits physical, 32 bits virtual
power management:
The compiler crashes when using -march=native. You dont need to compile for it
to crash, --help=target is enough. As a result, gcc can't build itself anymore.
The last known 'working' version is gcc 9. Tested are gcc 10, 11, and 12, all
crashing the same way. This is how it looks:
chopin /etc # gcc-12 -Q --help=target -march=native -freport-bug
gcc-12: internal compiler error: in cpu_indicator_init, at
common/config/i386/cpuinfo.h:986
0xb7cd535e __libc_start_main
???:0
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See <https://bugs.gentoo.org/> for instructions.
chopin /etc # gcc-12 -Q --help=target
The following options are target specific:
-m128bit-long-double [disabled]
-m16 [disabled]
-m32 [enabled]
-m3dnow [disabled]
-m3dnowa [disabled]
-m64 [disabled]
-m80387 [enabled]
-m8bit-idiv [disabled]
-m96bit-long-double [enabled]
-mabi= sysv
-mabm [disabled]
-maccumulate-outgoing-args [disabled]
-maddress-mode= short
-madx [disabled]
-maes [disabled]
-malign-data= compat
-malign-double [disabled]
-malign-functions= 0
-malign-jumps= 0
-malign-loops= 0
-malign-stringops [enabled]
-mamx-bf16 [disabled]
-mamx-int8 [disabled]
-mamx-tile [disabled]
-mandroid [disabled]
-march= i686
-masm= att
-mavx [disabled]
-mavx2 [disabled]
-mavx256-split-unaligned-load [disabled]
-mavx256-split-unaligned-store [disabled]
-mavx5124fmaps [disabled]
-mavx5124vnniw [disabled]
-mavx512bf16 [disabled]
-mavx512bitalg [disabled]
-mavx512bw [disabled]
-mavx512cd [disabled]
-mavx512dq [disabled]
-mavx512er [disabled]
-mavx512f [disabled]
-mavx512fp16 [disabled]
-mavx512ifma [disabled]
-mavx512pf [disabled]
-mavx512vbmi [disabled]
-mavx512vbmi2 [disabled]
-mavx512vl [disabled]
-mavx512vnni [disabled]
-mavx512vp2intersect [disabled]
-mavx512vpopcntdq [disabled]
-mavxvnni [disabled]
-mbionic [disabled]
-mbmi [disabled]
-mbmi2 [disabled]
-mbranch-cost=<0,5> 3
-mcall-ms2sysv-xlogues [disabled]
-mcet-switch [disabled]
-mcld [disabled]
-mcldemote [disabled]
-mclflushopt [disabled]
-mclwb [disabled]
-mclzero [disabled]
-mcmodel= 32
-mcpu=
-mcrc32 [disabled]
-mcx16 [disabled]
-mdirect-extern-access [enabled]
-mdispatch-scheduler [disabled]
-mdump-tune-features [disabled]
-menqcmd [disabled]
-mf16c [disabled]
-mfancy-math-387 [enabled]
-mfentry [disabled]
-mfentry-name=
-mfentry-section=
-mfma [disabled]
-mfma4 [disabled]
-mforce-drap [disabled]
-mforce-indirect-call [disabled]
-mfp-ret-in-387 [enabled]
-mfpmath= 387
-mfsgsbase [disabled]
-mfunction-return= keep
-mfused-madd -ffp-contract=fast
-mfxsr [disabled]
-mgeneral-regs-only [disabled]
-mgfni [disabled]
-mglibc [enabled]
-mhard-float [enabled]
-mharden-sls= none
-mhle [disabled]
-mhreset [disabled]
-miamcu [disabled]
-mieee-fp [enabled]
-mincoming-stack-boundary= 0
-mindirect-branch-cs-prefix [disabled]
-mindirect-branch-register [disabled]
-mindirect-branch= keep
-minline-all-stringops [disabled]
-minline-stringops-dynamically [disabled]
-minstrument-return= none
-mintel-syntax -masm=intel
-mkl [disabled]
-mlarge-data-threshold=<number> 65536
-mlong-double-128 [disabled]
-mlong-double-64 [disabled]
-mlong-double-80 [enabled]
-mlwp [disabled]
-mlzcnt [disabled]
-mmanual-endbr [disabled]
-mmemcpy-strategy=
-mmemset-strategy=
-mmitigate-rop [disabled]
-mmmx [disabled]
-mmovbe [disabled]
-mmovdir64b [disabled]
-mmovdiri [disabled]
-mmove-max= 128
-mmpx [disabled]
-mms-bitfields [disabled]
-mmusl [disabled]
-mmwait [disabled]
-mmwaitx [disabled]
-mneeded [disabled]
-mno-align-stringops [disabled]
-mno-default [disabled]
-mno-fancy-math-387 [disabled]
-mno-push-args [disabled]
-mno-red-zone [enabled]
-mno-sse4 [enabled]
-mnop-mcount [disabled]
-momit-leaf-frame-pointer [disabled]
-mpc32 [disabled]
-mpc64 [disabled]
-mpc80 [disabled]
-mpclmul [disabled]
-mpcommit [disabled]
-mpconfig [disabled]
-mpku [disabled]
-mpopcnt [disabled]
-mprefer-avx128 -mprefer-vector-width=128
-mprefer-vector-width= none
-mpreferred-stack-boundary= 0
-mprefetchwt1 [disabled]
-mprfchw [disabled]
-mptwrite [disabled]
-mpush-args [enabled]
-mrdpid [disabled]
-mrdrnd [disabled]
-mrdseed [disabled]
-mrecip [disabled]
-mrecip=
-mrecord-mcount [disabled]
-mrecord-return [disabled]
-mred-zone [disabled]
-mregparm= 0
-mrelax-cmpxchg-loop [disabled]
-mrtd [disabled]
-mrtm [disabled]
-msahf [enabled]
-mserialize [disabled]
-msgx [disabled]
-msha [disabled]
-mshstk [disabled]
-mskip-rax-setup [disabled]
-msoft-float [disabled]
-msse [disabled]
-msse2 [disabled]
-msse2avx [disabled]
-msse3 [disabled]
-msse4 [disabled]
-msse4.1 [disabled]
-msse4.2 [disabled]
-msse4a [disabled]
-msse5 -mavx
-msseregparm [disabled]
-mssse3 [disabled]
-mstack-arg-probe [disabled]
-mstack-protector-guard-offset=
-mstack-protector-guard-reg=
-mstack-protector-guard-symbol=
-mstack-protector-guard= tls
-mstackrealign [disabled]
-mstore-max= 128
-mstringop-strategy= [default]
-mstv [enabled]
-mtbm [disabled]
-mtls-dialect= gnu
-mtls-direct-seg-refs [enabled]
-mtsxldtrk [disabled]
-mtune-ctrl=
-mtune= generic
-muclibc [disabled]
-muintr [disabled]
-mvaes [disabled]
-mveclibabi= [default]
-mvect8-ret-in-mem [disabled]
-mvpclmulqdq [disabled]
-mvzeroupper [enabled]
-mwaitpkg [disabled]
-mwbnoinvd [disabled]
-mwidekl [disabled]
-mx32 [disabled]
-mxop [disabled]
-mxsave [disabled]
-mxsavec [disabled]
-mxsaveopt [disabled]
-mxsaves [disabled]
Known assembler dialects (for use with the -masm= option):
att intel
Known ABIs (for use with the -mabi= option):
ms sysv
Known code models (for use with the -mcmodel= option):
32 kernel large medium small
Valid arguments to -mfpmath=:
387 387+sse 387,sse both sse sse+387 sse,387
Known choices for mitigation against straight line speculation with
-mharden-sls=:
all indirect-jmp none return
Known indirect branch choices (for use with the
-mindirect-branch=/-mfunction-return= options):
keep thunk thunk-extern thunk-inline
Known choices for return instrumentation with -minstrument-return=:
call none nop5
Known data alignment choices (for use with the -malign-data= option):
abi cacheline compat
Known vectorization library ABIs (for use with the -mveclibabi= option):
acml svml
Known address mode (for use with the -maddress-mode= option):
long short
Known preferred register vector length (to use with the
-mprefer-vector-width= option):
128 256 512 none
Known stack protector guard (for use with the -mstack-protector-guard=
option):
global tls
Valid arguments to -mstringop-strategy=:
byte_loop libcall loop rep_4byte rep_8byte rep_byte unrolled_loop
vector_loop
Known TLS dialects (for use with the -mtls-dialect= option):
gnu gnu2
Known valid arguments for -march= option:
i386 i486 i586 pentium lakemont pentium-mmx winchip-c6 winchip2 c3 samuel-2
c3-2 nehemiah c7 esther i686 pentiumpro pentium2 pentium3 pentium3m pentium-m
pentium4 pentium4m prescott nocona core2 nehalem corei7 westmere sandybridge
corei7-avx ivybridge core-avx-i haswell core-avx2 broadwell skylake
skylake-avx512 cannonlake icelake-client rocketlake icelake-server cascadelake
tigerlake cooperlake sapphirerapids alderlake bonnell atom silvermont slm
goldmont goldmont-plus tremont knl knm intel geode k6 k6-2 k6-3 athlon
athlon-tbird athlon-4 athlon-xp athlon-mp x86-64 x86-64-v2 x86-64-v3 x86-64-v4
eden-x2 nano nano-1000 nano-2000 nano-3000 nano-x2 eden-x4 nano-x4 k8 k8-sse3
opteron opteron-sse3 athlon64 athlon64-sse3 athlon-fx amdfam10 barcelona bdver1
bdver2 bdver3 bdver4 znver1 znver2 znver3 btver1 btver2 generic native
Known valid arguments for -mtune= option:
generic i386 i486 pentium lakemont pentiumpro pentium4 nocona core2 nehalem
sandybridge haswell bonnell silvermont goldmont goldmont-plus tremont knl knm
skylake skylake-avx512 cannonlake icelake-client icelake-server cascadelake
tigerlake cooperlake sapphirerapids alderlake rocketlake intel geode k6 athlon
k8 amdfam10 bdver1 bdver2 bdver3 bdver4 btver1 btver2 znver1 znver2 znver3
chopin /etc # gcc-9.3.0 -Q --help=target -march=native
The following options are target specific:
(... everything ok here)
A diff between
gcc-9.3.0 -Q --help=target -march=native
and
gcc-12 -Q --help=target
is:
chopin /tmp # diff -u gcc9.target gcc12.target
--- gcc9.target 2022-10-23 12:42:17.942193436 +0200
+++ gcc12.target 2022-10-23 12:42:24.598109760 +0200
@@ -20,28 +20,35 @@
-malign-jumps= 0
-malign-loops= 0
-malign-stringops [enabled]
+ -mamx-bf16 [disabled]
+ -mamx-int8 [disabled]
+ -mamx-tile [disabled]
-mandroid [disabled]
- -march= nehemiah
+ -march= i686
-masm= att
-mavx [disabled]
-mavx2 [disabled]
- -mavx256-split-unaligned-load [enabled]
- -mavx256-split-unaligned-store [enabled]
+ -mavx256-split-unaligned-load [disabled]
+ -mavx256-split-unaligned-store [disabled]
-mavx5124fmaps [disabled]
-mavx5124vnniw [disabled]
+ -mavx512bf16 [disabled]
-mavx512bitalg [disabled]
-mavx512bw [disabled]
-mavx512cd [disabled]
-mavx512dq [disabled]
-mavx512er [disabled]
-mavx512f [disabled]
+ -mavx512fp16 [disabled]
-mavx512ifma [disabled]
-mavx512pf [disabled]
-mavx512vbmi [disabled]
-mavx512vbmi2 [disabled]
-mavx512vl [disabled]
-mavx512vnni [disabled]
+ -mavx512vp2intersect [disabled]
-mavx512vpopcntdq [disabled]
+ -mavxvnni [disabled]
-mbionic [disabled]
-mbmi [disabled]
-mbmi2 [disabled]
@@ -57,8 +64,10 @@
-mcpu=
-mcrc32 [disabled]
-mcx16 [disabled]
+ -mdirect-extern-access [enabled]
-mdispatch-scheduler [disabled]
-mdump-tune-features [disabled]
+ -menqcmd [disabled]
-mf16c [disabled]
-mfancy-math-387 [enabled]
-mfentry [disabled]
@@ -72,22 +81,26 @@
-mfpmath= 387
-mfsgsbase [disabled]
-mfunction-return= keep
- -mfused-madd
- -mfxsr [enabled]
+ -mfused-madd -ffp-contract=fast
+ -mfxsr [disabled]
-mgeneral-regs-only [disabled]
-mgfni [disabled]
-mglibc [enabled]
-mhard-float [enabled]
+ -mharden-sls= none
-mhle [disabled]
+ -mhreset [disabled]
-miamcu [disabled]
-mieee-fp [enabled]
-mincoming-stack-boundary= 0
+ -mindirect-branch-cs-prefix [disabled]
-mindirect-branch-register [disabled]
-mindirect-branch= keep
-minline-all-stringops [disabled]
-minline-stringops-dynamically [disabled]
-minstrument-return= none
- -mintel-syntax
+ -mintel-syntax -masm=intel
+ -mkl [disabled]
-mlarge-data-threshold=<number> 65536
-mlong-double-128 [disabled]
-mlong-double-64 [disabled]
@@ -98,14 +111,17 @@
-mmemcpy-strategy=
-mmemset-strategy=
-mmitigate-rop [disabled]
- -mmmx [enabled]
+ -mmmx [disabled]
-mmovbe [disabled]
-mmovdir64b [disabled]
-mmovdiri [disabled]
+ -mmove-max= 128
-mmpx [disabled]
-mms-bitfields [disabled]
-mmusl [disabled]
+ -mmwait [disabled]
-mmwaitx [disabled]
+ -mneeded [disabled]
-mno-align-stringops [disabled]
-mno-default [disabled]
-mno-fancy-math-387 [disabled]
@@ -122,7 +138,7 @@
-mpconfig [disabled]
-mpku [disabled]
-mpopcnt [disabled]
- -mprefer-avx128
+ -mprefer-avx128 -mprefer-vector-width=128
-mprefer-vector-width= none
-mpreferred-stack-boundary= 0
-mprefetchwt1 [disabled]
@@ -138,15 +154,17 @@
-mrecord-return [disabled]
-mred-zone [disabled]
-mregparm= 0
+ -mrelax-cmpxchg-loop [disabled]
-mrtd [disabled]
-mrtm [disabled]
- -msahf [disabled]
+ -msahf [enabled]
+ -mserialize [disabled]
-msgx [disabled]
-msha [disabled]
-mshstk [disabled]
-mskip-rax-setup [disabled]
-msoft-float [disabled]
- -msse [enabled]
+ -msse [disabled]
-msse2 [disabled]
-msse2avx [disabled]
-msse3 [disabled]
@@ -154,7 +172,7 @@
-msse4.1 [disabled]
-msse4.2 [disabled]
-msse4a [disabled]
- -msse5
+ -msse5 -mavx
-msseregparm [disabled]
-mssse3 [disabled]
-mstack-arg-probe [disabled]
@@ -163,14 +181,17 @@
-mstack-protector-guard-symbol=
-mstack-protector-guard= tls
-mstackrealign [disabled]
+ -mstore-max= 128
-mstringop-strategy= [default]
-mstv [enabled]
-mtbm [disabled]
-mtls-dialect= gnu
-mtls-direct-seg-refs [enabled]
+ -mtsxldtrk [disabled]
-mtune-ctrl=
-mtune= generic
-muclibc [disabled]
+ -muintr [disabled]
-mvaes [disabled]
-mveclibabi= [default]
-mvect8-ret-in-mem [disabled]
@@ -178,6 +199,7 @@
-mvzeroupper [enabled]
-mwaitpkg [disabled]
-mwbnoinvd [disabled]
+ -mwidekl [disabled]
-mx32 [disabled]
-mxop [disabled]
-mxsave [disabled]
@@ -197,6 +219,9 @@
Valid arguments to -mfpmath=:
387 387+sse 387,sse both sse sse+387 sse,387
+ Known choices for mitigation against straight line speculation with
-mharden-sls=:
+ all indirect-jmp none return
+
Known indirect branch choices (for use with the
-mindirect-branch=/-mfunction-return= options):
keep thunk thunk-extern thunk-inline
@@ -225,8 +250,8 @@
gnu gnu2
Known valid arguments for -march= option:
- i386 i486 i586 pentium lakemont pentium-mmx winchip-c6 winchip2 c3
samuel-2 c3-2 nehemiah c7 esther i686 pentiumpro pentium2 pentium3 pentium3m
pentium-m pentium4 pentium4m prescott nocona core2 nehalem corei7 westmere
sandybridge corei7-avx ivybridge core-avx-i haswell core-avx2 broadwell skylake
skylake-avx512 cannonlake icelake-client icelake-server cascadelake bonnell
atom silvermont slm goldmont goldmont-plus tremont knl knm intel geode k6 k6-2
k6-3 athlon athlon-tbird athlon-4 athlon-xp athlon-mp x86-64 eden-x2 nano
nano-1000 nano-2000 nano-3000 nano-x2 eden-x4 nano-x4 k8 k8-sse3 opteron
opteron-sse3 athlon64 athlon64-sse3 athlon-fx amdfam10 barcelona bdver1 bdver2
bdver3 bdver4 znver1 znver2 btver1 btver2 generic native
+ i386 i486 i586 pentium lakemont pentium-mmx winchip-c6 winchip2 c3
samuel-2 c3-2 nehemiah c7 esther i686 pentiumpro pentium2 pentium3 pentium3m
pentium-m pentium4 pentium4m prescott nocona core2 nehalem corei7 westmere
sandybridge corei7-avx ivybridge core-avx-i haswell core-avx2 broadwell skylake
skylake-avx512 cannonlake icelake-client rocketlake icelake-server cascadelake
tigerlake cooperlake sapphirerapids alderlake bonnell atom silvermont slm
goldmont goldmont-plus tremont knl knm intel geode k6 k6-2 k6-3 athlon
athlon-tbird athlon-4 athlon-xp athlon-mp x86-64 x86-64-v2 x86-64-v3 x86-64-v4
eden-x2 nano nano-1000 nano-2000 nano-3000 nano-x2 eden-x4 nano-x4 k8 k8-sse3
opteron opteron-sse3 athlon64 athlon64-sse3 athlon-fx amdfam10 barcelona bdver1
bdver2 bdver3 bdver4 znver1 znver2 znver3 btver1 btver2 generic native
Known valid arguments for -mtune= option:
- generic i386 i486 pentium lakemont pentiumpro pentium4 nocona core2
nehalem sandybridge haswell bonnell silvermont goldmont goldmont-plus tremont
knl knm skylake skylake-avx512 cannonlake icelake-client icelake-server
cascadelake intel geode k6 athlon k8 amdfam10 bdver1 bdver2 bdver3 bdver4
btver1 btver2 znver1 znver2
+ generic i386 i486 pentium lakemont pentiumpro pentium4 nocona core2
nehalem sandybridge haswell bonnell silvermont goldmont goldmont-plus tremont
knl knm skylake skylake-avx512 cannonlake icelake-client icelake-server
cascadelake tigerlake cooperlake sapphirerapids alderlake rocketlake intel
geode k6 athlon k8 amdfam10 bdver1 bdver2 bdver3 bdver4 btver1 btver2 znver1
znver2 znver3
This is a gentoo distribution. There's an option to compile GCC without any
gentoo-specific patches. The compiler crashes also in this case (that is, when
using the 'stage1' xgcc compiler to build the, i guess, stage2?). That's why we
think the bug was worth reporting upstream.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12/13 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
@ 2022-10-23 23:58 ` pinskia at gcc dot gnu.org
2022-10-24 8:02 ` marxin at gcc dot gnu.org
` (17 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: pinskia at gcc dot gnu.org @ 2022-10-23 23:58 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Host|X86_64 |i?86-linux-gnu
Keywords| |ice-on-valid-code
Target Milestone|--- |10.5
Summary|ICE on Via Nehemiah with |[10/11/12/13 Regression]
|--march=native |ICE on Via Nehemiah with
| |--march=native
Build|X86_64 |i?86-linux-gnu
Target|X86_64 |i?86-linux-gnu
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12/13 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
2022-10-23 23:58 ` [Bug target/107364] [10/11/12/13 Regression] " pinskia at gcc dot gnu.org
@ 2022-10-24 8:02 ` marxin at gcc dot gnu.org
2022-10-24 13:00 ` orzel at freehackers dot org
` (16 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: marxin at gcc dot gnu.org @ 2022-10-24 8:02 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
Martin Liška <marxin at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |marxin at gcc dot gnu.org
Ever confirmed|0 |1
Status|UNCONFIRMED |ASSIGNED
Assignee|unassigned at gcc dot gnu.org |marxin at gcc dot gnu.org
Last reconfirmed| |2022-10-24
--- Comment #1 from Martin Liška <marxin at gcc dot gnu.org> ---
Can you please run the following code snippet on the machine:
$ cat cpuid.c
#include "cpuid.h"
int main()
{
int eax, ebx, ecx, edx;
__get_cpuid (0, &eax, &ebx, &ecx, &edx);
__builtin_printf ("__get_cpuid(0): eax=%ld, ebx=%ld, ecx=%ld, edx=%ld\n",
eax, ebx, ecx, edx);
__get_cpuid (1, &eax, &ebx, &ecx, &edx);
__builtin_printf ("__get_cpuid(1): eax=%ld, ebx=%ld, ecx=%ld, edx=%ld\n",
eax, ebx, ecx, edx);
}
$ gcc cpuid.c && ./a.out
and paste the output here?
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12/13 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
2022-10-23 23:58 ` [Bug target/107364] [10/11/12/13 Regression] " pinskia at gcc dot gnu.org
2022-10-24 8:02 ` marxin at gcc dot gnu.org
@ 2022-10-24 13:00 ` orzel at freehackers dot org
2022-10-24 13:36 ` marxin at gcc dot gnu.org
` (15 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: orzel at freehackers dot org @ 2022-10-24 13:00 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #2 from Thomas Capricelli <orzel at freehackers dot org> ---
Sure, easy
chopin /tmp # ./cpuid
__get_cpuid(0): eax=1, ebx=1953391939, ecx=1936487777, edx=1215460705
__get_cpuid(1): eax=1683, ebx=0, ecx=0, edx=58765629
I't not better in hexa ? :
__get_cpuid(0): eax=1, ebx=746e6543, ecx=736c7561, edx=48727561
__get_cpuid(1): eax=693, ebx=0, ecx=0, edx=380b13d
(what would be a lot less easy, is to recompile gcc.. it takes days on this
machine)
there's also this command available:
CPU 0:
vendor_id = "CentaurHauls"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0x9 (9)
stepping id = 0x3 (3)
extended family = 0x0 (0)
extended model = 0x0 (0)
(family synth) = 0x6 (6)
(model synth) = 0x9 (9)
(simple synth) = VIA C3 / Eden ESP 7000/8000/10000 (Nehemiah C5XL),
.13um
miscellaneous (1/ebx):
process local APIC physical ID = 0x0 (0)
maximum IDs for CPUs in pkg = 0x0 (0)
CLFLUSH line size = 0x0 (0)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = false
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = false
MCE: machine check exception = false
CMPXCHG8B inst. = true
APIC on chip = false
SYSENTER and SYSEXIT = false
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = false
CMOV: conditional move/compare instr = true
PAT: page attribute table = false
PSE-36: page size extension = false
PSN: processor serial number = false
CLFLUSH instruction = false
DS: debug store = false
ACPI: thermal monitor and clock ctrl = false
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = false
SS: self snoop = false
hyper-threading / multi-core supported = false
TM: therm. monitor = false
IA64 = false
PBE: pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = false
PCLMULDQ instruction = false
DTES64: 64-bit debug store = false
MONITOR/MWAIT = false
CPL-qualified debug store = false
VMX: virtual machine extensions = false
SMX: safer mode extensions = false
Enhanced Intel SpeedStep Technology = false
TM2: thermal monitor 2 = false
SSSE3 extensions = false
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = false
xTPR disable = false
PDCM: perfmon and debug = false
PCID: process context identifiers = false
DCA: direct cache access = false
SSE4.1 extensions = false
SSE4.2 extensions = false
x2APIC: extended xAPIC support = false
MOVBE instruction = false
POPCNT instruction = false
time stamp counter deadline = false
AES instruction = false
XSAVE/XSTOR states = false
OS-enabled XSAVE/XSTOR = false
AVX: advanced vector extensions = false
F16C half-precision convert instruction = false
RDRAND instruction = false
hypervisor guest status = false
extended processor signature (0x80000001/eax):
generation = 0x0 (0)
model = 0x0 (0)
stepping = 0x0 (0)
(simple synth) = unknown
extended feature flags (0x80000001/edx):
x87 FPU on chip = false
virtual-8086 mode enhancement = false
debugging extensions = false
page size extensions = false
time stamp counter = false
RDMSR and WRMSR support = false
physical address extensions = false
machine check exception = false
CMPXCHG8B inst. = false
APIC on chip = false
SYSCALL and SYSRET instructions = false
memory type range registers = false
global paging extension = false
machine check architecture = false
conditional move/compare instruction = false
page attribute table = false
page size extension = false
multiprocessing capable = false
AMD multimedia instruction extensions = false
MMX Technology = false
extended MMX = false
SSE extensions = false
AA-64 = false
3DNow! instruction extensions = false
3DNow! instructions = false
brand = "VIA Nehemiah"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x80 (128)
instruction associativity = 0x8 (8)
data # entries = 0x80 (128)
data associativity = 0x8 (8)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x20 (32)
lines per tag = 0x1 (1)
associativity = 0x4 (4)
size (KB) = 0x40 (64)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x20 (32)
lines per tag = 0x1 (1)
associativity = 0x4 (4)
size (KB) = 0x40 (64)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x20 (32)
lines per tag = 0x1 (1)
associativity = 16-way (8)
size (KB) = 0x40 (64)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
0xc0000001 0x00: eax=0x00000000
extended feature flags (0xc0000001/edx):
alternate instruction set = true
alternate instruction set enabled = false
random number generator = true
random number generator enabled = true
LongHaul MSR 0000_110Ah = true
FEMMS = false
advanced cryptography engine (ACE) = false
advanced cryptography engine (ACE)enabled = false
montgomery multiplier/hash (ACE2) = false
montgomery multiplier/hash (ACE2) enabled = false
padlock hash engine (PHE) = false
padlock hash engine (PHE) enabled = false
padlock montgomery mult. (PMM) = false
padlock montgomery mult. (PMM) enabled = false
(multi-processing synth) = none
(multi-processing method) = Generic leaf 1 no multi-threading
(uarch synth) = VIA C3, .13um
(synth) = VIA C3 / Eden ESP 7000/8000/10000 (Nehemiah C5XL), .13um
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12/13 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (2 preceding siblings ...)
2022-10-24 13:00 ` orzel at freehackers dot org
@ 2022-10-24 13:36 ` marxin at gcc dot gnu.org
2022-10-24 13:40 ` marxin at gcc dot gnu.org
` (14 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: marxin at gcc dot gnu.org @ 2022-10-24 13:36 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #3 from Martin Liška <marxin at gcc dot gnu.org> ---
Created attachment 53769
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=53769&action=edit
Tentative patch
Have a patch for the ICE. Can you please output what you see with -march=native
now? Ideally if you use --verbose argument for the GCC compiler.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12/13 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (3 preceding siblings ...)
2022-10-24 13:36 ` marxin at gcc dot gnu.org
@ 2022-10-24 13:40 ` marxin at gcc dot gnu.org
2022-10-24 18:26 ` cvs-commit at gcc dot gnu.org
` (13 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: marxin at gcc dot gnu.org @ 2022-10-24 13:40 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #4 from Martin Liška <marxin at gcc dot gnu.org> ---
> there's also this command available:
What command does produce that?
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12/13 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (4 preceding siblings ...)
2022-10-24 13:40 ` marxin at gcc dot gnu.org
@ 2022-10-24 18:26 ` cvs-commit at gcc dot gnu.org
2022-10-24 18:27 ` [Bug target/107364] [10/11/12 " marxin at gcc dot gnu.org
` (12 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2022-10-24 18:26 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Martin Liska <marxin@gcc.gnu.org>:
https://gcc.gnu.org/g:f751bf4c5d1aaa1aacfcbdec62881c5ea1175dfb
commit r13-3463-gf751bf4c5d1aaa1aacfcbdec62881c5ea1175dfb
Author: Martin Liska <mliska@suse.cz>
Date: Mon Oct 24 15:34:39 2022 +0200
x86: fix VENDOR_MAX enum value
PR target/107364
gcc/ChangeLog:
* common/config/i386/i386-cpuinfo.h (enum processor_vendor):
Reorder enum values as BUILTIN_VENDOR_MAX should not point
in the middle of the valid enum values.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (5 preceding siblings ...)
2022-10-24 18:26 ` cvs-commit at gcc dot gnu.org
@ 2022-10-24 18:27 ` marxin at gcc dot gnu.org
2022-10-24 19:52 ` orzel at freehackers dot org
` (11 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: marxin at gcc dot gnu.org @ 2022-10-24 18:27 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
Martin Liška <marxin at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Summary|[10/11/12/13 Regression] |[10/11/12 Regression] ICE
|ICE on Via Nehemiah with |on Via Nehemiah with
|--march=native |--march=native
--- Comment #6 from Martin Liška <marxin at gcc dot gnu.org> ---
Fixed on master so far.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (6 preceding siblings ...)
2022-10-24 18:27 ` [Bug target/107364] [10/11/12 " marxin at gcc dot gnu.org
@ 2022-10-24 19:52 ` orzel at freehackers dot org
2022-10-24 20:18 ` orzel at freehackers dot org
` (10 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: orzel at freehackers dot org @ 2022-10-24 19:52 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #7 from Thomas Capricelli <orzel at freehackers dot org> ---
(In reply to Martin Liška from comment #4)
> > there's also this command available:
>
> What command does produce that?
Sorry, was supposed to be in the copy/pasted text:
sys-apps/cpuid / http://www.etallen.com/cpuid.html
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (7 preceding siblings ...)
2022-10-24 19:52 ` orzel at freehackers dot org
@ 2022-10-24 20:18 ` orzel at freehackers dot org
2022-10-24 20:30 ` marxin at gcc dot gnu.org
` (9 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: orzel at freehackers dot org @ 2022-10-24 20:18 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
Thomas Capricelli <orzel at freehackers dot org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|ASSIGNED |RESOLVED
Resolution|--- |FIXED
--- Comment #8 from Thomas Capricelli <orzel at freehackers dot org> ---
(In reply to Martin Liška from comment #6)
> Fixed on master so far.
Dang, you right, i had missed that.
I didn't know that
enum .. {
...
VENDOR_OTHER,
VENDOR_CYRIX,
VENDOR_NSC,
BUILTIN_VENDOR_MAX = VENDOR_OTHER,
VENDOR_MAX
};
would assign VENDOR_MAX = VENDOR_OTHER+1, but i confirmed with a quick test.
That means that all CENTAUR/CYRIX/NSC were broken since gcc 10 and nobody
noticed until me ?? That sounds very unlikely, does it not ?
(I dont even know what NSC is)
I'm not sure, but the "wrong" commit seems to be the very large
https://github.com/gcc-mirror/gcc/commit/1890f2f0e210ef515c39728c54151372d36dd187
It's about merging duplicates cpu definition between libgcc and gcc, but it
also adds the new enum CENTAUR/CYRIX/NSC. At the wrong place.
It's rather complicated to recompile gcc on this computer, but i'll try after
next gcc release. I'm rather confident this is it.
I close it until then. Thanks !
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (8 preceding siblings ...)
2022-10-24 20:18 ` orzel at freehackers dot org
@ 2022-10-24 20:30 ` marxin at gcc dot gnu.org
2022-10-24 20:38 ` hjl.tools at gmail dot com
` (8 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: marxin at gcc dot gnu.org @ 2022-10-24 20:30 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
Martin Liška <marxin at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |hjl at gcc dot gnu.org
--- Comment #9 from Martin Liška <marxin at gcc dot gnu.org> ---
...
> That means that all CENTAUR/CYRIX/NSC were broken since gcc 10 and nobody
> noticed until me ?? That sounds very unlikely, does it not ?
Yes, you are the first one who noticed!
>
> (I dont even know what NSC is)
>
> I'm not sure, but the "wrong" commit seems to be the very large
>
> https://github.com/gcc-mirror/gcc/commit/
> 1890f2f0e210ef515c39728c54151372d36dd187
Yep, I know about this commit.
I suspect g:6c35d16a3925958b3a22426de0cb8e04f654b6dd where e.g. sse detection
is unified:
- has_sse = edx & bit_SSE;
and rather:
+ else if (has_feature (FEATURE_SSE2)
is used. And then in g:792317cc777123b9cac8fc9a70fc85b01a3d7a0f newly added
get_available_features
which does the ISA features detection is called only for AMD and Intel CPUs :/
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (9 preceding siblings ...)
2022-10-24 20:30 ` marxin at gcc dot gnu.org
@ 2022-10-24 20:38 ` hjl.tools at gmail dot com
2022-10-24 20:46 ` orzel at freehackers dot org
` (7 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: hjl.tools at gmail dot com @ 2022-10-24 20:38 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #10 from H.J. Lu <hjl.tools at gmail dot com> ---
The fix should be backported to release branches.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (10 preceding siblings ...)
2022-10-24 20:38 ` hjl.tools at gmail dot com
@ 2022-10-24 20:46 ` orzel at freehackers dot org
2022-10-25 3:55 ` cvs-commit at gcc dot gnu.org
` (6 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: orzel at freehackers dot org @ 2022-10-24 20:46 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
Thomas Capricelli <orzel at freehackers dot org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Version|10.0 |unknown
--- Comment #11 from Thomas Capricelli <orzel at freehackers dot org> ---
(In reply to Thomas Capricelli from comment #8)
> (I dont even know what NSC is)
Oh, it's "NSC Geode". I thought Geode would be branded as 'AMD'. Although it
was originally from Cyrix. What a mess :)
I have one lying somewhere. I'll check on occasion.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (11 preceding siblings ...)
2022-10-24 20:46 ` orzel at freehackers dot org
@ 2022-10-25 3:55 ` cvs-commit at gcc dot gnu.org
2022-10-25 3:56 ` cvs-commit at gcc dot gnu.org
` (5 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2022-10-25 3:55 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #12 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-11 branch has been updated by Martin Liska
<marxin@gcc.gnu.org>:
https://gcc.gnu.org/g:d771f7c8fb780243abf5a333435cde05c20f017d
commit r11-10334-gd771f7c8fb780243abf5a333435cde05c20f017d
Author: Martin Liska <mliska@suse.cz>
Date: Mon Oct 24 15:34:39 2022 +0200
x86: fix VENDOR_MAX enum value
PR target/107364
gcc/ChangeLog:
* common/config/i386/i386-cpuinfo.h (enum processor_vendor):
Reorder enum values as BUILTIN_VENDOR_MAX should not point
in the middle of the valid enum values.
(cherry picked from commit f751bf4c5d1aaa1aacfcbdec62881c5ea1175dfb)
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (12 preceding siblings ...)
2022-10-25 3:55 ` cvs-commit at gcc dot gnu.org
@ 2022-10-25 3:56 ` cvs-commit at gcc dot gnu.org
2022-10-25 4:18 ` cvs-commit at gcc dot gnu.org
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From: cvs-commit at gcc dot gnu.org @ 2022-10-25 3:56 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #13 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by Martin Liska
<marxin@gcc.gnu.org>:
https://gcc.gnu.org/g:4db0753959dc7aeff567c689be6c4eb611aea8ee
commit r12-8863-g4db0753959dc7aeff567c689be6c4eb611aea8ee
Author: Martin Liska <mliska@suse.cz>
Date: Mon Oct 24 15:34:39 2022 +0200
x86: fix VENDOR_MAX enum value
PR target/107364
gcc/ChangeLog:
* common/config/i386/i386-cpuinfo.h (enum processor_vendor):
Reorder enum values as BUILTIN_VENDOR_MAX should not point
in the middle of the valid enum values.
(cherry picked from commit f751bf4c5d1aaa1aacfcbdec62881c5ea1175dfb)
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (13 preceding siblings ...)
2022-10-25 3:56 ` cvs-commit at gcc dot gnu.org
@ 2022-10-25 4:18 ` cvs-commit at gcc dot gnu.org
2022-10-25 4:24 ` cvs-commit at gcc dot gnu.org
` (3 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2022-10-25 4:18 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #14 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Martin Liska
<marxin@gcc.gnu.org>:
https://gcc.gnu.org/g:7cee6ad35eb0fd9f79100e5fa7b6560b8ea7fe10
commit r10-11058-g7cee6ad35eb0fd9f79100e5fa7b6560b8ea7fe10
Author: Martin Liska <mliska@suse.cz>
Date: Mon Oct 24 15:34:39 2022 +0200
x86: fix VENDOR_MAX enum value
PR target/107364
gcc/ChangeLog:
* common/config/i386/i386-cpuinfo.h (enum processor_vendor):
Reorder enum values as BUILTIN_VENDOR_MAX should not point
in the middle of the valid enum values.
(cherry picked from commit f751bf4c5d1aaa1aacfcbdec62881c5ea1175dfb)
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (14 preceding siblings ...)
2022-10-25 4:18 ` cvs-commit at gcc dot gnu.org
@ 2022-10-25 4:24 ` cvs-commit at gcc dot gnu.org
2022-10-25 4:24 ` cvs-commit at gcc dot gnu.org
` (2 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2022-10-25 4:24 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #15 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Martin Liska <marxin@gcc.gnu.org>:
https://gcc.gnu.org/g:f3f000b7689ce9eb6364808072025672af1e4e1b
commit r13-3472-gf3f000b7689ce9eb6364808072025672af1e4e1b
Author: Martin Liska <mliska@suse.cz>
Date: Tue Oct 25 06:16:03 2022 +0200
i386: fix pedantic warning
PR target/107364
gcc/ChangeLog:
* common/config/i386/i386-cpuinfo.h (enum processor_vendor):
Fix pedantic warning.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (15 preceding siblings ...)
2022-10-25 4:24 ` cvs-commit at gcc dot gnu.org
@ 2022-10-25 4:24 ` cvs-commit at gcc dot gnu.org
2022-10-25 4:25 ` cvs-commit at gcc dot gnu.org
2022-10-25 4:29 ` marxin at gcc dot gnu.org
18 siblings, 0 replies; 20+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2022-10-25 4:24 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #16 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-11 branch has been updated by Martin Liska
<marxin@gcc.gnu.org>:
https://gcc.gnu.org/g:6b01a5dca7f766f1bfeff969e8f089c6992aef88
commit r11-10335-g6b01a5dca7f766f1bfeff969e8f089c6992aef88
Author: Martin Liska <mliska@suse.cz>
Date: Tue Oct 25 06:16:03 2022 +0200
i386: fix pedantic warning
PR target/107364
gcc/ChangeLog:
* common/config/i386/i386-cpuinfo.h (enum processor_vendor):
Fix pedantic warning.
(cherry picked from commit f3f000b7689ce9eb6364808072025672af1e4e1b)
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (16 preceding siblings ...)
2022-10-25 4:24 ` cvs-commit at gcc dot gnu.org
@ 2022-10-25 4:25 ` cvs-commit at gcc dot gnu.org
2022-10-25 4:29 ` marxin at gcc dot gnu.org
18 siblings, 0 replies; 20+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2022-10-25 4:25 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #17 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by Martin Liska
<marxin@gcc.gnu.org>:
https://gcc.gnu.org/g:2a2093a9d40b5bc97b970fca9c02ff64056f3ed0
commit r12-8864-g2a2093a9d40b5bc97b970fca9c02ff64056f3ed0
Author: Martin Liska <mliska@suse.cz>
Date: Tue Oct 25 06:16:03 2022 +0200
i386: fix pedantic warning
PR target/107364
gcc/ChangeLog:
* common/config/i386/i386-cpuinfo.h (enum processor_vendor):
Fix pedantic warning.
(cherry picked from commit f3f000b7689ce9eb6364808072025672af1e4e1b)
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Bug target/107364] [10/11/12 Regression] ICE on Via Nehemiah with --march=native
2022-10-23 10:47 [Bug c/107364] New: ICE on Via Nehemiah with --march=native orzel at freehackers dot org
` (17 preceding siblings ...)
2022-10-25 4:25 ` cvs-commit at gcc dot gnu.org
@ 2022-10-25 4:29 ` marxin at gcc dot gnu.org
18 siblings, 0 replies; 20+ messages in thread
From: marxin at gcc dot gnu.org @ 2022-10-25 4:29 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364
--- Comment #18 from Martin Liška <marxin at gcc dot gnu.org> ---
(In reply to H.J. Lu from comment #10)
> The fix should be backported to release branches.
Done.
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-10-25 4:29 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
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